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60 lines
1.6 KiB
60 lines
1.6 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* cpcihp_zt5550.h |
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* |
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* Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions |
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* |
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* Copyright 2002 SOMA Networks, Inc. |
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* Copyright 2001 Intel San Luis Obispo |
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* Copyright 2000,2001 MontaVista Software Inc. |
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* |
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* Send feedback to <[email protected]> |
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*/ |
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#ifndef _CPCIHP_ZT5550_H |
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#define _CPCIHP_ZT5550_H |
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/* Direct registers */ |
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#define CSR_HCINDEX 0x00 |
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#define CSR_HCDATA 0x04 |
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#define CSR_INTSTAT 0x08 |
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#define CSR_INTMASK 0x09 |
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#define CSR_CNT0CMD 0x0C |
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#define CSR_CNT1CMD 0x0E |
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#define CSR_CNT0 0x10 |
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#define CSR_CNT1 0x14 |
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/* Masks for interrupt bits in CSR_INTMASK direct register */ |
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#define CNT0_INT_MASK 0x01 |
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#define CNT1_INT_MASK 0x02 |
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#define ENUM_INT_MASK 0x04 |
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#define ALL_DIRECT_INTS_MASK 0x07 |
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/* Indexed registers (through CSR_INDEX, CSR_DATA) */ |
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#define HC_INT_MASK_REG 0x04 |
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#define HC_STATUS_REG 0x08 |
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#define HC_CMD_REG 0x0C |
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#define ARB_CONFIG_GNT_REG 0x10 |
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#define ARB_CONFIG_CFG_REG 0x12 |
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#define ARB_CONFIG_REG 0x10 |
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#define ISOL_CONFIG_REG 0x18 |
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#define FAULT_STATUS_REG 0x20 |
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#define FAULT_CONFIG_REG 0x24 |
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#define WD_CONFIG_REG 0x2C |
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#define HC_DIAG_REG 0x30 |
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#define SERIAL_COMM_REG 0x34 |
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#define SERIAL_OUT_REG 0x38 |
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#define SERIAL_IN_REG 0x3C |
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/* Masks for interrupt bits in HC_INT_MASK_REG indexed register */ |
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#define SERIAL_INT_MASK 0x01 |
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#define FAULT_INT_MASK 0x02 |
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#define HCF_INT_MASK 0x04 |
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#define ALL_INDEXED_INTS_MASK 0x07 |
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/* Digital I/O port storing ENUM# */ |
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#define ENUM_PORT 0xE1 |
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/* Mask to get to the ENUM# bit on the bus */ |
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#define ENUM_MASK 0x40 |
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#endif /* _CPCIHP_ZT5550_H */
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