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556 lines
13 KiB
556 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* BRIEF MODULE DESCRIPTION |
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* PCI init for Ralink RT2880 solution |
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* |
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* Copyright 2007 Ralink Inc. ([email protected]) |
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* |
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* May 2007 Bruce Chang |
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* Initial Release |
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* |
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* May 2009 Bruce Chang |
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* support RT2880/RT3883 PCIe |
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* |
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* May 2011 Bruce Chang |
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* support RT6855/MT7620 PCIe |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_pci.h> |
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#include <linux/of_platform.h> |
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#include <linux/pci.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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#include <linux/sys_soc.h> |
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|
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/* MediaTek-specific configuration registers */ |
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#define PCIE_FTS_NUM 0x70c |
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#define PCIE_FTS_NUM_MASK GENMASK(15, 8) |
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#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8) |
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|
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/* Host-PCI bridge registers */ |
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#define RALINK_PCI_PCICFG_ADDR 0x0000 |
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#define RALINK_PCI_PCIMSK_ADDR 0x000c |
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#define RALINK_PCI_CONFIG_ADDR 0x0020 |
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#define RALINK_PCI_CONFIG_DATA 0x0024 |
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#define RALINK_PCI_MEMBASE 0x0028 |
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#define RALINK_PCI_IOBASE 0x002c |
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|
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/* PCIe RC control registers */ |
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#define RALINK_PCI_ID 0x0030 |
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#define RALINK_PCI_CLASS 0x0034 |
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#define RALINK_PCI_SUBID 0x0038 |
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#define RALINK_PCI_STATUS 0x0050 |
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|
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/* Some definition values */ |
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#define PCIE_REVISION_ID BIT(0) |
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#define PCIE_CLASS_CODE (0x60400 << 8) |
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#define PCIE_BAR_MAP_MAX GENMASK(30, 16) |
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#define PCIE_BAR_ENABLE BIT(0) |
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#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) |
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#define PCIE_PORT_LINKUP BIT(0) |
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#define PCIE_PORT_CNT 3 |
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#define PERST_DELAY_MS 100 |
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/** |
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* struct mt7621_pcie_port - PCIe port information |
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* @base: I/O mapped register base |
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* @list: port list |
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* @pcie: pointer to PCIe host info |
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* @clk: pointer to the port clock gate |
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* @phy: pointer to PHY control block |
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* @pcie_rst: pointer to port reset control |
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* @gpio_rst: gpio reset |
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* @slot: port slot |
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* @enabled: indicates if port is enabled |
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*/ |
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struct mt7621_pcie_port { |
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void __iomem *base; |
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struct list_head list; |
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struct mt7621_pcie *pcie; |
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struct clk *clk; |
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struct phy *phy; |
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struct reset_control *pcie_rst; |
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struct gpio_desc *gpio_rst; |
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u32 slot; |
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bool enabled; |
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}; |
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/** |
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* struct mt7621_pcie - PCIe host information |
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* @base: IO Mapped Register Base |
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* @dev: Pointer to PCIe device |
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* @ports: pointer to PCIe port information |
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* @resets_inverted: depends on chip revision |
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* reset lines are inverted. |
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*/ |
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struct mt7621_pcie { |
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struct device *dev; |
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void __iomem *base; |
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struct list_head ports; |
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bool resets_inverted; |
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}; |
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static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) |
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{ |
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return readl_relaxed(pcie->base + reg); |
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} |
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static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) |
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{ |
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writel_relaxed(val, pcie->base + reg); |
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} |
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static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) |
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{ |
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return readl_relaxed(port->base + reg); |
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} |
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static inline void pcie_port_write(struct mt7621_pcie_port *port, |
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u32 val, u32 reg) |
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{ |
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writel_relaxed(val, port->base + reg); |
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} |
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static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot, |
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unsigned int func, unsigned int where) |
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{ |
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return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | |
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(func << 8) | (where & 0xfc) | 0x80000000; |
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} |
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static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, |
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unsigned int devfn, int where) |
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{ |
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struct mt7621_pcie *pcie = bus->sysdata; |
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u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn), |
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PCI_FUNC(devfn), where); |
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writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); |
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return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); |
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} |
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static struct pci_ops mt7621_pcie_ops = { |
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.map_bus = mt7621_pcie_map_bus, |
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.read = pci_generic_config_read, |
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.write = pci_generic_config_write, |
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}; |
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static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) |
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{ |
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u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg); |
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); |
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return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); |
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} |
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static void write_config(struct mt7621_pcie *pcie, unsigned int dev, |
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u32 reg, u32 val) |
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{ |
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u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg); |
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); |
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); |
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} |
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static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port) |
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{ |
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if (port->gpio_rst) |
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gpiod_set_value(port->gpio_rst, 1); |
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} |
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static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port) |
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{ |
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if (port->gpio_rst) |
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gpiod_set_value(port->gpio_rst, 0); |
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} |
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static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port) |
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{ |
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return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0; |
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} |
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static inline void mt7621_control_assert(struct mt7621_pcie_port *port) |
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{ |
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struct mt7621_pcie *pcie = port->pcie; |
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if (pcie->resets_inverted) |
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reset_control_assert(port->pcie_rst); |
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else |
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reset_control_deassert(port->pcie_rst); |
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} |
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static inline void mt7621_control_deassert(struct mt7621_pcie_port *port) |
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{ |
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struct mt7621_pcie *pcie = port->pcie; |
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if (pcie->resets_inverted) |
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reset_control_deassert(port->pcie_rst); |
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else |
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reset_control_assert(port->pcie_rst); |
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} |
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static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, |
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struct device_node *node, |
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int slot) |
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{ |
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struct mt7621_pcie_port *port; |
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struct device *dev = pcie->dev; |
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struct platform_device *pdev = to_platform_device(dev); |
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char name[10]; |
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int err; |
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); |
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if (!port) |
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return -ENOMEM; |
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port->base = devm_platform_ioremap_resource(pdev, slot + 1); |
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if (IS_ERR(port->base)) |
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return PTR_ERR(port->base); |
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port->clk = devm_get_clk_from_child(dev, node, NULL); |
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if (IS_ERR(port->clk)) { |
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dev_err(dev, "failed to get pcie%d clock\n", slot); |
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return PTR_ERR(port->clk); |
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} |
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port->pcie_rst = of_reset_control_get_exclusive(node, NULL); |
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if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) { |
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dev_err(dev, "failed to get pcie%d reset control\n", slot); |
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return PTR_ERR(port->pcie_rst); |
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} |
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snprintf(name, sizeof(name), "pcie-phy%d", slot); |
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port->phy = devm_of_phy_get(dev, node, name); |
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if (IS_ERR(port->phy)) { |
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dev_err(dev, "failed to get pcie-phy%d\n", slot); |
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err = PTR_ERR(port->phy); |
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goto remove_reset; |
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} |
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port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, |
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GPIOD_OUT_LOW); |
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if (IS_ERR(port->gpio_rst)) { |
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dev_err(dev, "failed to get GPIO for PCIe%d\n", slot); |
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err = PTR_ERR(port->gpio_rst); |
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goto remove_reset; |
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} |
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port->slot = slot; |
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port->pcie = pcie; |
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INIT_LIST_HEAD(&port->list); |
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list_add_tail(&port->list, &pcie->ports); |
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return 0; |
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remove_reset: |
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reset_control_put(port->pcie_rst); |
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return err; |
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} |
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static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) |
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{ |
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struct device *dev = pcie->dev; |
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struct platform_device *pdev = to_platform_device(dev); |
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struct device_node *node = dev->of_node, *child; |
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int err; |
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pcie->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(pcie->base)) |
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return PTR_ERR(pcie->base); |
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for_each_available_child_of_node(node, child) { |
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int slot; |
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err = of_pci_get_devfn(child); |
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if (err < 0) { |
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of_node_put(child); |
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dev_err(dev, "failed to parse devfn: %d\n", err); |
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return err; |
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} |
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slot = PCI_SLOT(err); |
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err = mt7621_pcie_parse_port(pcie, child, slot); |
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if (err) { |
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of_node_put(child); |
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return err; |
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} |
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} |
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return 0; |
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} |
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static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) |
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{ |
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struct mt7621_pcie *pcie = port->pcie; |
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struct device *dev = pcie->dev; |
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u32 slot = port->slot; |
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int err; |
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err = phy_init(port->phy); |
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if (err) { |
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dev_err(dev, "failed to initialize port%d phy\n", slot); |
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return err; |
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} |
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err = phy_power_on(port->phy); |
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if (err) { |
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dev_err(dev, "failed to power on port%d phy\n", slot); |
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phy_exit(port->phy); |
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return err; |
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} |
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port->enabled = true; |
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return 0; |
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} |
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static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie) |
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{ |
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struct mt7621_pcie_port *port; |
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list_for_each_entry(port, &pcie->ports, list) { |
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/* PCIe RC reset assert */ |
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mt7621_control_assert(port); |
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/* PCIe EP reset assert */ |
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mt7621_rst_gpio_pcie_assert(port); |
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} |
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msleep(PERST_DELAY_MS); |
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} |
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static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) |
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{ |
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struct mt7621_pcie_port *port; |
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list_for_each_entry(port, &pcie->ports, list) |
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mt7621_control_deassert(port); |
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} |
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static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie) |
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{ |
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struct mt7621_pcie_port *port; |
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list_for_each_entry(port, &pcie->ports, list) |
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mt7621_rst_gpio_pcie_deassert(port); |
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msleep(PERST_DELAY_MS); |
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} |
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static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie) |
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{ |
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struct device *dev = pcie->dev; |
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struct mt7621_pcie_port *port, *tmp; |
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u8 num_disabled = 0; |
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int err; |
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mt7621_pcie_reset_assert(pcie); |
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mt7621_pcie_reset_rc_deassert(pcie); |
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list_for_each_entry_safe(port, tmp, &pcie->ports, list) { |
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u32 slot = port->slot; |
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if (slot == 1) { |
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port->enabled = true; |
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continue; |
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} |
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err = mt7621_pcie_init_port(port); |
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if (err) { |
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dev_err(dev, "initializing port %d failed\n", slot); |
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list_del(&port->list); |
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} |
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} |
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mt7621_pcie_reset_ep_deassert(pcie); |
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tmp = NULL; |
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list_for_each_entry(port, &pcie->ports, list) { |
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u32 slot = port->slot; |
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if (!mt7621_pcie_port_is_linkup(port)) { |
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", |
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slot); |
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mt7621_control_assert(port); |
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port->enabled = false; |
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num_disabled++; |
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if (slot == 0) { |
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tmp = port; |
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continue; |
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} |
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if (slot == 1 && tmp && !tmp->enabled) |
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phy_power_off(tmp->phy); |
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} |
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} |
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return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV; |
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} |
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static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) |
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{ |
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struct mt7621_pcie *pcie = port->pcie; |
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u32 slot = port->slot; |
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u32 val; |
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/* enable pcie interrupt */ |
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); |
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val |= PCIE_PORT_INT_EN(slot); |
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); |
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/* map 2G DDR region */ |
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pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, |
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PCI_BASE_ADDRESS_0); |
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/* configure class code and revision ID */ |
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pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID, |
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RALINK_PCI_CLASS); |
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/* configure RC FTS number to 250 when it leaves L0s */ |
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val = read_config(pcie, slot, PCIE_FTS_NUM); |
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val &= ~PCIE_FTS_NUM_MASK; |
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val |= PCIE_FTS_NUM_L0(0x50); |
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write_config(pcie, slot, PCIE_FTS_NUM, val); |
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} |
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static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) |
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{ |
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struct mt7621_pcie *pcie = pci_host_bridge_priv(host); |
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struct device *dev = pcie->dev; |
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struct mt7621_pcie_port *port; |
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struct resource_entry *entry; |
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int err; |
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entry = resource_list_first_type(&host->windows, IORESOURCE_IO); |
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if (!entry) { |
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dev_err(dev, "cannot get io resource\n"); |
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return -EINVAL; |
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} |
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/* Setup MEMWIN and IOWIN */ |
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pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); |
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pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); |
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list_for_each_entry(port, &pcie->ports, list) { |
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if (port->enabled) { |
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err = clk_prepare_enable(port->clk); |
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if (err) { |
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dev_err(dev, "enabling clk pcie%d\n", |
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port->slot); |
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return err; |
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} |
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mt7621_pcie_enable_port(port); |
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dev_info(dev, "PCIE%d enabled\n", port->slot); |
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} |
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} |
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return 0; |
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} |
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static int mt7621_pcie_register_host(struct pci_host_bridge *host) |
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{ |
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struct mt7621_pcie *pcie = pci_host_bridge_priv(host); |
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host->ops = &mt7621_pcie_ops; |
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host->sysdata = pcie; |
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return pci_host_probe(host); |
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} |
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static const struct soc_device_attribute mt7621_pcie_quirks_match[] = { |
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{ .soc_id = "mt7621", .revision = "E2" } |
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}; |
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static int mt7621_pcie_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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const struct soc_device_attribute *attr; |
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struct mt7621_pcie_port *port; |
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struct mt7621_pcie *pcie; |
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struct pci_host_bridge *bridge; |
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int err; |
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if (!dev->of_node) |
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return -ENODEV; |
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); |
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if (!bridge) |
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return -ENOMEM; |
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pcie = pci_host_bridge_priv(bridge); |
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pcie->dev = dev; |
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platform_set_drvdata(pdev, pcie); |
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INIT_LIST_HEAD(&pcie->ports); |
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attr = soc_device_match(mt7621_pcie_quirks_match); |
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if (attr) |
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pcie->resets_inverted = true; |
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err = mt7621_pcie_parse_dt(pcie); |
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if (err) { |
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dev_err(dev, "parsing DT failed\n"); |
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return err; |
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} |
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err = mt7621_pcie_init_ports(pcie); |
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if (err) { |
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dev_err(dev, "nothing connected in virtual bridges\n"); |
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return 0; |
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} |
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err = mt7621_pcie_enable_ports(bridge); |
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if (err) { |
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dev_err(dev, "error enabling pcie ports\n"); |
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goto remove_resets; |
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} |
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return mt7621_pcie_register_host(bridge); |
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remove_resets: |
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list_for_each_entry(port, &pcie->ports, list) |
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reset_control_put(port->pcie_rst); |
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return err; |
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} |
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static int mt7621_pcie_remove(struct platform_device *pdev) |
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{ |
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struct mt7621_pcie *pcie = platform_get_drvdata(pdev); |
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struct mt7621_pcie_port *port; |
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list_for_each_entry(port, &pcie->ports, list) |
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reset_control_put(port->pcie_rst); |
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return 0; |
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} |
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static const struct of_device_id mt7621_pcie_ids[] = { |
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{ .compatible = "mediatek,mt7621-pci" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, mt7621_pcie_ids); |
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static struct platform_driver mt7621_pcie_driver = { |
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.probe = mt7621_pcie_probe, |
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.remove = mt7621_pcie_remove, |
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.driver = { |
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.name = "mt7621-pci", |
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.of_match_table = mt7621_pcie_ids, |
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}, |
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}; |
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builtin_platform_driver(mt7621_pcie_driver); |
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MODULE_LICENSE("GPL v2");
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