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552 lines
19 KiB
552 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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// Copyright (c) 2017 Cadence |
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// Cadence PCIe controller driver. |
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// Author: Cyrille Pitchen <[email protected]> |
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#ifndef _PCIE_CADENCE_H |
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#define _PCIE_CADENCE_H |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/pci-epf.h> |
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#include <linux/phy/phy.h> |
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/* Parameters for the waiting for link up routine */ |
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#define LINK_WAIT_MAX_RETRIES 10 |
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#define LINK_WAIT_USLEEP_MIN 90000 |
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#define LINK_WAIT_USLEEP_MAX 100000 |
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/* |
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* Local Management Registers |
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*/ |
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#define CDNS_PCIE_LM_BASE 0x00100000 |
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/* Vendor ID Register */ |
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#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) |
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#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) |
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#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 |
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#define CDNS_PCIE_LM_ID_VENDOR(vid) \ |
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(((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) |
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#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) |
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#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 |
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#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ |
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(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) |
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/* Root Port Requestor ID Register */ |
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#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) |
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#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) |
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#define CDNS_PCIE_LM_RP_RID_SHIFT 0 |
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#define CDNS_PCIE_LM_RP_RID_(rid) \ |
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(((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) |
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/* Endpoint Bus and Device Number Register */ |
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#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) |
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#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) |
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#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 |
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#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) |
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#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 |
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/* Endpoint Function f BAR b Configuration Registers */ |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ |
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(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ |
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(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ |
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(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) |
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#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ |
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(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) |
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#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ |
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(CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) |
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#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ |
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(CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ |
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(GENMASK(4, 0) << ((b) * 8)) |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ |
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(((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ |
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(GENMASK(7, 5) << ((b) * 8)) |
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ |
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(((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) |
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/* Endpoint Function Configuration Register */ |
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#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) |
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/* Root Complex BAR Configuration Register */ |
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#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ |
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(((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ |
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(((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ |
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(((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ |
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(((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 |
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#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 |
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#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) |
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#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) |
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/* BAR control values applicable to both Endpoint Function and Root Complex */ |
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 |
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 |
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 |
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 |
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 |
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 |
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#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ |
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(CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) |
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#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ |
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(CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) |
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#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ |
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(CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) |
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#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ |
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(CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) |
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#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ |
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(CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) |
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#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ |
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(CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) |
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#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ |
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(((aperture) - 2) << ((bar) * 8)) |
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/* |
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* Endpoint Function Registers (PCI configuration space for endpoint functions) |
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*/ |
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#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) |
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#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 |
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#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 |
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#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 |
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/* |
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* Root Port Registers (PCI configuration space for the root port function) |
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*/ |
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#define CDNS_PCIE_RP_BASE 0x00200000 |
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#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 |
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/* |
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* Address Translation Registers |
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*/ |
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#define CDNS_PCIE_AT_BASE 0x00400000 |
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/* Region r Outbound AXI to PCIe Address Translation Register 0 */ |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ |
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(CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ |
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(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ |
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(((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ |
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(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) |
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/* Region r Outbound AXI to PCIe Address Translation Register 1 */ |
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ |
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(CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) |
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/* Region r Outbound PCIe Descriptor Register 0 */ |
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#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ |
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(CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd |
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/* Bit 23 MUST be set in RC mode. */ |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) |
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#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ |
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(((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) |
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/* Region r Outbound PCIe Descriptor Register 1 */ |
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#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ |
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(CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) |
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#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) |
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#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ |
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((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) |
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/* Region r AXI Region Base Address Register 0 */ |
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ |
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(CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) |
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) |
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ |
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(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) |
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/* Region r AXI Region Base Address Register 1 */ |
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ |
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(CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) |
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/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ |
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ |
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(CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) |
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) |
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ |
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(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) |
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ |
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(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) |
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/* AXI link down register */ |
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#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) |
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/* LTSSM Capabilities register */ |
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#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) |
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#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) |
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#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 |
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#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ |
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(((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ |
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CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) |
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enum cdns_pcie_rp_bar { |
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RP_BAR_UNDEFINED = -1, |
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RP_BAR0, |
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RP_BAR1, |
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RP_NO_BAR |
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}; |
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#define CDNS_PCIE_RP_MAX_IB 0x3 |
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#define CDNS_PCIE_MAX_OB 32 |
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struct cdns_pcie_rp_ib_bar { |
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u64 size; |
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bool free; |
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}; |
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/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ |
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#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ |
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(CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) |
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#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ |
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(CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) |
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/* Normal/Vendor specific message access: offset inside some outbound region */ |
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#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) |
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#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ |
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(((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) |
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#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) |
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#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ |
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(((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) |
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#define CDNS_PCIE_MSG_NO_DATA BIT(16) |
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struct cdns_pcie; |
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enum cdns_pcie_msg_code { |
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MSG_CODE_ASSERT_INTA = 0x20, |
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MSG_CODE_ASSERT_INTB = 0x21, |
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MSG_CODE_ASSERT_INTC = 0x22, |
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MSG_CODE_ASSERT_INTD = 0x23, |
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MSG_CODE_DEASSERT_INTA = 0x24, |
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MSG_CODE_DEASSERT_INTB = 0x25, |
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MSG_CODE_DEASSERT_INTC = 0x26, |
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MSG_CODE_DEASSERT_INTD = 0x27, |
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}; |
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enum cdns_pcie_msg_routing { |
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/* Route to Root Complex */ |
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MSG_ROUTING_TO_RC, |
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/* Use Address Routing */ |
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MSG_ROUTING_BY_ADDR, |
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/* Use ID Routing */ |
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MSG_ROUTING_BY_ID, |
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/* Route as Broadcast Message from Root Complex */ |
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MSG_ROUTING_BCAST, |
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/* Local message; terminate at receiver (INTx messages) */ |
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MSG_ROUTING_LOCAL, |
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/* Gather & route to Root Complex (PME_TO_Ack message) */ |
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MSG_ROUTING_GATHER, |
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}; |
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struct cdns_pcie_ops { |
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int (*start_link)(struct cdns_pcie *pcie); |
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void (*stop_link)(struct cdns_pcie *pcie); |
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bool (*link_up)(struct cdns_pcie *pcie); |
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u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); |
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}; |
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/** |
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* struct cdns_pcie - private data for Cadence PCIe controller drivers |
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* @reg_base: IO mapped register base |
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* @mem_res: start/end offsets in the physical system memory to map PCI accesses |
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* @dev: PCIe controller |
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* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. |
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* @phy_count: number of supported PHY devices |
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* @phy: list of pointers to specific PHY control blocks |
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* @link: list of pointers to corresponding device link representations |
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* @ops: Platform-specific ops to control various inputs from Cadence PCIe |
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* wrapper |
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*/ |
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struct cdns_pcie { |
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void __iomem *reg_base; |
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struct resource *mem_res; |
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struct device *dev; |
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bool is_rc; |
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int phy_count; |
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struct phy **phy; |
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struct device_link **link; |
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const struct cdns_pcie_ops *ops; |
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}; |
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/** |
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* struct cdns_pcie_rc - private data for this PCIe Root Complex driver |
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* @pcie: Cadence PCIe controller |
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* @dev: pointer to PCIe device |
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* @cfg_res: start/end offsets in the physical system memory to map PCI |
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* configuration space accesses |
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* @cfg_base: IO mapped window to access the PCI configuration space of a |
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* single function at a time |
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* @vendor_id: PCI vendor ID |
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* @device_id: PCI device ID |
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* @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or |
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* available |
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* @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 |
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* @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk |
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*/ |
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struct cdns_pcie_rc { |
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struct cdns_pcie pcie; |
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struct resource *cfg_res; |
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void __iomem *cfg_base; |
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u32 vendor_id; |
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u32 device_id; |
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bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; |
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unsigned int quirk_retrain_flag:1; |
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unsigned int quirk_detect_quiet_flag:1; |
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}; |
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/** |
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* struct cdns_pcie_epf - Structure to hold info about endpoint function |
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* @epf: Info about virtual functions attached to the physical function |
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* @epf_bar: reference to the pci_epf_bar for the six Base Address Registers |
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*/ |
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struct cdns_pcie_epf { |
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struct cdns_pcie_epf *epf; |
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struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; |
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}; |
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/** |
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* struct cdns_pcie_ep - private data for this PCIe endpoint controller driver |
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* @pcie: Cadence PCIe controller |
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* @max_regions: maximum number of regions supported by hardware |
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* @ob_region_map: bitmask of mapped outbound regions |
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* @ob_addr: base addresses in the AXI bus where the outbound regions start |
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* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ |
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* dedicated outbound regions is mapped. |
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* @irq_cpu_addr: base address in the CPU space where a write access triggers |
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* the sending of a memory write (MSI) / normal message (legacy |
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* IRQ) TLP through the PCIe bus. |
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* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ |
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* dedicated outbound region. |
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* @irq_pci_fn: the latest PCI function that has updated the mapping of |
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* the MSI/legacy IRQ dedicated outbound region. |
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* @irq_pending: bitmask of asserted legacy IRQs. |
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* @lock: spin lock to disable interrupts while modifying PCIe controller |
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* registers fields (RMW) accessible by both remote RC and EP to |
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* minimize time between read and write |
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* @epf: Structure to hold info about endpoint function |
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* @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk |
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*/ |
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struct cdns_pcie_ep { |
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struct cdns_pcie pcie; |
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u32 max_regions; |
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unsigned long ob_region_map; |
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phys_addr_t *ob_addr; |
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phys_addr_t irq_phys_addr; |
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void __iomem *irq_cpu_addr; |
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u64 irq_pci_addr; |
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u8 irq_pci_fn; |
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u8 irq_pending; |
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/* protect writing to PCI_STATUS while raising legacy interrupts */ |
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spinlock_t lock; |
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struct cdns_pcie_epf *epf; |
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unsigned int quirk_detect_quiet_flag:1; |
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}; |
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/* Register access */ |
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static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) |
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{ |
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writel(value, pcie->reg_base + reg); |
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} |
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static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) |
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{ |
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return readl(pcie->reg_base + reg); |
|
} |
|
|
|
static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) |
|
{ |
|
void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); |
|
unsigned int offset = (unsigned long)addr & 0x3; |
|
u32 val = readl(aligned_addr); |
|
|
|
if (!IS_ALIGNED((uintptr_t)addr, size)) { |
|
pr_warn("Address %p and size %d are not aligned\n", addr, size); |
|
return 0; |
|
} |
|
|
|
if (size > 2) |
|
return val; |
|
|
|
return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); |
|
} |
|
|
|
static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) |
|
{ |
|
void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); |
|
unsigned int offset = (unsigned long)addr & 0x3; |
|
u32 mask; |
|
u32 val; |
|
|
|
if (!IS_ALIGNED((uintptr_t)addr, size)) { |
|
pr_warn("Address %p and size %d are not aligned\n", addr, size); |
|
return; |
|
} |
|
|
|
if (size > 2) { |
|
writel(value, addr); |
|
return; |
|
} |
|
|
|
mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); |
|
val = readl(aligned_addr) & mask; |
|
val |= value << (offset * 8); |
|
writel(val, aligned_addr); |
|
} |
|
|
|
/* Root Port register access */ |
|
static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, |
|
u32 reg, u8 value) |
|
{ |
|
void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; |
|
|
|
cdns_pcie_write_sz(addr, 0x1, value); |
|
} |
|
|
|
static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, |
|
u32 reg, u16 value) |
|
{ |
|
void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; |
|
|
|
cdns_pcie_write_sz(addr, 0x2, value); |
|
} |
|
|
|
static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) |
|
{ |
|
void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; |
|
|
|
return cdns_pcie_read_sz(addr, 0x2); |
|
} |
|
|
|
/* Endpoint Function register access */ |
|
static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, |
|
u32 reg, u8 value) |
|
{ |
|
void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; |
|
|
|
cdns_pcie_write_sz(addr, 0x1, value); |
|
} |
|
|
|
static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, |
|
u32 reg, u16 value) |
|
{ |
|
void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; |
|
|
|
cdns_pcie_write_sz(addr, 0x2, value); |
|
} |
|
|
|
static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, |
|
u32 reg, u32 value) |
|
{ |
|
writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); |
|
} |
|
|
|
static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) |
|
{ |
|
void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; |
|
|
|
return cdns_pcie_read_sz(addr, 0x2); |
|
} |
|
|
|
static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) |
|
{ |
|
return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); |
|
} |
|
|
|
static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) |
|
{ |
|
if (pcie->ops->start_link) |
|
return pcie->ops->start_link(pcie); |
|
|
|
return 0; |
|
} |
|
|
|
static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) |
|
{ |
|
if (pcie->ops->stop_link) |
|
pcie->ops->stop_link(pcie); |
|
} |
|
|
|
static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) |
|
{ |
|
if (pcie->ops->link_up) |
|
return pcie->ops->link_up(pcie); |
|
|
|
return true; |
|
} |
|
|
|
#ifdef CONFIG_PCIE_CADENCE_HOST |
|
int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); |
|
void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, |
|
int where); |
|
#else |
|
static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) |
|
{ |
|
return 0; |
|
} |
|
|
|
static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, |
|
int where) |
|
{ |
|
return NULL; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_PCIE_CADENCE_EP |
|
int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); |
|
#else |
|
static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) |
|
{ |
|
return 0; |
|
} |
|
#endif |
|
|
|
void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); |
|
|
|
void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, |
|
u32 r, bool is_io, |
|
u64 cpu_addr, u64 pci_addr, size_t size); |
|
|
|
void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, |
|
u8 busnr, u8 fn, |
|
u32 r, u64 cpu_addr); |
|
|
|
void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); |
|
void cdns_pcie_disable_phy(struct cdns_pcie *pcie); |
|
int cdns_pcie_enable_phy(struct cdns_pcie *pcie); |
|
int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); |
|
extern const struct dev_pm_ops cdns_pcie_pm_ops; |
|
|
|
#endif /* _PCIE_CADENCE_H */
|
|
|