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202 lines
6.4 KiB
202 lines
6.4 KiB
/* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices |
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* |
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* Author : Liu Junliang <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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#ifndef _SR9800_H |
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#define _SR9800_H |
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/* SR9800 spec. command table on Linux Platform */ |
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/* command : Software Station Management Control Reg */ |
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#define SR_CMD_SET_SW_MII 0x06 |
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/* command : PHY Read Reg */ |
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#define SR_CMD_READ_MII_REG 0x07 |
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/* command : PHY Write Reg */ |
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#define SR_CMD_WRITE_MII_REG 0x08 |
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/* command : Hardware Station Management Control Reg */ |
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#define SR_CMD_SET_HW_MII 0x0a |
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/* command : SROM Read Reg */ |
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#define SR_CMD_READ_EEPROM 0x0b |
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/* command : SROM Write Reg */ |
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#define SR_CMD_WRITE_EEPROM 0x0c |
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/* command : SROM Write Enable Reg */ |
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#define SR_CMD_WRITE_ENABLE 0x0d |
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/* command : SROM Write Disable Reg */ |
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#define SR_CMD_WRITE_DISABLE 0x0e |
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/* command : RX Control Read Reg */ |
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#define SR_CMD_READ_RX_CTL 0x0f |
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#define SR_RX_CTL_PRO (1 << 0) |
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#define SR_RX_CTL_AMALL (1 << 1) |
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#define SR_RX_CTL_SEP (1 << 2) |
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#define SR_RX_CTL_AB (1 << 3) |
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#define SR_RX_CTL_AM (1 << 4) |
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#define SR_RX_CTL_AP (1 << 5) |
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#define SR_RX_CTL_ARP (1 << 6) |
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#define SR_RX_CTL_SO (1 << 7) |
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#define SR_RX_CTL_RH1M (1 << 8) |
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#define SR_RX_CTL_RH2M (1 << 9) |
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#define SR_RX_CTL_RH3M (1 << 10) |
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/* command : RX Control Write Reg */ |
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#define SR_CMD_WRITE_RX_CTL 0x10 |
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/* command : IPG0/IPG1/IPG2 Control Read Reg */ |
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#define SR_CMD_READ_IPG012 0x11 |
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/* command : IPG0/IPG1/IPG2 Control Write Reg */ |
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#define SR_CMD_WRITE_IPG012 0x12 |
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/* command : Node ID Read Reg */ |
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#define SR_CMD_READ_NODE_ID 0x13 |
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/* command : Node ID Write Reg */ |
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#define SR_CMD_WRITE_NODE_ID 0x14 |
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/* command : Multicast Filter Array Read Reg */ |
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#define SR_CMD_READ_MULTI_FILTER 0x15 |
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/* command : Multicast Filter Array Write Reg */ |
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#define SR_CMD_WRITE_MULTI_FILTER 0x16 |
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/* command : Eth/HomePNA PHY Address Reg */ |
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#define SR_CMD_READ_PHY_ID 0x19 |
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/* command : Medium Status Read Reg */ |
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#define SR_CMD_READ_MEDIUM_STATUS 0x1a |
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#define SR_MONITOR_LINK (1 << 1) |
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#define SR_MONITOR_MAGIC (1 << 2) |
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#define SR_MONITOR_HSFS (1 << 4) |
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/* command : Medium Status Write Reg */ |
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#define SR_CMD_WRITE_MEDIUM_MODE 0x1b |
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#define SR_MEDIUM_GM (1 << 0) |
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#define SR_MEDIUM_FD (1 << 1) |
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#define SR_MEDIUM_AC (1 << 2) |
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#define SR_MEDIUM_ENCK (1 << 3) |
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#define SR_MEDIUM_RFC (1 << 4) |
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#define SR_MEDIUM_TFC (1 << 5) |
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#define SR_MEDIUM_JFE (1 << 6) |
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#define SR_MEDIUM_PF (1 << 7) |
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#define SR_MEDIUM_RE (1 << 8) |
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#define SR_MEDIUM_PS (1 << 9) |
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#define SR_MEDIUM_RSV (1 << 10) |
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#define SR_MEDIUM_SBP (1 << 11) |
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#define SR_MEDIUM_SM (1 << 12) |
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/* command : Monitor Mode Status Read Reg */ |
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#define SR_CMD_READ_MONITOR_MODE 0x1c |
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/* command : Monitor Mode Status Write Reg */ |
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#define SR_CMD_WRITE_MONITOR_MODE 0x1d |
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/* command : GPIO Status Read Reg */ |
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#define SR_CMD_READ_GPIOS 0x1e |
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#define SR_GPIO_GPO0EN (1 << 0) /* GPIO0 Output enable */ |
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#define SR_GPIO_GPO_0 (1 << 1) /* GPIO0 Output value */ |
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#define SR_GPIO_GPO1EN (1 << 2) /* GPIO1 Output enable */ |
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#define SR_GPIO_GPO_1 (1 << 3) /* GPIO1 Output value */ |
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#define SR_GPIO_GPO2EN (1 << 4) /* GPIO2 Output enable */ |
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#define SR_GPIO_GPO_2 (1 << 5) /* GPIO2 Output value */ |
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#define SR_GPIO_RESERVED (1 << 6) /* Reserved */ |
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#define SR_GPIO_RSE (1 << 7) /* Reload serial EEPROM */ |
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/* command : GPIO Status Write Reg */ |
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#define SR_CMD_WRITE_GPIOS 0x1f |
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/* command : Eth PHY Power and Reset Control Reg */ |
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#define SR_CMD_SW_RESET 0x20 |
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#define SR_SWRESET_CLEAR 0x00 |
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#define SR_SWRESET_RR (1 << 0) |
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#define SR_SWRESET_RT (1 << 1) |
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#define SR_SWRESET_PRTE (1 << 2) |
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#define SR_SWRESET_PRL (1 << 3) |
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#define SR_SWRESET_BZ (1 << 4) |
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#define SR_SWRESET_IPRL (1 << 5) |
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#define SR_SWRESET_IPPD (1 << 6) |
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/* command : Software Interface Selection Status Read Reg */ |
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#define SR_CMD_SW_PHY_STATUS 0x21 |
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/* command : Software Interface Selection Status Write Reg */ |
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#define SR_CMD_SW_PHY_SELECT 0x22 |
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/* command : BULK in Buffer Size Reg */ |
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#define SR_CMD_BULKIN_SIZE 0x2A |
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/* command : LED_MUX Control Reg */ |
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#define SR_CMD_LED_MUX 0x70 |
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#define SR_LED_MUX_TX_ACTIVE (1 << 0) |
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#define SR_LED_MUX_RX_ACTIVE (1 << 1) |
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#define SR_LED_MUX_COLLISION (1 << 2) |
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#define SR_LED_MUX_DUP_COL (1 << 3) |
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#define SR_LED_MUX_DUP (1 << 4) |
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#define SR_LED_MUX_SPEED (1 << 5) |
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#define SR_LED_MUX_LINK_ACTIVE (1 << 6) |
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#define SR_LED_MUX_LINK (1 << 7) |
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/* Register Access Flags */ |
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#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE) |
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#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE) |
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/* Multicast Filter Array size & Max Number */ |
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#define SR_MCAST_FILTER_SIZE 8 |
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#define SR_MAX_MCAST 64 |
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/* IPG0/1/2 Default Value */ |
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#define SR9800_IPG0_DEFAULT 0x15 |
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#define SR9800_IPG1_DEFAULT 0x0c |
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#define SR9800_IPG2_DEFAULT 0x12 |
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/* Medium Status Default Mode */ |
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#define SR9800_MEDIUM_DEFAULT \ |
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(SR_MEDIUM_FD | SR_MEDIUM_RFC | \ |
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SR_MEDIUM_TFC | SR_MEDIUM_PS | \ |
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SR_MEDIUM_AC | SR_MEDIUM_RE) |
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/* RX Control Default Setting */ |
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#define SR_DEFAULT_RX_CTL \ |
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(SR_RX_CTL_SO | SR_RX_CTL_AB | SR_RX_CTL_RH1M) |
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/* EEPROM Magic Number & EEPROM Size */ |
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#define SR_EEPROM_MAGIC 0xdeadbeef |
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#define SR9800_EEPROM_LEN 0xff |
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/* SR9800 Driver Version and Driver Name */ |
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#define DRIVER_VERSION "11-Nov-2013" |
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#define DRIVER_NAME "CoreChips" |
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#define DRIVER_FLAG \ |
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(FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET) |
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/* SR9800 BULKIN Buffer Size */ |
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#define SR9800_MAX_BULKIN_2K 0 |
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#define SR9800_MAX_BULKIN_4K 1 |
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#define SR9800_MAX_BULKIN_6K 2 |
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#define SR9800_MAX_BULKIN_8K 3 |
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#define SR9800_MAX_BULKIN_16K 4 |
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#define SR9800_MAX_BULKIN_20K 5 |
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#define SR9800_MAX_BULKIN_24K 6 |
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#define SR9800_MAX_BULKIN_32K 7 |
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struct {unsigned short size, byte_cnt, threshold; } SR9800_BULKIN_SIZE[] = { |
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/* 2k */ |
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{2048, 0x8000, 0x8001}, |
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/* 4k */ |
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{4096, 0x8100, 0x8147}, |
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/* 6k */ |
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{6144, 0x8200, 0x81EB}, |
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/* 8k */ |
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{8192, 0x8300, 0x83D7}, |
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/* 16 */ |
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{16384, 0x8400, 0x851E}, |
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/* 20k */ |
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{20480, 0x8500, 0x8666}, |
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/* 24k */ |
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{24576, 0x8600, 0x87AE}, |
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/* 32k */ |
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{32768, 0x8700, 0x8A3D}, |
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}; |
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/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ |
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struct sr_data { |
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u8 multi_filter[SR_MCAST_FILTER_SIZE]; |
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u8 mac_addr[ETH_ALEN]; |
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u8 phymode; |
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u8 ledmode; |
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u8 eeprom_len; |
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}; |
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struct sr9800_int_data { |
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__le16 res1; |
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u8 link; |
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__le16 res2; |
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u8 status; |
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__le16 res3; |
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} __packed; |
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#endif /* _SR9800_H */
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