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170 lines
4.8 KiB
170 lines
4.8 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices |
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* |
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* Author : Liu Junliang <[email protected]> |
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*/ |
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#ifndef _SR9700_H |
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#define _SR9700_H |
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/* sr9700 spec. register table on Linux platform */ |
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/* Network Control Reg */ |
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#define SR_NCR 0x00 |
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#define NCR_RST (1 << 0) |
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#define NCR_LBK (3 << 1) |
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#define NCR_FDX (1 << 3) |
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#define NCR_WAKEEN (1 << 6) |
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/* Network Status Reg */ |
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#define SR_NSR 0x01 |
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#define NSR_RXRDY (1 << 0) |
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#define NSR_RXOV (1 << 1) |
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#define NSR_TX1END (1 << 2) |
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#define NSR_TX2END (1 << 3) |
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#define NSR_TXFULL (1 << 4) |
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#define NSR_WAKEST (1 << 5) |
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#define NSR_LINKST (1 << 6) |
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#define NSR_SPEED (1 << 7) |
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/* Tx Control Reg */ |
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#define SR_TCR 0x02 |
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#define TCR_CRC_DIS (1 << 1) |
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#define TCR_PAD_DIS (1 << 2) |
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#define TCR_LC_CARE (1 << 3) |
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#define TCR_CRS_CARE (1 << 4) |
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#define TCR_EXCECM (1 << 5) |
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#define TCR_LF_EN (1 << 6) |
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/* Tx Status Reg for Packet Index 1 */ |
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#define SR_TSR1 0x03 |
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#define TSR1_EC (1 << 2) |
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#define TSR1_COL (1 << 3) |
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#define TSR1_LC (1 << 4) |
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#define TSR1_NC (1 << 5) |
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#define TSR1_LOC (1 << 6) |
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#define TSR1_TLF (1 << 7) |
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/* Tx Status Reg for Packet Index 2 */ |
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#define SR_TSR2 0x04 |
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#define TSR2_EC (1 << 2) |
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#define TSR2_COL (1 << 3) |
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#define TSR2_LC (1 << 4) |
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#define TSR2_NC (1 << 5) |
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#define TSR2_LOC (1 << 6) |
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#define TSR2_TLF (1 << 7) |
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/* Rx Control Reg*/ |
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#define SR_RCR 0x05 |
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#define RCR_RXEN (1 << 0) |
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#define RCR_PRMSC (1 << 1) |
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#define RCR_RUNT (1 << 2) |
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#define RCR_ALL (1 << 3) |
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#define RCR_DIS_CRC (1 << 4) |
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#define RCR_DIS_LONG (1 << 5) |
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/* Rx Status Reg */ |
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#define SR_RSR 0x06 |
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#define RSR_AE (1 << 2) |
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#define RSR_MF (1 << 6) |
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#define RSR_RF (1 << 7) |
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/* Rx Overflow Counter Reg */ |
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#define SR_ROCR 0x07 |
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#define ROCR_ROC (0x7F << 0) |
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#define ROCR_RXFU (1 << 7) |
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/* Back Pressure Threshold Reg */ |
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#define SR_BPTR 0x08 |
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#define BPTR_JPT (0x0F << 0) |
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#define BPTR_BPHW (0x0F << 4) |
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/* Flow Control Threshold Reg */ |
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#define SR_FCTR 0x09 |
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#define FCTR_LWOT (0x0F << 0) |
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#define FCTR_HWOT (0x0F << 4) |
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/* rx/tx Flow Control Reg */ |
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#define SR_FCR 0x0A |
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#define FCR_FLCE (1 << 0) |
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#define FCR_BKPA (1 << 4) |
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#define FCR_TXPEN (1 << 5) |
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#define FCR_TXPF (1 << 6) |
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#define FCR_TXP0 (1 << 7) |
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/* Eeprom & Phy Control Reg */ |
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#define SR_EPCR 0x0B |
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#define EPCR_ERRE (1 << 0) |
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#define EPCR_ERPRW (1 << 1) |
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#define EPCR_ERPRR (1 << 2) |
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#define EPCR_EPOS (1 << 3) |
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#define EPCR_WEP (1 << 4) |
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/* Eeprom & Phy Address Reg */ |
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#define SR_EPAR 0x0C |
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#define EPAR_EROA (0x3F << 0) |
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#define EPAR_PHY_ADR_MASK (0x03 << 6) |
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#define EPAR_PHY_ADR (0x01 << 6) |
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/* Eeprom & Phy Data Reg */ |
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#define SR_EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */ |
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/* Wakeup Control Reg */ |
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#define SR_WCR 0x0F |
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#define WCR_MAGICST (1 << 0) |
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#define WCR_LINKST (1 << 2) |
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#define WCR_MAGICEN (1 << 3) |
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#define WCR_LINKEN (1 << 5) |
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/* Physical Address Reg */ |
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#define SR_PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */ |
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/* Multicast Address Reg */ |
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#define SR_MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */ |
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/* 0x1e unused */ |
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/* Phy Reset Reg */ |
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#define SR_PRR 0x1F |
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#define PRR_PHY_RST (1 << 0) |
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/* Tx sdram Write Pointer Address Low */ |
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#define SR_TWPAL 0x20 |
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/* Tx sdram Write Pointer Address High */ |
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#define SR_TWPAH 0x21 |
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/* Tx sdram Read Pointer Address Low */ |
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#define SR_TRPAL 0x22 |
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/* Tx sdram Read Pointer Address High */ |
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#define SR_TRPAH 0x23 |
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/* Rx sdram Write Pointer Address Low */ |
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#define SR_RWPAL 0x24 |
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/* Rx sdram Write Pointer Address High */ |
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#define SR_RWPAH 0x25 |
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/* Rx sdram Read Pointer Address Low */ |
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#define SR_RRPAL 0x26 |
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/* Rx sdram Read Pointer Address High */ |
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#define SR_RRPAH 0x27 |
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/* Vendor ID register */ |
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#define SR_VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */ |
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/* Product ID register */ |
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#define SR_PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */ |
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/* CHIP Revision register */ |
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#define SR_CHIPR 0x2C |
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/* 0x2D --> 0xEF unused */ |
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/* USB Device Address */ |
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#define SR_USBDA 0xF0 |
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#define USBDA_USBFA (0x7F << 0) |
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/* RX packet Counter Reg */ |
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#define SR_RXC 0xF1 |
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/* Tx packet Counter & USB Status Reg */ |
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#define SR_TXC_USBS 0xF2 |
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#define TXC_USBS_TXC0 (1 << 0) |
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#define TXC_USBS_TXC1 (1 << 1) |
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#define TXC_USBS_TXC2 (1 << 2) |
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#define TXC_USBS_EP1RDY (1 << 5) |
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#define TXC_USBS_SUSFLAG (1 << 6) |
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#define TXC_USBS_RXFAULT (1 << 7) |
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/* USB Control register */ |
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#define SR_USBC 0xF4 |
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#define USBC_EP3NAK (1 << 4) |
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#define USBC_EP3ACK (1 << 5) |
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/* Register access commands and flags */ |
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#define SR_RD_REGS 0x00 |
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#define SR_WR_REGS 0x01 |
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#define SR_WR_REG 0x03 |
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#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE) |
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#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE) |
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/* parameters */ |
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#define SR_SHARE_TIMEOUT 1000 |
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#define SR_EEPROM_LEN 256 |
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#define SR_MCAST_SIZE 8 |
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#define SR_MCAST_ADDR_FLAG 0x80 |
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#define SR_MCAST_MAX 64 |
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#define SR_TX_OVERHEAD 2 /* 2bytes header */ |
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#define SR_RX_OVERHEAD 7 /* 3bytes header + 4crc tail */ |
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#endif /* _SR9700_H */
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