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1277 lines
31 KiB
1277 lines
31 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Ethernet driver for the WIZnet W5100 chip. |
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* |
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* Copyright (C) 2006-2008 WIZnet Co.,Ltd. |
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* Copyright (C) 2012 Mike Sinkovsky <[email protected]> |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/platform_device.h> |
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#include <linux/platform_data/wiznet.h> |
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#include <linux/ethtool.h> |
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#include <linux/skbuff.h> |
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#include <linux/types.h> |
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#include <linux/errno.h> |
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#include <linux/delay.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/gpio.h> |
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#include "w5100.h" |
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#define DRV_NAME "w5100" |
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#define DRV_VERSION "2012-04-04" |
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MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION); |
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MODULE_AUTHOR("Mike Sinkovsky <[email protected]>"); |
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MODULE_ALIAS("platform:"DRV_NAME); |
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MODULE_LICENSE("GPL"); |
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|
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/* |
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* W5100/W5200/W5500 common registers |
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*/ |
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#define W5100_COMMON_REGS 0x0000 |
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#define W5100_MR 0x0000 /* Mode Register */ |
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#define MR_RST 0x80 /* S/W reset */ |
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#define MR_PB 0x10 /* Ping block */ |
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#define MR_AI 0x02 /* Address Auto-Increment */ |
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#define MR_IND 0x01 /* Indirect mode */ |
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#define W5100_SHAR 0x0009 /* Source MAC address */ |
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#define W5100_IR 0x0015 /* Interrupt Register */ |
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#define W5100_COMMON_REGS_LEN 0x0040 |
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#define W5100_Sn_MR 0x0000 /* Sn Mode Register */ |
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#define W5100_Sn_CR 0x0001 /* Sn Command Register */ |
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#define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */ |
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#define W5100_Sn_SR 0x0003 /* Sn Status Register */ |
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#define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */ |
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#define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */ |
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#define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */ |
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#define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */ |
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#define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */ |
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#define S0_REGS(priv) ((priv)->s0_regs) |
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#define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR) |
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#define S0_MR_MACRAW 0x04 /* MAC RAW mode */ |
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#define S0_MR_MF 0x40 /* MAC Filter for W5100 and W5200 */ |
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#define W5500_S0_MR_MF 0x80 /* MAC Filter for W5500 */ |
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#define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR) |
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#define S0_CR_OPEN 0x01 /* OPEN command */ |
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#define S0_CR_CLOSE 0x10 /* CLOSE command */ |
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#define S0_CR_SEND 0x20 /* SEND command */ |
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#define S0_CR_RECV 0x40 /* RECV command */ |
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#define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR) |
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#define S0_IR_SENDOK 0x10 /* complete sending */ |
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#define S0_IR_RECV 0x04 /* receiving data */ |
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#define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR) |
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#define S0_SR_MACRAW 0x42 /* mac raw mode */ |
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#define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR) |
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#define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD) |
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#define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR) |
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#define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR) |
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#define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD) |
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#define W5100_S0_REGS_LEN 0x0040 |
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/* |
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* W5100 and W5200 common registers |
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*/ |
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#define W5100_IMR 0x0016 /* Interrupt Mask Register */ |
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#define IR_S0 0x01 /* S0 interrupt */ |
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#define W5100_RTR 0x0017 /* Retry Time-value Register */ |
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#define RTR_DEFAULT 2000 /* =0x07d0 (2000) */ |
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|
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/* |
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* W5100 specific register and memory |
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*/ |
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#define W5100_RMSR 0x001a /* Receive Memory Size */ |
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#define W5100_TMSR 0x001b /* Transmit Memory Size */ |
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#define W5100_S0_REGS 0x0400 |
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#define W5100_TX_MEM_START 0x4000 |
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#define W5100_TX_MEM_SIZE 0x2000 |
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#define W5100_RX_MEM_START 0x6000 |
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#define W5100_RX_MEM_SIZE 0x2000 |
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|
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/* |
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* W5200 specific register and memory |
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*/ |
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#define W5200_S0_REGS 0x4000 |
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#define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */ |
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#define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */ |
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#define W5200_TX_MEM_START 0x8000 |
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#define W5200_TX_MEM_SIZE 0x4000 |
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#define W5200_RX_MEM_START 0xc000 |
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#define W5200_RX_MEM_SIZE 0x4000 |
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/* |
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* W5500 specific register and memory |
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* |
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* W5500 register and memory are organized by multiple blocks. Each one is |
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* selected by 16bits offset address and 5bits block select bits. So we |
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* encode it into 32bits address. (lower 16bits is offset address and |
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* upper 16bits is block select bits) |
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*/ |
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#define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */ |
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#define W5500_RTR 0x0019 /* Retry Time-value Register */ |
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#define W5500_S0_REGS 0x10000 |
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#define W5500_Sn_RXMEM_SIZE(n) \ |
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(0x1001e + (n) * 0x40000) /* Sn RX Memory Size */ |
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#define W5500_Sn_TXMEM_SIZE(n) \ |
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(0x1001f + (n) * 0x40000) /* Sn TX Memory Size */ |
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#define W5500_TX_MEM_START 0x20000 |
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#define W5500_TX_MEM_SIZE 0x04000 |
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#define W5500_RX_MEM_START 0x30000 |
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#define W5500_RX_MEM_SIZE 0x04000 |
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/* |
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* Device driver private data structure |
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*/ |
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struct w5100_priv { |
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const struct w5100_ops *ops; |
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/* Socket 0 register offset address */ |
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u32 s0_regs; |
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/* Socket 0 TX buffer offset address and size */ |
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u32 s0_tx_buf; |
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u16 s0_tx_buf_size; |
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/* Socket 0 RX buffer offset address and size */ |
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u32 s0_rx_buf; |
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u16 s0_rx_buf_size; |
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int irq; |
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int link_irq; |
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int link_gpio; |
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struct napi_struct napi; |
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struct net_device *ndev; |
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bool promisc; |
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u32 msg_enable; |
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struct workqueue_struct *xfer_wq; |
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struct work_struct rx_work; |
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struct sk_buff *tx_skb; |
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struct work_struct tx_work; |
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struct work_struct setrx_work; |
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struct work_struct restart_work; |
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}; |
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/************************************************************************ |
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* |
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* Lowlevel I/O functions |
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* |
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***********************************************************************/ |
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struct w5100_mmio_priv { |
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void __iomem *base; |
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/* Serialize access in indirect address mode */ |
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spinlock_t reg_lock; |
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}; |
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static inline struct w5100_mmio_priv *w5100_mmio_priv(struct net_device *dev) |
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{ |
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return w5100_ops_priv(dev); |
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} |
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static inline void __iomem *w5100_mmio(struct net_device *ndev) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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return mmio_priv->base; |
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} |
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/* |
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* In direct address mode host system can directly access W5100 registers |
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* after mapping to Memory-Mapped I/O space. |
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* |
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* 0x8000 bytes are required for memory space. |
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*/ |
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static inline int w5100_read_direct(struct net_device *ndev, u32 addr) |
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{ |
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return ioread8(w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT)); |
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} |
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static inline int __w5100_write_direct(struct net_device *ndev, u32 addr, |
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u8 data) |
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{ |
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iowrite8(data, w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT)); |
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return 0; |
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} |
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static inline int w5100_write_direct(struct net_device *ndev, u32 addr, u8 data) |
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{ |
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__w5100_write_direct(ndev, addr, data); |
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return 0; |
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} |
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static int w5100_read16_direct(struct net_device *ndev, u32 addr) |
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{ |
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u16 data; |
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data = w5100_read_direct(ndev, addr) << 8; |
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data |= w5100_read_direct(ndev, addr + 1); |
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return data; |
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} |
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static int w5100_write16_direct(struct net_device *ndev, u32 addr, u16 data) |
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{ |
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__w5100_write_direct(ndev, addr, data >> 8); |
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__w5100_write_direct(ndev, addr + 1, data); |
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return 0; |
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} |
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static int w5100_readbulk_direct(struct net_device *ndev, u32 addr, u8 *buf, |
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int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++, addr++) |
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*buf++ = w5100_read_direct(ndev, addr); |
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return 0; |
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} |
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static int w5100_writebulk_direct(struct net_device *ndev, u32 addr, |
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const u8 *buf, int len) |
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{ |
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int i; |
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for (i = 0; i < len; i++, addr++) |
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__w5100_write_direct(ndev, addr, *buf++); |
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return 0; |
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} |
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static int w5100_mmio_init(struct net_device *ndev) |
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{ |
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struct platform_device *pdev = to_platform_device(ndev->dev.parent); |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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spin_lock_init(&mmio_priv->reg_lock); |
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mmio_priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); |
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if (IS_ERR(mmio_priv->base)) |
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return PTR_ERR(mmio_priv->base); |
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return 0; |
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} |
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static const struct w5100_ops w5100_mmio_direct_ops = { |
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.chip_id = W5100, |
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.read = w5100_read_direct, |
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.write = w5100_write_direct, |
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.read16 = w5100_read16_direct, |
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.write16 = w5100_write16_direct, |
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.readbulk = w5100_readbulk_direct, |
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.writebulk = w5100_writebulk_direct, |
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.init = w5100_mmio_init, |
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}; |
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/* |
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* In indirect address mode host system indirectly accesses registers by |
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* using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data |
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* Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space. |
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* Mode Register (MR) is directly accessible. |
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* |
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* Only 0x04 bytes are required for memory space. |
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*/ |
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#define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */ |
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#define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */ |
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static int w5100_read_indirect(struct net_device *ndev, u32 addr) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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unsigned long flags; |
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u8 data; |
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spin_lock_irqsave(&mmio_priv->reg_lock, flags); |
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w5100_write16_direct(ndev, W5100_IDM_AR, addr); |
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data = w5100_read_direct(ndev, W5100_IDM_DR); |
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spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); |
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return data; |
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} |
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static int w5100_write_indirect(struct net_device *ndev, u32 addr, u8 data) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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unsigned long flags; |
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spin_lock_irqsave(&mmio_priv->reg_lock, flags); |
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w5100_write16_direct(ndev, W5100_IDM_AR, addr); |
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w5100_write_direct(ndev, W5100_IDM_DR, data); |
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spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); |
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return 0; |
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} |
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static int w5100_read16_indirect(struct net_device *ndev, u32 addr) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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unsigned long flags; |
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u16 data; |
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spin_lock_irqsave(&mmio_priv->reg_lock, flags); |
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w5100_write16_direct(ndev, W5100_IDM_AR, addr); |
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data = w5100_read_direct(ndev, W5100_IDM_DR) << 8; |
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data |= w5100_read_direct(ndev, W5100_IDM_DR); |
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spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); |
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return data; |
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} |
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static int w5100_write16_indirect(struct net_device *ndev, u32 addr, u16 data) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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unsigned long flags; |
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spin_lock_irqsave(&mmio_priv->reg_lock, flags); |
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w5100_write16_direct(ndev, W5100_IDM_AR, addr); |
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__w5100_write_direct(ndev, W5100_IDM_DR, data >> 8); |
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w5100_write_direct(ndev, W5100_IDM_DR, data); |
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spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); |
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return 0; |
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} |
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static int w5100_readbulk_indirect(struct net_device *ndev, u32 addr, u8 *buf, |
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int len) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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unsigned long flags; |
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int i; |
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spin_lock_irqsave(&mmio_priv->reg_lock, flags); |
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w5100_write16_direct(ndev, W5100_IDM_AR, addr); |
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for (i = 0; i < len; i++) |
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*buf++ = w5100_read_direct(ndev, W5100_IDM_DR); |
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spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); |
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return 0; |
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} |
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static int w5100_writebulk_indirect(struct net_device *ndev, u32 addr, |
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const u8 *buf, int len) |
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{ |
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struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev); |
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unsigned long flags; |
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int i; |
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spin_lock_irqsave(&mmio_priv->reg_lock, flags); |
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w5100_write16_direct(ndev, W5100_IDM_AR, addr); |
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for (i = 0; i < len; i++) |
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__w5100_write_direct(ndev, W5100_IDM_DR, *buf++); |
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spin_unlock_irqrestore(&mmio_priv->reg_lock, flags); |
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return 0; |
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} |
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static int w5100_reset_indirect(struct net_device *ndev) |
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{ |
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w5100_write_direct(ndev, W5100_MR, MR_RST); |
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mdelay(5); |
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w5100_write_direct(ndev, W5100_MR, MR_PB | MR_AI | MR_IND); |
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return 0; |
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} |
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static const struct w5100_ops w5100_mmio_indirect_ops = { |
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.chip_id = W5100, |
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.read = w5100_read_indirect, |
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.write = w5100_write_indirect, |
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.read16 = w5100_read16_indirect, |
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.write16 = w5100_write16_indirect, |
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.readbulk = w5100_readbulk_indirect, |
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.writebulk = w5100_writebulk_indirect, |
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.init = w5100_mmio_init, |
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.reset = w5100_reset_indirect, |
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}; |
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#if defined(CONFIG_WIZNET_BUS_DIRECT) |
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static int w5100_read(struct w5100_priv *priv, u32 addr) |
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{ |
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return w5100_read_direct(priv->ndev, addr); |
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} |
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static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data) |
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{ |
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return w5100_write_direct(priv->ndev, addr, data); |
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} |
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static int w5100_read16(struct w5100_priv *priv, u32 addr) |
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{ |
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return w5100_read16_direct(priv->ndev, addr); |
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} |
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static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data) |
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{ |
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return w5100_write16_direct(priv->ndev, addr, data); |
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} |
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static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len) |
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{ |
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return w5100_readbulk_direct(priv->ndev, addr, buf, len); |
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} |
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static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf, |
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int len) |
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{ |
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return w5100_writebulk_direct(priv->ndev, addr, buf, len); |
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} |
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#elif defined(CONFIG_WIZNET_BUS_INDIRECT) |
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static int w5100_read(struct w5100_priv *priv, u32 addr) |
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{ |
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return w5100_read_indirect(priv->ndev, addr); |
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} |
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static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data) |
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{ |
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return w5100_write_indirect(priv->ndev, addr, data); |
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} |
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static int w5100_read16(struct w5100_priv *priv, u32 addr) |
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{ |
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return w5100_read16_indirect(priv->ndev, addr); |
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} |
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static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data) |
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{ |
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return w5100_write16_indirect(priv->ndev, addr, data); |
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} |
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static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len) |
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{ |
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return w5100_readbulk_indirect(priv->ndev, addr, buf, len); |
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} |
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static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf, |
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int len) |
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{ |
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return w5100_writebulk_indirect(priv->ndev, addr, buf, len); |
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} |
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#else /* CONFIG_WIZNET_BUS_ANY */ |
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static int w5100_read(struct w5100_priv *priv, u32 addr) |
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{ |
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return priv->ops->read(priv->ndev, addr); |
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} |
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static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data) |
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{ |
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return priv->ops->write(priv->ndev, addr, data); |
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} |
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static int w5100_read16(struct w5100_priv *priv, u32 addr) |
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{ |
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return priv->ops->read16(priv->ndev, addr); |
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} |
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static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data) |
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{ |
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return priv->ops->write16(priv->ndev, addr, data); |
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} |
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static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len) |
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{ |
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return priv->ops->readbulk(priv->ndev, addr, buf, len); |
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} |
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static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf, |
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int len) |
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{ |
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return priv->ops->writebulk(priv->ndev, addr, buf, len); |
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} |
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|
|
#endif |
|
|
|
static int w5100_readbuf(struct w5100_priv *priv, u16 offset, u8 *buf, int len) |
|
{ |
|
u32 addr; |
|
int remain = 0; |
|
int ret; |
|
const u32 mem_start = priv->s0_rx_buf; |
|
const u16 mem_size = priv->s0_rx_buf_size; |
|
|
|
offset %= mem_size; |
|
addr = mem_start + offset; |
|
|
|
if (offset + len > mem_size) { |
|
remain = (offset + len) % mem_size; |
|
len = mem_size - offset; |
|
} |
|
|
|
ret = w5100_readbulk(priv, addr, buf, len); |
|
if (ret || !remain) |
|
return ret; |
|
|
|
return w5100_readbulk(priv, mem_start, buf + len, remain); |
|
} |
|
|
|
static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf, |
|
int len) |
|
{ |
|
u32 addr; |
|
int ret; |
|
int remain = 0; |
|
const u32 mem_start = priv->s0_tx_buf; |
|
const u16 mem_size = priv->s0_tx_buf_size; |
|
|
|
offset %= mem_size; |
|
addr = mem_start + offset; |
|
|
|
if (offset + len > mem_size) { |
|
remain = (offset + len) % mem_size; |
|
len = mem_size - offset; |
|
} |
|
|
|
ret = w5100_writebulk(priv, addr, buf, len); |
|
if (ret || !remain) |
|
return ret; |
|
|
|
return w5100_writebulk(priv, mem_start, buf + len, remain); |
|
} |
|
|
|
static int w5100_reset(struct w5100_priv *priv) |
|
{ |
|
if (priv->ops->reset) |
|
return priv->ops->reset(priv->ndev); |
|
|
|
w5100_write(priv, W5100_MR, MR_RST); |
|
mdelay(5); |
|
w5100_write(priv, W5100_MR, MR_PB); |
|
|
|
return 0; |
|
} |
|
|
|
static int w5100_command(struct w5100_priv *priv, u16 cmd) |
|
{ |
|
unsigned long timeout; |
|
|
|
w5100_write(priv, W5100_S0_CR(priv), cmd); |
|
|
|
timeout = jiffies + msecs_to_jiffies(100); |
|
|
|
while (w5100_read(priv, W5100_S0_CR(priv)) != 0) { |
|
if (time_after(jiffies, timeout)) |
|
return -EIO; |
|
cpu_relax(); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void w5100_write_macaddr(struct w5100_priv *priv) |
|
{ |
|
struct net_device *ndev = priv->ndev; |
|
|
|
w5100_writebulk(priv, W5100_SHAR, ndev->dev_addr, ETH_ALEN); |
|
} |
|
|
|
static void w5100_socket_intr_mask(struct w5100_priv *priv, u8 mask) |
|
{ |
|
u32 imr; |
|
|
|
if (priv->ops->chip_id == W5500) |
|
imr = W5500_SIMR; |
|
else |
|
imr = W5100_IMR; |
|
|
|
w5100_write(priv, imr, mask); |
|
} |
|
|
|
static void w5100_enable_intr(struct w5100_priv *priv) |
|
{ |
|
w5100_socket_intr_mask(priv, IR_S0); |
|
} |
|
|
|
static void w5100_disable_intr(struct w5100_priv *priv) |
|
{ |
|
w5100_socket_intr_mask(priv, 0); |
|
} |
|
|
|
static void w5100_memory_configure(struct w5100_priv *priv) |
|
{ |
|
/* Configure 16K of internal memory |
|
* as 8K RX buffer and 8K TX buffer |
|
*/ |
|
w5100_write(priv, W5100_RMSR, 0x03); |
|
w5100_write(priv, W5100_TMSR, 0x03); |
|
} |
|
|
|
static void w5200_memory_configure(struct w5100_priv *priv) |
|
{ |
|
int i; |
|
|
|
/* Configure internal RX memory as 16K RX buffer and |
|
* internal TX memory as 16K TX buffer |
|
*/ |
|
w5100_write(priv, W5200_Sn_RXMEM_SIZE(0), 0x10); |
|
w5100_write(priv, W5200_Sn_TXMEM_SIZE(0), 0x10); |
|
|
|
for (i = 1; i < 8; i++) { |
|
w5100_write(priv, W5200_Sn_RXMEM_SIZE(i), 0); |
|
w5100_write(priv, W5200_Sn_TXMEM_SIZE(i), 0); |
|
} |
|
} |
|
|
|
static void w5500_memory_configure(struct w5100_priv *priv) |
|
{ |
|
int i; |
|
|
|
/* Configure internal RX memory as 16K RX buffer and |
|
* internal TX memory as 16K TX buffer |
|
*/ |
|
w5100_write(priv, W5500_Sn_RXMEM_SIZE(0), 0x10); |
|
w5100_write(priv, W5500_Sn_TXMEM_SIZE(0), 0x10); |
|
|
|
for (i = 1; i < 8; i++) { |
|
w5100_write(priv, W5500_Sn_RXMEM_SIZE(i), 0); |
|
w5100_write(priv, W5500_Sn_TXMEM_SIZE(i), 0); |
|
} |
|
} |
|
|
|
static int w5100_hw_reset(struct w5100_priv *priv) |
|
{ |
|
u32 rtr; |
|
|
|
w5100_reset(priv); |
|
|
|
w5100_disable_intr(priv); |
|
w5100_write_macaddr(priv); |
|
|
|
switch (priv->ops->chip_id) { |
|
case W5100: |
|
w5100_memory_configure(priv); |
|
rtr = W5100_RTR; |
|
break; |
|
case W5200: |
|
w5200_memory_configure(priv); |
|
rtr = W5100_RTR; |
|
break; |
|
case W5500: |
|
w5500_memory_configure(priv); |
|
rtr = W5500_RTR; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
if (w5100_read16(priv, rtr) != RTR_DEFAULT) |
|
return -ENODEV; |
|
|
|
return 0; |
|
} |
|
|
|
static void w5100_hw_start(struct w5100_priv *priv) |
|
{ |
|
u8 mode = S0_MR_MACRAW; |
|
|
|
if (!priv->promisc) { |
|
if (priv->ops->chip_id == W5500) |
|
mode |= W5500_S0_MR_MF; |
|
else |
|
mode |= S0_MR_MF; |
|
} |
|
|
|
w5100_write(priv, W5100_S0_MR(priv), mode); |
|
w5100_command(priv, S0_CR_OPEN); |
|
w5100_enable_intr(priv); |
|
} |
|
|
|
static void w5100_hw_close(struct w5100_priv *priv) |
|
{ |
|
w5100_disable_intr(priv); |
|
w5100_command(priv, S0_CR_CLOSE); |
|
} |
|
|
|
/*********************************************************************** |
|
* |
|
* Device driver functions / callbacks |
|
* |
|
***********************************************************************/ |
|
|
|
static void w5100_get_drvinfo(struct net_device *ndev, |
|
struct ethtool_drvinfo *info) |
|
{ |
|
strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
|
strlcpy(info->version, DRV_VERSION, sizeof(info->version)); |
|
strlcpy(info->bus_info, dev_name(ndev->dev.parent), |
|
sizeof(info->bus_info)); |
|
} |
|
|
|
static u32 w5100_get_link(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
if (gpio_is_valid(priv->link_gpio)) |
|
return !!gpio_get_value(priv->link_gpio); |
|
|
|
return 1; |
|
} |
|
|
|
static u32 w5100_get_msglevel(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
return priv->msg_enable; |
|
} |
|
|
|
static void w5100_set_msglevel(struct net_device *ndev, u32 value) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
priv->msg_enable = value; |
|
} |
|
|
|
static int w5100_get_regs_len(struct net_device *ndev) |
|
{ |
|
return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN; |
|
} |
|
|
|
static void w5100_get_regs(struct net_device *ndev, |
|
struct ethtool_regs *regs, void *buf) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
regs->version = 1; |
|
w5100_readbulk(priv, W5100_COMMON_REGS, buf, W5100_COMMON_REGS_LEN); |
|
buf += W5100_COMMON_REGS_LEN; |
|
w5100_readbulk(priv, S0_REGS(priv), buf, W5100_S0_REGS_LEN); |
|
} |
|
|
|
static void w5100_restart(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
netif_stop_queue(ndev); |
|
w5100_hw_reset(priv); |
|
w5100_hw_start(priv); |
|
ndev->stats.tx_errors++; |
|
netif_trans_update(ndev); |
|
netif_wake_queue(ndev); |
|
} |
|
|
|
static void w5100_restart_work(struct work_struct *work) |
|
{ |
|
struct w5100_priv *priv = container_of(work, struct w5100_priv, |
|
restart_work); |
|
|
|
w5100_restart(priv->ndev); |
|
} |
|
|
|
static void w5100_tx_timeout(struct net_device *ndev, unsigned int txqueue) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
if (priv->ops->may_sleep) |
|
schedule_work(&priv->restart_work); |
|
else |
|
w5100_restart(ndev); |
|
} |
|
|
|
static void w5100_tx_skb(struct net_device *ndev, struct sk_buff *skb) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
u16 offset; |
|
|
|
offset = w5100_read16(priv, W5100_S0_TX_WR(priv)); |
|
w5100_writebuf(priv, offset, skb->data, skb->len); |
|
w5100_write16(priv, W5100_S0_TX_WR(priv), offset + skb->len); |
|
ndev->stats.tx_bytes += skb->len; |
|
ndev->stats.tx_packets++; |
|
dev_kfree_skb(skb); |
|
|
|
w5100_command(priv, S0_CR_SEND); |
|
} |
|
|
|
static void w5100_tx_work(struct work_struct *work) |
|
{ |
|
struct w5100_priv *priv = container_of(work, struct w5100_priv, |
|
tx_work); |
|
struct sk_buff *skb = priv->tx_skb; |
|
|
|
priv->tx_skb = NULL; |
|
|
|
if (WARN_ON(!skb)) |
|
return; |
|
w5100_tx_skb(priv->ndev, skb); |
|
} |
|
|
|
static netdev_tx_t w5100_start_tx(struct sk_buff *skb, struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
netif_stop_queue(ndev); |
|
|
|
if (priv->ops->may_sleep) { |
|
WARN_ON(priv->tx_skb); |
|
priv->tx_skb = skb; |
|
queue_work(priv->xfer_wq, &priv->tx_work); |
|
} else { |
|
w5100_tx_skb(ndev, skb); |
|
} |
|
|
|
return NETDEV_TX_OK; |
|
} |
|
|
|
static struct sk_buff *w5100_rx_skb(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
struct sk_buff *skb; |
|
u16 rx_len; |
|
u16 offset; |
|
u8 header[2]; |
|
u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR(priv)); |
|
|
|
if (rx_buf_len == 0) |
|
return NULL; |
|
|
|
offset = w5100_read16(priv, W5100_S0_RX_RD(priv)); |
|
w5100_readbuf(priv, offset, header, 2); |
|
rx_len = get_unaligned_be16(header) - 2; |
|
|
|
skb = netdev_alloc_skb_ip_align(ndev, rx_len); |
|
if (unlikely(!skb)) { |
|
w5100_write16(priv, W5100_S0_RX_RD(priv), offset + rx_buf_len); |
|
w5100_command(priv, S0_CR_RECV); |
|
ndev->stats.rx_dropped++; |
|
return NULL; |
|
} |
|
|
|
skb_put(skb, rx_len); |
|
w5100_readbuf(priv, offset + 2, skb->data, rx_len); |
|
w5100_write16(priv, W5100_S0_RX_RD(priv), offset + 2 + rx_len); |
|
w5100_command(priv, S0_CR_RECV); |
|
skb->protocol = eth_type_trans(skb, ndev); |
|
|
|
ndev->stats.rx_packets++; |
|
ndev->stats.rx_bytes += rx_len; |
|
|
|
return skb; |
|
} |
|
|
|
static void w5100_rx_work(struct work_struct *work) |
|
{ |
|
struct w5100_priv *priv = container_of(work, struct w5100_priv, |
|
rx_work); |
|
struct sk_buff *skb; |
|
|
|
while ((skb = w5100_rx_skb(priv->ndev))) |
|
netif_rx_ni(skb); |
|
|
|
w5100_enable_intr(priv); |
|
} |
|
|
|
static int w5100_napi_poll(struct napi_struct *napi, int budget) |
|
{ |
|
struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi); |
|
int rx_count; |
|
|
|
for (rx_count = 0; rx_count < budget; rx_count++) { |
|
struct sk_buff *skb = w5100_rx_skb(priv->ndev); |
|
|
|
if (skb) |
|
netif_receive_skb(skb); |
|
else |
|
break; |
|
} |
|
|
|
if (rx_count < budget) { |
|
napi_complete_done(napi, rx_count); |
|
w5100_enable_intr(priv); |
|
} |
|
|
|
return rx_count; |
|
} |
|
|
|
static irqreturn_t w5100_interrupt(int irq, void *ndev_instance) |
|
{ |
|
struct net_device *ndev = ndev_instance; |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
int ir = w5100_read(priv, W5100_S0_IR(priv)); |
|
if (!ir) |
|
return IRQ_NONE; |
|
w5100_write(priv, W5100_S0_IR(priv), ir); |
|
|
|
if (ir & S0_IR_SENDOK) { |
|
netif_dbg(priv, tx_done, ndev, "tx done\n"); |
|
netif_wake_queue(ndev); |
|
} |
|
|
|
if (ir & S0_IR_RECV) { |
|
w5100_disable_intr(priv); |
|
|
|
if (priv->ops->may_sleep) |
|
queue_work(priv->xfer_wq, &priv->rx_work); |
|
else if (napi_schedule_prep(&priv->napi)) |
|
__napi_schedule(&priv->napi); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static irqreturn_t w5100_detect_link(int irq, void *ndev_instance) |
|
{ |
|
struct net_device *ndev = ndev_instance; |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
if (netif_running(ndev)) { |
|
if (gpio_get_value(priv->link_gpio) != 0) { |
|
netif_info(priv, link, ndev, "link is up\n"); |
|
netif_carrier_on(ndev); |
|
} else { |
|
netif_info(priv, link, ndev, "link is down\n"); |
|
netif_carrier_off(ndev); |
|
} |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static void w5100_setrx_work(struct work_struct *work) |
|
{ |
|
struct w5100_priv *priv = container_of(work, struct w5100_priv, |
|
setrx_work); |
|
|
|
w5100_hw_start(priv); |
|
} |
|
|
|
static void w5100_set_rx_mode(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
bool set_promisc = (ndev->flags & IFF_PROMISC) != 0; |
|
|
|
if (priv->promisc != set_promisc) { |
|
priv->promisc = set_promisc; |
|
|
|
if (priv->ops->may_sleep) |
|
schedule_work(&priv->setrx_work); |
|
else |
|
w5100_hw_start(priv); |
|
} |
|
} |
|
|
|
static int w5100_set_macaddr(struct net_device *ndev, void *addr) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
struct sockaddr *sock_addr = addr; |
|
|
|
if (!is_valid_ether_addr(sock_addr->sa_data)) |
|
return -EADDRNOTAVAIL; |
|
memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN); |
|
w5100_write_macaddr(priv); |
|
return 0; |
|
} |
|
|
|
static int w5100_open(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
netif_info(priv, ifup, ndev, "enabling\n"); |
|
w5100_hw_start(priv); |
|
napi_enable(&priv->napi); |
|
netif_start_queue(ndev); |
|
if (!gpio_is_valid(priv->link_gpio) || |
|
gpio_get_value(priv->link_gpio) != 0) |
|
netif_carrier_on(ndev); |
|
return 0; |
|
} |
|
|
|
static int w5100_stop(struct net_device *ndev) |
|
{ |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
netif_info(priv, ifdown, ndev, "shutting down\n"); |
|
w5100_hw_close(priv); |
|
netif_carrier_off(ndev); |
|
netif_stop_queue(ndev); |
|
napi_disable(&priv->napi); |
|
return 0; |
|
} |
|
|
|
static const struct ethtool_ops w5100_ethtool_ops = { |
|
.get_drvinfo = w5100_get_drvinfo, |
|
.get_msglevel = w5100_get_msglevel, |
|
.set_msglevel = w5100_set_msglevel, |
|
.get_link = w5100_get_link, |
|
.get_regs_len = w5100_get_regs_len, |
|
.get_regs = w5100_get_regs, |
|
}; |
|
|
|
static const struct net_device_ops w5100_netdev_ops = { |
|
.ndo_open = w5100_open, |
|
.ndo_stop = w5100_stop, |
|
.ndo_start_xmit = w5100_start_tx, |
|
.ndo_tx_timeout = w5100_tx_timeout, |
|
.ndo_set_rx_mode = w5100_set_rx_mode, |
|
.ndo_set_mac_address = w5100_set_macaddr, |
|
.ndo_validate_addr = eth_validate_addr, |
|
}; |
|
|
|
static int w5100_mmio_probe(struct platform_device *pdev) |
|
{ |
|
struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev); |
|
const void *mac_addr = NULL; |
|
struct resource *mem; |
|
const struct w5100_ops *ops; |
|
int irq; |
|
|
|
if (data && is_valid_ether_addr(data->mac_addr)) |
|
mac_addr = data->mac_addr; |
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!mem) |
|
return -EINVAL; |
|
if (resource_size(mem) < W5100_BUS_DIRECT_SIZE) |
|
ops = &w5100_mmio_indirect_ops; |
|
else |
|
ops = &w5100_mmio_direct_ops; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
return w5100_probe(&pdev->dev, ops, sizeof(struct w5100_mmio_priv), |
|
mac_addr, irq, data ? data->link_gpio : -EINVAL); |
|
} |
|
|
|
static int w5100_mmio_remove(struct platform_device *pdev) |
|
{ |
|
return w5100_remove(&pdev->dev); |
|
} |
|
|
|
void *w5100_ops_priv(const struct net_device *ndev) |
|
{ |
|
return netdev_priv(ndev) + |
|
ALIGN(sizeof(struct w5100_priv), NETDEV_ALIGN); |
|
} |
|
EXPORT_SYMBOL_GPL(w5100_ops_priv); |
|
|
|
int w5100_probe(struct device *dev, const struct w5100_ops *ops, |
|
int sizeof_ops_priv, const void *mac_addr, int irq, |
|
int link_gpio) |
|
{ |
|
struct w5100_priv *priv; |
|
struct net_device *ndev; |
|
int err; |
|
size_t alloc_size; |
|
|
|
alloc_size = sizeof(*priv); |
|
if (sizeof_ops_priv) { |
|
alloc_size = ALIGN(alloc_size, NETDEV_ALIGN); |
|
alloc_size += sizeof_ops_priv; |
|
} |
|
alloc_size += NETDEV_ALIGN - 1; |
|
|
|
ndev = alloc_etherdev(alloc_size); |
|
if (!ndev) |
|
return -ENOMEM; |
|
SET_NETDEV_DEV(ndev, dev); |
|
dev_set_drvdata(dev, ndev); |
|
priv = netdev_priv(ndev); |
|
|
|
switch (ops->chip_id) { |
|
case W5100: |
|
priv->s0_regs = W5100_S0_REGS; |
|
priv->s0_tx_buf = W5100_TX_MEM_START; |
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priv->s0_tx_buf_size = W5100_TX_MEM_SIZE; |
|
priv->s0_rx_buf = W5100_RX_MEM_START; |
|
priv->s0_rx_buf_size = W5100_RX_MEM_SIZE; |
|
break; |
|
case W5200: |
|
priv->s0_regs = W5200_S0_REGS; |
|
priv->s0_tx_buf = W5200_TX_MEM_START; |
|
priv->s0_tx_buf_size = W5200_TX_MEM_SIZE; |
|
priv->s0_rx_buf = W5200_RX_MEM_START; |
|
priv->s0_rx_buf_size = W5200_RX_MEM_SIZE; |
|
break; |
|
case W5500: |
|
priv->s0_regs = W5500_S0_REGS; |
|
priv->s0_tx_buf = W5500_TX_MEM_START; |
|
priv->s0_tx_buf_size = W5500_TX_MEM_SIZE; |
|
priv->s0_rx_buf = W5500_RX_MEM_START; |
|
priv->s0_rx_buf_size = W5500_RX_MEM_SIZE; |
|
break; |
|
default: |
|
err = -EINVAL; |
|
goto err_register; |
|
} |
|
|
|
priv->ndev = ndev; |
|
priv->ops = ops; |
|
priv->irq = irq; |
|
priv->link_gpio = link_gpio; |
|
|
|
ndev->netdev_ops = &w5100_netdev_ops; |
|
ndev->ethtool_ops = &w5100_ethtool_ops; |
|
netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16); |
|
|
|
/* This chip doesn't support VLAN packets with normal MTU, |
|
* so disable VLAN for this device. |
|
*/ |
|
ndev->features |= NETIF_F_VLAN_CHALLENGED; |
|
|
|
err = register_netdev(ndev); |
|
if (err < 0) |
|
goto err_register; |
|
|
|
priv->xfer_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, |
|
netdev_name(ndev)); |
|
if (!priv->xfer_wq) { |
|
err = -ENOMEM; |
|
goto err_wq; |
|
} |
|
|
|
INIT_WORK(&priv->rx_work, w5100_rx_work); |
|
INIT_WORK(&priv->tx_work, w5100_tx_work); |
|
INIT_WORK(&priv->setrx_work, w5100_setrx_work); |
|
INIT_WORK(&priv->restart_work, w5100_restart_work); |
|
|
|
if (mac_addr) |
|
memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); |
|
else |
|
eth_hw_addr_random(ndev); |
|
|
|
if (priv->ops->init) { |
|
err = priv->ops->init(priv->ndev); |
|
if (err) |
|
goto err_hw; |
|
} |
|
|
|
err = w5100_hw_reset(priv); |
|
if (err) |
|
goto err_hw; |
|
|
|
if (ops->may_sleep) { |
|
err = request_threaded_irq(priv->irq, NULL, w5100_interrupt, |
|
IRQF_TRIGGER_LOW | IRQF_ONESHOT, |
|
netdev_name(ndev), ndev); |
|
} else { |
|
err = request_irq(priv->irq, w5100_interrupt, |
|
IRQF_TRIGGER_LOW, netdev_name(ndev), ndev); |
|
} |
|
if (err) |
|
goto err_hw; |
|
|
|
if (gpio_is_valid(priv->link_gpio)) { |
|
char *link_name = devm_kzalloc(dev, 16, GFP_KERNEL); |
|
|
|
if (!link_name) { |
|
err = -ENOMEM; |
|
goto err_gpio; |
|
} |
|
snprintf(link_name, 16, "%s-link", netdev_name(ndev)); |
|
priv->link_irq = gpio_to_irq(priv->link_gpio); |
|
if (request_any_context_irq(priv->link_irq, w5100_detect_link, |
|
IRQF_TRIGGER_RISING | |
|
IRQF_TRIGGER_FALLING, |
|
link_name, priv->ndev) < 0) |
|
priv->link_gpio = -EINVAL; |
|
} |
|
|
|
return 0; |
|
|
|
err_gpio: |
|
free_irq(priv->irq, ndev); |
|
err_hw: |
|
destroy_workqueue(priv->xfer_wq); |
|
err_wq: |
|
unregister_netdev(ndev); |
|
err_register: |
|
free_netdev(ndev); |
|
return err; |
|
} |
|
EXPORT_SYMBOL_GPL(w5100_probe); |
|
|
|
int w5100_remove(struct device *dev) |
|
{ |
|
struct net_device *ndev = dev_get_drvdata(dev); |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
w5100_hw_reset(priv); |
|
free_irq(priv->irq, ndev); |
|
if (gpio_is_valid(priv->link_gpio)) |
|
free_irq(priv->link_irq, ndev); |
|
|
|
flush_work(&priv->setrx_work); |
|
flush_work(&priv->restart_work); |
|
destroy_workqueue(priv->xfer_wq); |
|
|
|
unregister_netdev(ndev); |
|
free_netdev(ndev); |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(w5100_remove); |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int w5100_suspend(struct device *dev) |
|
{ |
|
struct net_device *ndev = dev_get_drvdata(dev); |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
if (netif_running(ndev)) { |
|
netif_carrier_off(ndev); |
|
netif_device_detach(ndev); |
|
|
|
w5100_hw_close(priv); |
|
} |
|
return 0; |
|
} |
|
|
|
static int w5100_resume(struct device *dev) |
|
{ |
|
struct net_device *ndev = dev_get_drvdata(dev); |
|
struct w5100_priv *priv = netdev_priv(ndev); |
|
|
|
if (netif_running(ndev)) { |
|
w5100_hw_reset(priv); |
|
w5100_hw_start(priv); |
|
|
|
netif_device_attach(ndev); |
|
if (!gpio_is_valid(priv->link_gpio) || |
|
gpio_get_value(priv->link_gpio) != 0) |
|
netif_carrier_on(ndev); |
|
} |
|
return 0; |
|
} |
|
#endif /* CONFIG_PM_SLEEP */ |
|
|
|
SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume); |
|
EXPORT_SYMBOL_GPL(w5100_pm_ops); |
|
|
|
static struct platform_driver w5100_mmio_driver = { |
|
.driver = { |
|
.name = DRV_NAME, |
|
.pm = &w5100_pm_ops, |
|
}, |
|
.probe = w5100_mmio_probe, |
|
.remove = w5100_mmio_remove, |
|
}; |
|
module_platform_driver(w5100_mmio_driver);
|
|
|