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912 lines
23 KiB
912 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2007 - 2018 Intel Corporation. */ |
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|
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/* e1000_i210 |
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* e1000_i211 |
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*/ |
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|
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#include <linux/types.h> |
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#include <linux/if_ether.h> |
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|
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#include "e1000_hw.h" |
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#include "e1000_i210.h" |
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|
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static s32 igb_update_flash_i210(struct e1000_hw *hw); |
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|
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/** |
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* igb_get_hw_semaphore_i210 - Acquire hardware semaphore |
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* @hw: pointer to the HW structure |
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* |
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* Acquire the HW semaphore to access the PHY or NVM |
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*/ |
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static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw) |
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{ |
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u32 swsm; |
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s32 timeout = hw->nvm.word_size + 1; |
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s32 i = 0; |
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|
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/* Get the SW semaphore */ |
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while (i < timeout) { |
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swsm = rd32(E1000_SWSM); |
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if (!(swsm & E1000_SWSM_SMBI)) |
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break; |
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udelay(50); |
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i++; |
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} |
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if (i == timeout) { |
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/* In rare circumstances, the SW semaphore may already be held |
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* unintentionally. Clear the semaphore once before giving up. |
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*/ |
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if (hw->dev_spec._82575.clear_semaphore_once) { |
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hw->dev_spec._82575.clear_semaphore_once = false; |
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igb_put_hw_semaphore(hw); |
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for (i = 0; i < timeout; i++) { |
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swsm = rd32(E1000_SWSM); |
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if (!(swsm & E1000_SWSM_SMBI)) |
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break; |
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udelay(50); |
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} |
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} |
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/* If we do not have the semaphore here, we have to give up. */ |
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if (i == timeout) { |
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hw_dbg("Driver can't access device - SMBI bit is set.\n"); |
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return -E1000_ERR_NVM; |
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} |
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} |
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/* Get the FW semaphore. */ |
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for (i = 0; i < timeout; i++) { |
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swsm = rd32(E1000_SWSM); |
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wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); |
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/* Semaphore acquired if bit latched */ |
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if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) |
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break; |
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udelay(50); |
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} |
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if (i == timeout) { |
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/* Release semaphores */ |
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igb_put_hw_semaphore(hw); |
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hw_dbg("Driver can't access the NVM\n"); |
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return -E1000_ERR_NVM; |
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} |
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return 0; |
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} |
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/** |
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* igb_acquire_nvm_i210 - Request for access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Acquire the necessary semaphores for exclusive access to the EEPROM. |
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* Set the EEPROM access request bit and wait for EEPROM access grant bit. |
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* Return successful if access grant bit set, else clear the request for |
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* EEPROM access and return -E1000_ERR_NVM (-1). |
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**/ |
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static s32 igb_acquire_nvm_i210(struct e1000_hw *hw) |
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{ |
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return igb_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM); |
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} |
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/** |
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* igb_release_nvm_i210 - Release exclusive access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Stop any current commands to the EEPROM and clear the EEPROM request bit, |
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* then release the semaphores acquired. |
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**/ |
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static void igb_release_nvm_i210(struct e1000_hw *hw) |
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{ |
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igb_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM); |
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} |
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/** |
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* igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore |
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* @hw: pointer to the HW structure |
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* @mask: specifies which semaphore to acquire |
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* |
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* Acquire the SW/FW semaphore to access the PHY or NVM. The mask |
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* will also specify which port we're acquiring the lock for. |
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**/ |
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s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) |
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{ |
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u32 swfw_sync; |
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u32 swmask = mask; |
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u32 fwmask = mask << 16; |
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s32 ret_val = 0; |
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s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ |
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while (i < timeout) { |
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if (igb_get_hw_semaphore_i210(hw)) { |
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ret_val = -E1000_ERR_SWFW_SYNC; |
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goto out; |
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} |
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swfw_sync = rd32(E1000_SW_FW_SYNC); |
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if (!(swfw_sync & (fwmask | swmask))) |
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break; |
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/* Firmware currently using resource (fwmask) */ |
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igb_put_hw_semaphore(hw); |
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mdelay(5); |
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i++; |
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} |
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if (i == timeout) { |
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hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
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ret_val = -E1000_ERR_SWFW_SYNC; |
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goto out; |
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} |
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swfw_sync |= swmask; |
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wr32(E1000_SW_FW_SYNC, swfw_sync); |
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igb_put_hw_semaphore(hw); |
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out: |
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return ret_val; |
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} |
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/** |
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* igb_release_swfw_sync_i210 - Release SW/FW semaphore |
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* @hw: pointer to the HW structure |
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* @mask: specifies which semaphore to acquire |
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* |
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* Release the SW/FW semaphore used to access the PHY or NVM. The mask |
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* will also specify which port we're releasing the lock for. |
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**/ |
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void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) |
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{ |
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u32 swfw_sync; |
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while (igb_get_hw_semaphore_i210(hw)) |
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; /* Empty */ |
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swfw_sync = rd32(E1000_SW_FW_SYNC); |
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swfw_sync &= ~mask; |
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wr32(E1000_SW_FW_SYNC, swfw_sync); |
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igb_put_hw_semaphore(hw); |
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} |
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/** |
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* igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register |
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* @hw: pointer to the HW structure |
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* @offset: offset of word in the Shadow Ram to read |
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* @words: number of words to read |
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* @data: word read from the Shadow Ram |
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* |
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* Reads a 16 bit word from the Shadow Ram using the EERD register. |
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* Uses necessary synchronization semaphores. |
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**/ |
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static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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s32 status = 0; |
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u16 i, count; |
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/* We cannot hold synchronization semaphores for too long, |
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* because of forceful takeover procedure. However it is more efficient |
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* to read in bursts than synchronizing access for each word. |
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*/ |
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for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) { |
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count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ? |
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E1000_EERD_EEWR_MAX_COUNT : (words - i); |
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if (!(hw->nvm.ops.acquire(hw))) { |
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status = igb_read_nvm_eerd(hw, offset, count, |
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data + i); |
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hw->nvm.ops.release(hw); |
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} else { |
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status = E1000_ERR_SWFW_SYNC; |
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} |
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if (status) |
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break; |
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} |
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return status; |
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} |
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/** |
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* igb_write_nvm_srwr - Write to Shadow Ram using EEWR |
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* @hw: pointer to the HW structure |
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* @offset: offset within the Shadow Ram to be written to |
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* @words: number of words to write |
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* @data: 16 bit word(s) to be written to the Shadow Ram |
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* |
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* Writes data to Shadow Ram at offset using EEWR register. |
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* |
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* If igb_update_nvm_checksum is not called after this function , the |
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* Shadow Ram will most likely contain an invalid checksum. |
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**/ |
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static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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u32 i, k, eewr = 0; |
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u32 attempts = 100000; |
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s32 ret_val = 0; |
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/* A check for invalid values: offset too large, too many words, |
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* too many words for the offset, and not enough words. |
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*/ |
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
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(words == 0)) { |
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hw_dbg("nvm parameter(s) out of bounds\n"); |
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ret_val = -E1000_ERR_NVM; |
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goto out; |
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} |
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for (i = 0; i < words; i++) { |
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eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | |
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(data[i] << E1000_NVM_RW_REG_DATA) | |
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E1000_NVM_RW_REG_START; |
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wr32(E1000_SRWR, eewr); |
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for (k = 0; k < attempts; k++) { |
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if (E1000_NVM_RW_REG_DONE & |
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rd32(E1000_SRWR)) { |
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ret_val = 0; |
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break; |
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} |
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udelay(5); |
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} |
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if (ret_val) { |
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hw_dbg("Shadow RAM write EEWR timed out\n"); |
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break; |
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} |
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} |
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out: |
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return ret_val; |
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} |
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/** |
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* igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR |
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* @hw: pointer to the HW structure |
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* @offset: offset within the Shadow RAM to be written to |
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* @words: number of words to write |
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* @data: 16 bit word(s) to be written to the Shadow RAM |
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* |
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* Writes data to Shadow RAM at offset using EEWR register. |
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* |
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* If e1000_update_nvm_checksum is not called after this function , the |
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* data will not be committed to FLASH and also Shadow RAM will most likely |
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* contain an invalid checksum. |
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* |
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* If error code is returned, data and Shadow RAM may be inconsistent - buffer |
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* partially written. |
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**/ |
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static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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s32 status = 0; |
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u16 i, count; |
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/* We cannot hold synchronization semaphores for too long, |
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* because of forceful takeover procedure. However it is more efficient |
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* to write in bursts than synchronizing access for each word. |
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*/ |
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for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) { |
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count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ? |
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E1000_EERD_EEWR_MAX_COUNT : (words - i); |
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if (!(hw->nvm.ops.acquire(hw))) { |
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status = igb_write_nvm_srwr(hw, offset, count, |
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data + i); |
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hw->nvm.ops.release(hw); |
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} else { |
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status = E1000_ERR_SWFW_SYNC; |
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} |
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if (status) |
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break; |
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} |
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return status; |
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} |
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/** |
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* igb_read_invm_word_i210 - Reads OTP |
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* @hw: pointer to the HW structure |
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* @address: the word address (aka eeprom offset) to read |
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* @data: pointer to the data read |
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* |
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* Reads 16-bit words from the OTP. Return error when the word is not |
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* stored in OTP. |
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**/ |
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static s32 igb_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data) |
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{ |
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s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND; |
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u32 invm_dword; |
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u16 i; |
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u8 record_type, word_address; |
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for (i = 0; i < E1000_INVM_SIZE; i++) { |
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invm_dword = rd32(E1000_INVM_DATA_REG(i)); |
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/* Get record type */ |
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record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); |
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if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE) |
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break; |
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if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE) |
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i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; |
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if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE) |
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i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; |
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if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) { |
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word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); |
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if (word_address == address) { |
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*data = INVM_DWORD_TO_WORD_DATA(invm_dword); |
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hw_dbg("Read INVM Word 0x%02x = %x\n", |
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address, *data); |
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status = 0; |
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break; |
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} |
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} |
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} |
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if (status) |
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hw_dbg("Requested word 0x%02x not found in OTP\n", address); |
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return status; |
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} |
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/** |
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* igb_read_invm_i210 - Read invm wrapper function for I210/I211 |
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* @hw: pointer to the HW structure |
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* @offset: offset to read from |
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* @words: number of words to read (unused) |
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* @data: pointer to the data read |
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* |
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* Wrapper function to return data formerly found in the NVM. |
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**/ |
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static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset, |
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u16 __always_unused words, u16 *data) |
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{ |
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s32 ret_val = 0; |
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/* Only the MAC addr is required to be present in the iNVM */ |
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switch (offset) { |
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case NVM_MAC_ADDR: |
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ret_val = igb_read_invm_word_i210(hw, (u8)offset, &data[0]); |
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ret_val |= igb_read_invm_word_i210(hw, (u8)offset+1, |
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&data[1]); |
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ret_val |= igb_read_invm_word_i210(hw, (u8)offset+2, |
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&data[2]); |
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if (ret_val) |
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hw_dbg("MAC Addr not found in iNVM\n"); |
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break; |
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case NVM_INIT_CTRL_2: |
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ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
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if (ret_val) { |
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*data = NVM_INIT_CTRL_2_DEFAULT_I211; |
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ret_val = 0; |
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} |
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break; |
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case NVM_INIT_CTRL_4: |
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ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
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if (ret_val) { |
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*data = NVM_INIT_CTRL_4_DEFAULT_I211; |
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ret_val = 0; |
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} |
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break; |
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case NVM_LED_1_CFG: |
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ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
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if (ret_val) { |
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*data = NVM_LED_1_CFG_DEFAULT_I211; |
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ret_val = 0; |
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} |
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break; |
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case NVM_LED_0_2_CFG: |
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ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
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if (ret_val) { |
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*data = NVM_LED_0_2_CFG_DEFAULT_I211; |
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ret_val = 0; |
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} |
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break; |
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case NVM_ID_LED_SETTINGS: |
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ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
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if (ret_val) { |
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*data = ID_LED_RESERVED_FFFF; |
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ret_val = 0; |
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} |
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break; |
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case NVM_SUB_DEV_ID: |
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*data = hw->subsystem_device_id; |
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break; |
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case NVM_SUB_VEN_ID: |
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*data = hw->subsystem_vendor_id; |
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break; |
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case NVM_DEV_ID: |
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*data = hw->device_id; |
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break; |
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case NVM_VEN_ID: |
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*data = hw->vendor_id; |
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break; |
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default: |
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hw_dbg("NVM word 0x%02x is not mapped.\n", offset); |
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*data = NVM_RESERVED_WORD; |
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break; |
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} |
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return ret_val; |
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} |
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/** |
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* igb_read_invm_version - Reads iNVM version and image type |
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* @hw: pointer to the HW structure |
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* @invm_ver: version structure for the version read |
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* |
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* Reads iNVM version and image type. |
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**/ |
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s32 igb_read_invm_version(struct e1000_hw *hw, |
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struct e1000_fw_version *invm_ver) { |
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u32 *record = NULL; |
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u32 *next_record = NULL; |
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u32 i = 0; |
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u32 invm_dword = 0; |
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u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE / |
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E1000_INVM_RECORD_SIZE_IN_BYTES); |
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u32 buffer[E1000_INVM_SIZE]; |
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s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND; |
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u16 version = 0; |
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|
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/* Read iNVM memory */ |
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for (i = 0; i < E1000_INVM_SIZE; i++) { |
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invm_dword = rd32(E1000_INVM_DATA_REG(i)); |
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buffer[i] = invm_dword; |
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} |
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|
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/* Read version number */ |
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for (i = 1; i < invm_blocks; i++) { |
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record = &buffer[invm_blocks - i]; |
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next_record = &buffer[invm_blocks - i + 1]; |
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|
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/* Check if we have first version location used */ |
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if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) { |
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version = 0; |
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status = 0; |
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break; |
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} |
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/* Check if we have second version location used */ |
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else if ((i == 1) && |
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((*record & E1000_INVM_VER_FIELD_TWO) == 0)) { |
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version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; |
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status = 0; |
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break; |
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} |
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/* Check if we have odd version location |
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* used and it is the last one used |
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*/ |
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else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) && |
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((*record & 0x3) == 0)) || (((*record & 0x3) != 0) && |
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(i != 1))) { |
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version = (*next_record & E1000_INVM_VER_FIELD_TWO) |
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>> 13; |
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status = 0; |
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break; |
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} |
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/* Check if we have even version location |
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* used and it is the last one used |
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*/ |
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else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) && |
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((*record & 0x3) == 0)) { |
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version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; |
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status = 0; |
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break; |
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} |
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} |
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|
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if (!status) { |
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invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK) |
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>> E1000_INVM_MAJOR_SHIFT; |
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invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK; |
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} |
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/* Read Image Type */ |
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for (i = 1; i < invm_blocks; i++) { |
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record = &buffer[invm_blocks - i]; |
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next_record = &buffer[invm_blocks - i + 1]; |
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|
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/* Check if we have image type in first location used */ |
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if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) { |
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invm_ver->invm_img_type = 0; |
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status = 0; |
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break; |
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} |
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/* Check if we have image type in first location used */ |
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else if ((((*record & 0x3) == 0) && |
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((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) || |
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((((*record & 0x3) != 0) && (i != 1)))) { |
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invm_ver->invm_img_type = |
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(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23; |
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status = 0; |
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break; |
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} |
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} |
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return status; |
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} |
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|
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/** |
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* igb_validate_nvm_checksum_i210 - Validate EEPROM checksum |
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* @hw: pointer to the HW structure |
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* |
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* Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
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* and then verifies that the sum of the EEPROM is equal to 0xBABA. |
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**/ |
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static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw) |
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{ |
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s32 status = 0; |
|
s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *); |
|
|
|
if (!(hw->nvm.ops.acquire(hw))) { |
|
|
|
/* Replace the read function with semaphore grabbing with |
|
* the one that skips this for a while. |
|
* We have semaphore taken already here. |
|
*/ |
|
read_op_ptr = hw->nvm.ops.read; |
|
hw->nvm.ops.read = igb_read_nvm_eerd; |
|
|
|
status = igb_validate_nvm_checksum(hw); |
|
|
|
/* Revert original read operation. */ |
|
hw->nvm.ops.read = read_op_ptr; |
|
|
|
hw->nvm.ops.release(hw); |
|
} else { |
|
status = E1000_ERR_SWFW_SYNC; |
|
} |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* igb_update_nvm_checksum_i210 - Update EEPROM checksum |
|
* @hw: pointer to the HW structure |
|
* |
|
* Updates the EEPROM checksum by reading/adding each word of the EEPROM |
|
* up to the checksum. Then calculates the EEPROM checksum and writes the |
|
* value to the EEPROM. Next commit EEPROM data onto the Flash. |
|
**/ |
|
static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val = 0; |
|
u16 checksum = 0; |
|
u16 i, nvm_data; |
|
|
|
/* Read the first word from the EEPROM. If this times out or fails, do |
|
* not continue or we could be in for a very long wait while every |
|
* EEPROM read fails |
|
*/ |
|
ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data); |
|
if (ret_val) { |
|
hw_dbg("EEPROM read failed\n"); |
|
goto out; |
|
} |
|
|
|
if (!(hw->nvm.ops.acquire(hw))) { |
|
/* Do not use hw->nvm.ops.write, hw->nvm.ops.read |
|
* because we do not want to take the synchronization |
|
* semaphores twice here. |
|
*/ |
|
|
|
for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
|
ret_val = igb_read_nvm_eerd(hw, i, 1, &nvm_data); |
|
if (ret_val) { |
|
hw->nvm.ops.release(hw); |
|
hw_dbg("NVM Read Error while updating checksum.\n"); |
|
goto out; |
|
} |
|
checksum += nvm_data; |
|
} |
|
checksum = (u16) NVM_SUM - checksum; |
|
ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, |
|
&checksum); |
|
if (ret_val) { |
|
hw->nvm.ops.release(hw); |
|
hw_dbg("NVM Write Error while updating checksum.\n"); |
|
goto out; |
|
} |
|
|
|
hw->nvm.ops.release(hw); |
|
|
|
ret_val = igb_update_flash_i210(hw); |
|
} else { |
|
ret_val = -E1000_ERR_SWFW_SYNC; |
|
} |
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_pool_flash_update_done_i210 - Pool FLUDONE status. |
|
* @hw: pointer to the HW structure |
|
* |
|
**/ |
|
static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val = -E1000_ERR_NVM; |
|
u32 i, reg; |
|
|
|
for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) { |
|
reg = rd32(E1000_EECD); |
|
if (reg & E1000_EECD_FLUDONE_I210) { |
|
ret_val = 0; |
|
break; |
|
} |
|
udelay(5); |
|
} |
|
|
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_get_flash_presence_i210 - Check if flash device is detected. |
|
* @hw: pointer to the HW structure |
|
* |
|
**/ |
|
bool igb_get_flash_presence_i210(struct e1000_hw *hw) |
|
{ |
|
u32 eec = 0; |
|
bool ret_val = false; |
|
|
|
eec = rd32(E1000_EECD); |
|
if (eec & E1000_EECD_FLASH_DETECTED_I210) |
|
ret_val = true; |
|
|
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_update_flash_i210 - Commit EEPROM to the flash |
|
* @hw: pointer to the HW structure |
|
* |
|
**/ |
|
static s32 igb_update_flash_i210(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val = 0; |
|
u32 flup; |
|
|
|
ret_val = igb_pool_flash_update_done_i210(hw); |
|
if (ret_val == -E1000_ERR_NVM) { |
|
hw_dbg("Flash update time out\n"); |
|
goto out; |
|
} |
|
|
|
flup = rd32(E1000_EECD) | E1000_EECD_FLUPD_I210; |
|
wr32(E1000_EECD, flup); |
|
|
|
ret_val = igb_pool_flash_update_done_i210(hw); |
|
if (ret_val) |
|
hw_dbg("Flash update time out\n"); |
|
else |
|
hw_dbg("Flash update complete\n"); |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_valid_led_default_i210 - Verify a valid default LED config |
|
* @hw: pointer to the HW structure |
|
* @data: pointer to the NVM (EEPROM) |
|
* |
|
* Read the EEPROM for the current default LED configuration. If the |
|
* LED configuration is not valid, set to a valid LED configuration. |
|
**/ |
|
s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data) |
|
{ |
|
s32 ret_val; |
|
|
|
ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); |
|
if (ret_val) { |
|
hw_dbg("NVM Read Error\n"); |
|
goto out; |
|
} |
|
|
|
if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { |
|
switch (hw->phy.media_type) { |
|
case e1000_media_type_internal_serdes: |
|
*data = ID_LED_DEFAULT_I210_SERDES; |
|
break; |
|
case e1000_media_type_copper: |
|
default: |
|
*data = ID_LED_DEFAULT_I210; |
|
break; |
|
} |
|
} |
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* __igb_access_xmdio_reg - Read/write XMDIO register |
|
* @hw: pointer to the HW structure |
|
* @address: XMDIO address to program |
|
* @dev_addr: device address to program |
|
* @data: pointer to value to read/write from/to the XMDIO address |
|
* @read: boolean flag to indicate read or write |
|
**/ |
|
static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address, |
|
u8 dev_addr, u16 *data, bool read) |
|
{ |
|
s32 ret_val = 0; |
|
|
|
ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); |
|
if (ret_val) |
|
return ret_val; |
|
|
|
ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); |
|
if (ret_val) |
|
return ret_val; |
|
|
|
ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | |
|
dev_addr); |
|
if (ret_val) |
|
return ret_val; |
|
|
|
if (read) |
|
ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data); |
|
else |
|
ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); |
|
if (ret_val) |
|
return ret_val; |
|
|
|
/* Recalibrate the device back to 0 */ |
|
ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0); |
|
if (ret_val) |
|
return ret_val; |
|
|
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_read_xmdio_reg - Read XMDIO register |
|
* @hw: pointer to the HW structure |
|
* @addr: XMDIO address to program |
|
* @dev_addr: device address to program |
|
* @data: value to be read from the EMI address |
|
**/ |
|
s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data) |
|
{ |
|
return __igb_access_xmdio_reg(hw, addr, dev_addr, data, true); |
|
} |
|
|
|
/** |
|
* igb_write_xmdio_reg - Write XMDIO register |
|
* @hw: pointer to the HW structure |
|
* @addr: XMDIO address to program |
|
* @dev_addr: device address to program |
|
* @data: value to be written to the XMDIO address |
|
**/ |
|
s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data) |
|
{ |
|
return __igb_access_xmdio_reg(hw, addr, dev_addr, &data, false); |
|
} |
|
|
|
/** |
|
* igb_init_nvm_params_i210 - Init NVM func ptrs. |
|
* @hw: pointer to the HW structure |
|
**/ |
|
s32 igb_init_nvm_params_i210(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val = 0; |
|
struct e1000_nvm_info *nvm = &hw->nvm; |
|
|
|
nvm->ops.acquire = igb_acquire_nvm_i210; |
|
nvm->ops.release = igb_release_nvm_i210; |
|
nvm->ops.valid_led_default = igb_valid_led_default_i210; |
|
|
|
/* NVM Function Pointers */ |
|
if (igb_get_flash_presence_i210(hw)) { |
|
hw->nvm.type = e1000_nvm_flash_hw; |
|
nvm->ops.read = igb_read_nvm_srrd_i210; |
|
nvm->ops.write = igb_write_nvm_srwr_i210; |
|
nvm->ops.validate = igb_validate_nvm_checksum_i210; |
|
nvm->ops.update = igb_update_nvm_checksum_i210; |
|
} else { |
|
hw->nvm.type = e1000_nvm_invm; |
|
nvm->ops.read = igb_read_invm_i210; |
|
nvm->ops.write = NULL; |
|
nvm->ops.validate = NULL; |
|
nvm->ops.update = NULL; |
|
} |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_pll_workaround_i210 |
|
* @hw: pointer to the HW structure |
|
* |
|
* Works around an errata in the PLL circuit where it occasionally |
|
* provides the wrong clock frequency after power up. |
|
**/ |
|
s32 igb_pll_workaround_i210(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val; |
|
u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; |
|
u16 nvm_word, phy_word, pci_word, tmp_nvm; |
|
int i; |
|
|
|
/* Get and set needed register values */ |
|
wuc = rd32(E1000_WUC); |
|
mdicnfg = rd32(E1000_MDICNFG); |
|
reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; |
|
wr32(E1000_MDICNFG, reg_val); |
|
|
|
/* Get data from NVM, or set default */ |
|
ret_val = igb_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD, |
|
&nvm_word); |
|
if (ret_val) |
|
nvm_word = E1000_INVM_DEFAULT_AL; |
|
tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL; |
|
igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, E1000_PHY_PLL_FREQ_PAGE); |
|
phy_word = E1000_PHY_PLL_UNCONF; |
|
for (i = 0; i < E1000_MAX_PLL_TRIES; i++) { |
|
/* check current state directly from internal PHY */ |
|
igb_read_phy_reg_82580(hw, E1000_PHY_PLL_FREQ_REG, &phy_word); |
|
if ((phy_word & E1000_PHY_PLL_UNCONF) |
|
!= E1000_PHY_PLL_UNCONF) { |
|
ret_val = 0; |
|
break; |
|
} else { |
|
ret_val = -E1000_ERR_PHY; |
|
} |
|
/* directly reset the internal PHY */ |
|
ctrl = rd32(E1000_CTRL); |
|
wr32(E1000_CTRL, ctrl|E1000_CTRL_PHY_RST); |
|
|
|
ctrl_ext = rd32(E1000_CTRL_EXT); |
|
ctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE); |
|
wr32(E1000_CTRL_EXT, ctrl_ext); |
|
|
|
wr32(E1000_WUC, 0); |
|
reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); |
|
wr32(E1000_EEARBC_I210, reg_val); |
|
|
|
igb_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); |
|
pci_word |= E1000_PCI_PMCSR_D3; |
|
igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); |
|
usleep_range(1000, 2000); |
|
pci_word &= ~E1000_PCI_PMCSR_D3; |
|
igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); |
|
reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); |
|
wr32(E1000_EEARBC_I210, reg_val); |
|
|
|
/* restore WUC register */ |
|
wr32(E1000_WUC, wuc); |
|
} |
|
igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0); |
|
/* restore MDICNFG setting */ |
|
wr32(E1000_MDICNFG, mdicnfg); |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_get_cfg_done_i210 - Read config done bit |
|
* @hw: pointer to the HW structure |
|
* |
|
* Read the management control register for the config done bit for |
|
* completion status. NOTE: silicon which is EEPROM-less will fail trying |
|
* to read the config done bit, so an error is *ONLY* logged and returns |
|
* 0. If we were to return with error, EEPROM-less silicon |
|
* would not be able to be reset or change link. |
|
**/ |
|
s32 igb_get_cfg_done_i210(struct e1000_hw *hw) |
|
{ |
|
s32 timeout = PHY_CFG_TIMEOUT; |
|
u32 mask = E1000_NVM_CFG_DONE_PORT_0; |
|
|
|
while (timeout) { |
|
if (rd32(E1000_EEMNGCTL_I210) & mask) |
|
break; |
|
usleep_range(1000, 2000); |
|
timeout--; |
|
} |
|
if (!timeout) |
|
hw_dbg("MNG configuration cycle has not completed.\n"); |
|
|
|
return 0; |
|
}
|
|
|