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539 lines
14 KiB
539 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation |
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* Provides Bus interface for MIIM regs |
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* |
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* Author: Andy Fleming <[email protected]> |
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* Modifier: Sandeep Gopalpet <[email protected]> |
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* |
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* Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. |
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* |
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* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/errno.h> |
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#include <linux/slab.h> |
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#include <linux/delay.h> |
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#include <linux/module.h> |
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#include <linux/mii.h> |
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#include <linux/of_address.h> |
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#include <linux/of_mdio.h> |
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#include <linux/of_device.h> |
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|
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#include <asm/io.h> |
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#if IS_ENABLED(CONFIG_UCC_GETH) |
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#include <soc/fsl/qe/ucc.h> |
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#endif |
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|
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#include "gianfar.h" |
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|
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#define MIIMIND_BUSY 0x00000001 |
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#define MIIMIND_NOTVALID 0x00000004 |
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#define MIIMCFG_INIT_VALUE 0x00000007 |
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#define MIIMCFG_RESET 0x80000000 |
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#define MII_READ_COMMAND 0x00000001 |
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struct fsl_pq_mii { |
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u32 miimcfg; /* MII management configuration reg */ |
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u32 miimcom; /* MII management command reg */ |
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u32 miimadd; /* MII management address reg */ |
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u32 miimcon; /* MII management control reg */ |
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u32 miimstat; /* MII management status reg */ |
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u32 miimind; /* MII management indication reg */ |
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}; |
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|
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struct fsl_pq_mdio { |
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u8 res1[16]; |
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u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ |
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u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ |
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u8 res2[4]; |
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u32 emapm; /* MDIO Event mapping register (for etsec2)*/ |
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u8 res3[1280]; |
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struct fsl_pq_mii mii; |
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u8 res4[28]; |
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u32 utbipar; /* TBI phy address reg (only on UCC) */ |
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u8 res5[2728]; |
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} __packed; |
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|
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/* Number of microseconds to wait for an MII register to respond */ |
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#define MII_TIMEOUT 1000 |
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struct fsl_pq_mdio_priv { |
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void __iomem *map; |
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struct fsl_pq_mii __iomem *regs; |
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}; |
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|
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/* |
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* Per-device-type data. Each type of device tree node that we support gets |
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* one of these. |
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* |
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* @mii_offset: the offset of the MII registers within the memory map of the |
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* node. Some nodes define only the MII registers, and some define the whole |
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* MAC (which includes the MII registers). |
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* |
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* @get_tbipa: determines the address of the TBIPA register |
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* |
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* @ucc_configure: a special function for extra QE configuration |
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*/ |
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struct fsl_pq_mdio_data { |
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unsigned int mii_offset; /* offset of the MII registers */ |
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uint32_t __iomem * (*get_tbipa)(void __iomem *p); |
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void (*ucc_configure)(phys_addr_t start, phys_addr_t end); |
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}; |
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|
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/* |
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* Write value to the PHY at mii_id at register regnum, on the bus attached |
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* to the local interface, which may be different from the generic mdio bus |
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* (tied to a single interface), waiting until the write is done before |
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* returning. This is helpful in programming interfaces like the TBI which |
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* control interfaces like onchip SERDES and are always tied to the local |
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* mdio pins, which may not be the same as system mdio bus, used for |
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* controlling the external PHYs, for example. |
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*/ |
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static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
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u16 value) |
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{ |
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struct fsl_pq_mdio_priv *priv = bus->priv; |
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struct fsl_pq_mii __iomem *regs = priv->regs; |
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unsigned int timeout; |
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/* Set the PHY address and the register address we want to write */ |
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iowrite32be((mii_id << 8) | regnum, ®s->miimadd); |
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|
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/* Write out the value we want */ |
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iowrite32be(value, ®s->miimcon); |
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|
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/* Wait for the transaction to finish */ |
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timeout = MII_TIMEOUT; |
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while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { |
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cpu_relax(); |
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timeout--; |
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} |
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return timeout ? 0 : -ETIMEDOUT; |
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} |
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/* |
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* Read the bus for PHY at addr mii_id, register regnum, and return the value. |
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* Clears miimcom first. |
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* |
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* All PHY operation done on the bus attached to the local interface, which |
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* may be different from the generic mdio bus. This is helpful in programming |
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* interfaces like the TBI which, in turn, control interfaces like on-chip |
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* SERDES and are always tied to the local mdio pins, which may not be the |
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* same as system mdio bus, used for controlling the external PHYs, for eg. |
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*/ |
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static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
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{ |
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struct fsl_pq_mdio_priv *priv = bus->priv; |
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struct fsl_pq_mii __iomem *regs = priv->regs; |
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unsigned int timeout; |
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u16 value; |
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/* Set the PHY address and the register address we want to read */ |
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iowrite32be((mii_id << 8) | regnum, ®s->miimadd); |
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|
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/* Clear miimcom, and then initiate a read */ |
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iowrite32be(0, ®s->miimcom); |
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iowrite32be(MII_READ_COMMAND, ®s->miimcom); |
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|
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/* Wait for the transaction to finish, normally less than 100us */ |
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timeout = MII_TIMEOUT; |
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while ((ioread32be(®s->miimind) & |
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(MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) { |
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cpu_relax(); |
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timeout--; |
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} |
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if (!timeout) |
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return -ETIMEDOUT; |
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|
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/* Grab the value of the register from miimstat */ |
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value = ioread32be(®s->miimstat); |
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dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); |
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return value; |
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} |
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/* Reset the MIIM registers, and wait for the bus to free */ |
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static int fsl_pq_mdio_reset(struct mii_bus *bus) |
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{ |
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struct fsl_pq_mdio_priv *priv = bus->priv; |
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struct fsl_pq_mii __iomem *regs = priv->regs; |
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unsigned int timeout; |
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mutex_lock(&bus->mdio_lock); |
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/* Reset the management interface */ |
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iowrite32be(MIIMCFG_RESET, ®s->miimcfg); |
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|
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/* Setup the MII Mgmt clock speed */ |
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iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg); |
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|
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/* Wait until the bus is free */ |
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timeout = MII_TIMEOUT; |
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while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { |
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cpu_relax(); |
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timeout--; |
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} |
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mutex_unlock(&bus->mdio_lock); |
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if (!timeout) { |
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dev_err(&bus->dev, "timeout waiting for MII bus\n"); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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#if IS_ENABLED(CONFIG_GIANFAR) |
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/* |
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* Return the TBIPA address, starting from the address |
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* of the mapped GFAR MDIO registers (struct gfar) |
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* This is mildly evil, but so is our hardware for doing this. |
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* Also, we have to cast back to struct gfar because of |
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* definition weirdness done in gianfar.h. |
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*/ |
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static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p) |
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{ |
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struct gfar __iomem *enet_regs = p; |
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return &enet_regs->tbipa; |
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} |
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/* |
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* Return the TBIPA address, starting from the address |
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* of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar) |
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*/ |
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static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p) |
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{ |
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return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs)); |
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} |
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/* |
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* Return the TBIPAR address for an eTSEC2 node |
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*/ |
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static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) |
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{ |
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return p; |
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} |
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#endif |
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#if IS_ENABLED(CONFIG_UCC_GETH) |
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/* |
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* Return the TBIPAR address for a QE MDIO node, starting from the address |
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* of the mapped MII registers (struct fsl_pq_mii) |
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*/ |
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static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) |
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{ |
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struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii); |
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return &mdio->utbipar; |
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} |
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/* |
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* Find the UCC node that controls the given MDIO node |
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* |
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* For some reason, the QE MDIO nodes are not children of the UCC devices |
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* that control them. Therefore, we need to scan all UCC nodes looking for |
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* the one that encompases the given MDIO node. We do this by comparing |
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* physical addresses. The 'start' and 'end' addresses of the MDIO node are |
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* passed, and the correct UCC node will cover the entire address range. |
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* |
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* This assumes that there is only one QE MDIO node in the entire device tree. |
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*/ |
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static void ucc_configure(phys_addr_t start, phys_addr_t end) |
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{ |
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static bool found_mii_master; |
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struct device_node *np = NULL; |
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if (found_mii_master) |
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return; |
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for_each_compatible_node(np, NULL, "ucc_geth") { |
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struct resource res; |
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const uint32_t *iprop; |
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uint32_t id; |
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int ret; |
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ret = of_address_to_resource(np, 0, &res); |
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if (ret < 0) { |
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pr_debug("fsl-pq-mdio: no address range in node %pOF\n", |
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np); |
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continue; |
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} |
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/* if our mdio regs fall within this UCC regs range */ |
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if ((start < res.start) || (end > res.end)) |
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continue; |
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iprop = of_get_property(np, "cell-index", NULL); |
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if (!iprop) { |
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iprop = of_get_property(np, "device-id", NULL); |
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if (!iprop) { |
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pr_debug("fsl-pq-mdio: no UCC ID in node %pOF\n", |
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np); |
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continue; |
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} |
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} |
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id = be32_to_cpup(iprop); |
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/* |
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* cell-index and device-id for QE nodes are |
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* numbered from 1, not 0. |
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*/ |
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if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { |
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pr_debug("fsl-pq-mdio: invalid UCC ID in node %pOF\n", |
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np); |
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continue; |
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} |
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pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); |
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found_mii_master = true; |
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} |
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} |
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#endif |
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static const struct of_device_id fsl_pq_mdio_match[] = { |
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#if IS_ENABLED(CONFIG_GIANFAR) |
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{ |
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.compatible = "fsl,gianfar-tbi", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = 0, |
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.get_tbipa = get_gfar_tbipa_from_mii, |
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}, |
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}, |
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{ |
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.compatible = "fsl,gianfar-mdio", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = 0, |
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.get_tbipa = get_gfar_tbipa_from_mii, |
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}, |
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}, |
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{ |
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.type = "mdio", |
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.compatible = "gianfar", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = offsetof(struct fsl_pq_mdio, mii), |
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.get_tbipa = get_gfar_tbipa_from_mdio, |
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}, |
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}, |
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{ |
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.compatible = "fsl,etsec2-tbi", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = offsetof(struct fsl_pq_mdio, mii), |
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.get_tbipa = get_etsec_tbipa, |
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}, |
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}, |
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{ |
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.compatible = "fsl,etsec2-mdio", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = offsetof(struct fsl_pq_mdio, mii), |
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.get_tbipa = get_etsec_tbipa, |
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}, |
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}, |
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#endif |
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#if IS_ENABLED(CONFIG_UCC_GETH) |
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{ |
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.compatible = "fsl,ucc-mdio", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = 0, |
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.get_tbipa = get_ucc_tbipa, |
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.ucc_configure = ucc_configure, |
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}, |
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}, |
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{ |
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/* Legacy UCC MDIO node */ |
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.type = "mdio", |
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.compatible = "ucc_geth_phy", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = 0, |
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.get_tbipa = get_ucc_tbipa, |
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.ucc_configure = ucc_configure, |
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}, |
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}, |
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#endif |
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/* No Kconfig option for Fman support yet */ |
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{ |
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.compatible = "fsl,fman-mdio", |
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.data = &(struct fsl_pq_mdio_data) { |
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.mii_offset = 0, |
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/* Fman TBI operations are handled elsewhere */ |
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}, |
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}, |
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|
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); |
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static void set_tbipa(const u32 tbipa_val, struct platform_device *pdev, |
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uint32_t __iomem * (*get_tbipa)(void __iomem *), |
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void __iomem *reg_map, struct resource *reg_res) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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uint32_t __iomem *tbipa; |
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bool tbipa_mapped; |
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tbipa = of_iomap(np, 1); |
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if (tbipa) { |
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tbipa_mapped = true; |
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} else { |
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tbipa_mapped = false; |
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tbipa = (*get_tbipa)(reg_map); |
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/* |
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* Add consistency check to make sure TBI is contained within |
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* the mapped range (not because we would get a segfault, |
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* rather to catch bugs in computing TBI address). Print error |
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* message but continue anyway. |
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*/ |
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if ((void *)tbipa > reg_map + resource_size(reg_res) - 4) |
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dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n", |
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((void *)tbipa - reg_map) + 4); |
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} |
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iowrite32be(be32_to_cpu(tbipa_val), tbipa); |
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if (tbipa_mapped) |
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iounmap(tbipa); |
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} |
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static int fsl_pq_mdio_probe(struct platform_device *pdev) |
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{ |
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const struct of_device_id *id = |
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of_match_device(fsl_pq_mdio_match, &pdev->dev); |
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const struct fsl_pq_mdio_data *data; |
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struct device_node *np = pdev->dev.of_node; |
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struct resource res; |
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struct device_node *tbi; |
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struct fsl_pq_mdio_priv *priv; |
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struct mii_bus *new_bus; |
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int err; |
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if (!id) { |
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dev_err(&pdev->dev, "Failed to match device\n"); |
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return -ENODEV; |
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} |
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data = id->data; |
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dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); |
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new_bus = mdiobus_alloc_size(sizeof(*priv)); |
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if (!new_bus) |
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return -ENOMEM; |
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priv = new_bus->priv; |
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new_bus->name = "Freescale PowerQUICC MII Bus"; |
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new_bus->read = &fsl_pq_mdio_read; |
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new_bus->write = &fsl_pq_mdio_write; |
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new_bus->reset = &fsl_pq_mdio_reset; |
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err = of_address_to_resource(np, 0, &res); |
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if (err < 0) { |
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dev_err(&pdev->dev, "could not obtain address information\n"); |
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goto error; |
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} |
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snprintf(new_bus->id, MII_BUS_ID_SIZE, "%pOFn@%llx", np, |
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(unsigned long long)res.start); |
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priv->map = of_iomap(np, 0); |
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if (!priv->map) { |
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err = -ENOMEM; |
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goto error; |
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} |
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|
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/* |
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* Some device tree nodes represent only the MII registers, and |
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* others represent the MAC and MII registers. The 'mii_offset' field |
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* contains the offset of the MII registers inside the mapped register |
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* space. |
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*/ |
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if (data->mii_offset > resource_size(&res)) { |
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dev_err(&pdev->dev, "invalid register map\n"); |
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err = -EINVAL; |
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goto error; |
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} |
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priv->regs = priv->map + data->mii_offset; |
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|
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new_bus->parent = &pdev->dev; |
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platform_set_drvdata(pdev, new_bus); |
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|
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if (data->get_tbipa) { |
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for_each_child_of_node(np, tbi) { |
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if (of_node_is_type(tbi, "tbi-phy")) { |
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dev_dbg(&pdev->dev, "found TBI PHY node %pOFP\n", |
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tbi); |
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break; |
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} |
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} |
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|
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if (tbi) { |
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const u32 *prop = of_get_property(tbi, "reg", NULL); |
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if (!prop) { |
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dev_err(&pdev->dev, |
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"missing 'reg' property in node %pOF\n", |
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tbi); |
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err = -EBUSY; |
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goto error; |
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} |
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set_tbipa(*prop, pdev, |
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data->get_tbipa, priv->map, &res); |
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} |
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} |
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|
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if (data->ucc_configure) |
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data->ucc_configure(res.start, res.end); |
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|
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err = of_mdiobus_register(new_bus, np); |
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if (err) { |
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dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", |
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new_bus->name); |
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goto error; |
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} |
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return 0; |
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error: |
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if (priv->map) |
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iounmap(priv->map); |
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kfree(new_bus); |
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return err; |
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} |
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static int fsl_pq_mdio_remove(struct platform_device *pdev) |
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{ |
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struct device *device = &pdev->dev; |
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struct mii_bus *bus = dev_get_drvdata(device); |
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struct fsl_pq_mdio_priv *priv = bus->priv; |
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mdiobus_unregister(bus); |
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iounmap(priv->map); |
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mdiobus_free(bus); |
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return 0; |
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} |
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static struct platform_driver fsl_pq_mdio_driver = { |
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.driver = { |
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.name = "fsl-pq_mdio", |
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.of_match_table = fsl_pq_mdio_match, |
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}, |
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.probe = fsl_pq_mdio_probe, |
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.remove = fsl_pq_mdio_remove, |
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}; |
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module_platform_driver(fsl_pq_mdio_driver); |
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|
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MODULE_LICENSE("GPL");
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|
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