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181 lines
4.8 KiB
181 lines
4.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Reset controller portions for the U8500 PRCC |
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* Copyright (C) 2021 Linus Walleij <[email protected]> |
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*/ |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/types.h> |
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#include <linux/reset-controller.h> |
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#include <linux/bits.h> |
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#include <linux/delay.h> |
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#include "prcc.h" |
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#include "reset-prcc.h" |
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#define to_u8500_prcc_reset(p) container_of((p), struct u8500_prcc_reset, rcdev) |
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/* This macro flattens the 2-dimensional PRCC numberspace */ |
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#define PRCC_RESET_LINE(prcc_num, bit) \ |
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(((prcc_num) * PRCC_PERIPHS_PER_CLUSTER) + (bit)) |
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/* |
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* Reset registers in each PRCC - the reset lines are active low |
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* so what you need to do is write a bit for the peripheral you |
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* want to put into reset into the CLEAR register, this will assert |
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* the reset by pulling the line low. SET take the device out of |
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* reset. The status reflects the actual state of the line. |
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*/ |
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#define PRCC_K_SOFTRST_SET 0x018 |
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#define PRCC_K_SOFTRST_CLEAR 0x01c |
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#define PRCC_K_RST_STATUS 0x020 |
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static int prcc_num_to_index(unsigned int num) |
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{ |
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switch (num) { |
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case 1: |
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return CLKRST1_INDEX; |
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case 2: |
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return CLKRST2_INDEX; |
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case 3: |
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return CLKRST3_INDEX; |
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case 5: |
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return CLKRST5_INDEX; |
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case 6: |
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return CLKRST6_INDEX; |
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} |
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return -EINVAL; |
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} |
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static void __iomem *u8500_prcc_reset_base(struct u8500_prcc_reset *ur, |
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unsigned long id) |
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{ |
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unsigned int prcc_num, index; |
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prcc_num = id / PRCC_PERIPHS_PER_CLUSTER; |
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index = prcc_num_to_index(prcc_num); |
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if (index > ARRAY_SIZE(ur->base)) |
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return NULL; |
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return ur->base[index]; |
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} |
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static int u8500_prcc_reset(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
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void __iomem *base = u8500_prcc_reset_base(ur, id); |
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unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
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pr_debug("PRCC cycle reset id %lu, bit %u\n", id, bit); |
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/* |
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* Assert reset and then release it. The one microsecond |
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* delay is found in the vendor reference code. |
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*/ |
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writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR); |
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udelay(1); |
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writel(BIT(bit), base + PRCC_K_SOFTRST_SET); |
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udelay(1); |
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return 0; |
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} |
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static int u8500_prcc_reset_assert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
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void __iomem *base = u8500_prcc_reset_base(ur, id); |
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unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
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pr_debug("PRCC assert reset id %lu, bit %u\n", id, bit); |
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writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR); |
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return 0; |
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} |
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static int u8500_prcc_reset_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
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void __iomem *base = u8500_prcc_reset_base(ur, id); |
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unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
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pr_debug("PRCC deassert reset id %lu, bit %u\n", id, bit); |
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writel(BIT(bit), base + PRCC_K_SOFTRST_SET); |
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return 0; |
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} |
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static int u8500_prcc_reset_status(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
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void __iomem *base = u8500_prcc_reset_base(ur, id); |
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unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
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u32 val; |
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pr_debug("PRCC check status on reset line id %lu, bit %u\n", id, bit); |
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val = readl(base + PRCC_K_RST_STATUS); |
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/* Active low so return the inverse value of the bit */ |
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return !(val & BIT(bit)); |
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} |
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static const struct reset_control_ops u8500_prcc_reset_ops = { |
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.reset = u8500_prcc_reset, |
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.assert = u8500_prcc_reset_assert, |
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.deassert = u8500_prcc_reset_deassert, |
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.status = u8500_prcc_reset_status, |
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}; |
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static int u8500_prcc_reset_xlate(struct reset_controller_dev *rcdev, |
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const struct of_phandle_args *reset_spec) |
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{ |
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unsigned int prcc_num, bit; |
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if (reset_spec->args_count != 2) |
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return -EINVAL; |
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prcc_num = reset_spec->args[0]; |
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bit = reset_spec->args[1]; |
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if (prcc_num != 1 && prcc_num != 2 && prcc_num != 3 && |
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prcc_num != 5 && prcc_num != 6) { |
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pr_err("%s: invalid PRCC %d\n", __func__, prcc_num); |
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return -EINVAL; |
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} |
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pr_debug("located reset line %d at PRCC %d bit %d\n", |
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PRCC_RESET_LINE(prcc_num, bit), prcc_num, bit); |
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return PRCC_RESET_LINE(prcc_num, bit); |
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} |
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void u8500_prcc_reset_init(struct device_node *np, struct u8500_prcc_reset *ur) |
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{ |
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struct reset_controller_dev *rcdev = &ur->rcdev; |
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int ret; |
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int i; |
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for (i = 0; i < CLKRST_MAX; i++) { |
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ur->base[i] = ioremap(ur->phy_base[i], SZ_4K); |
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if (!ur->base[i]) |
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pr_err("PRCC failed to remap for reset base %d (%08x)\n", |
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i, ur->phy_base[i]); |
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} |
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rcdev->owner = THIS_MODULE; |
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rcdev->ops = &u8500_prcc_reset_ops; |
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rcdev->of_node = np; |
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rcdev->of_reset_n_cells = 2; |
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rcdev->of_xlate = u8500_prcc_reset_xlate; |
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ret = reset_controller_register(rcdev); |
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if (ret) |
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pr_err("PRCC failed to register reset controller\n"); |
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}
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