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371 lines
8.9 KiB
371 lines
8.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/clk/tegra.h> |
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#include <linux/device.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include "clk.h" |
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#define CLK_SOURCE_EMC 0x19c |
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#define CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29) |
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#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ BIT(16) |
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#define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0) |
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#define CLK_SRC_PLLM 0 |
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#define CLK_SRC_PLLC 1 |
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#define CLK_SRC_PLLP 2 |
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#define CLK_SRC_CLK_M 3 |
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#define CLK_SRC_PLLM_UD 4 |
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#define CLK_SRC_PLLMB_UD 5 |
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#define CLK_SRC_PLLMB 6 |
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#define CLK_SRC_PLLP_UD 7 |
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struct tegra210_clk_emc { |
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struct clk_hw hw; |
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void __iomem *regs; |
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struct tegra210_clk_emc_provider *provider; |
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struct clk *parents[8]; |
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}; |
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static inline struct tegra210_clk_emc * |
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to_tegra210_clk_emc(struct clk_hw *hw) |
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{ |
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return container_of(hw, struct tegra210_clk_emc, hw); |
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} |
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static const char *tegra210_clk_emc_parents[] = { |
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"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb_ud", |
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"pll_mb", "pll_p_ud", |
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}; |
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static u8 tegra210_clk_emc_get_parent(struct clk_hw *hw) |
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{ |
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struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); |
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u32 value; |
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u8 src; |
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value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); |
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src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, value); |
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return src; |
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} |
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static unsigned long tegra210_clk_emc_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); |
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u32 value, div; |
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/* |
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* CCF assumes that neither the parent nor its rate will change during |
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* ->set_rate(), so the parent rate passed in here was cached from the |
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* parent before the ->set_rate() call. |
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* |
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* This can lead to wrong results being reported for the EMC clock if |
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* the parent and/or parent rate have changed as part of the EMC rate |
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* change sequence. Fix this by overriding the parent clock with what |
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* we know to be the correct value after the rate change. |
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*/ |
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parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
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value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); |
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div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, value); |
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div += 2; |
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return DIV_ROUND_UP(parent_rate * 2, div); |
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} |
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static long tegra210_clk_emc_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); |
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struct tegra210_clk_emc_provider *provider = emc->provider; |
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unsigned int i; |
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if (!provider || !provider->configs || provider->num_configs == 0) |
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return clk_hw_get_rate(hw); |
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for (i = 0; i < provider->num_configs; i++) { |
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if (provider->configs[i].rate >= rate) |
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return provider->configs[i].rate; |
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} |
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return provider->configs[i - 1].rate; |
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} |
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static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, |
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u8 index) |
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{ |
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struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); |
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const char *name = clk_hw_get_name(parent); |
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/* XXX implement cache? */ |
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return __clk_lookup(name); |
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} |
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static int tegra210_clk_emc_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); |
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struct tegra210_clk_emc_provider *provider = emc->provider; |
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struct tegra210_clk_emc_config *config; |
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struct device *dev = provider->dev; |
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struct clk_hw *old, *new, *parent; |
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u8 old_idx, new_idx, index; |
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struct clk *clk; |
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unsigned int i; |
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int err; |
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if (!provider->configs || provider->num_configs == 0) |
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return -EINVAL; |
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for (i = 0; i < provider->num_configs; i++) { |
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if (provider->configs[i].rate >= rate) { |
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config = &provider->configs[i]; |
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break; |
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} |
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} |
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if (i == provider->num_configs) |
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config = &provider->configs[i - 1]; |
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old_idx = tegra210_clk_emc_get_parent(hw); |
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new_idx = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value); |
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old = clk_hw_get_parent_by_index(hw, old_idx); |
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new = clk_hw_get_parent_by_index(hw, new_idx); |
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/* if the rate has changed... */ |
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if (config->parent_rate != clk_hw_get_rate(old)) { |
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/* ... but the clock source remains the same ... */ |
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if (new_idx == old_idx) { |
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/* ... switch to the alternative clock source. */ |
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switch (new_idx) { |
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case CLK_SRC_PLLM: |
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new_idx = CLK_SRC_PLLMB; |
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break; |
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case CLK_SRC_PLLM_UD: |
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new_idx = CLK_SRC_PLLMB_UD; |
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break; |
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case CLK_SRC_PLLMB_UD: |
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new_idx = CLK_SRC_PLLM_UD; |
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break; |
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case CLK_SRC_PLLMB: |
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new_idx = CLK_SRC_PLLM; |
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break; |
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} |
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/* |
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* This should never happen because we can't deal with |
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* it. |
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*/ |
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if (WARN_ON(new_idx == old_idx)) |
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return -EINVAL; |
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new = clk_hw_get_parent_by_index(hw, new_idx); |
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} |
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index = new_idx; |
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parent = new; |
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} else { |
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index = old_idx; |
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parent = old; |
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} |
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clk = tegra210_clk_emc_find_parent(emc, index); |
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if (IS_ERR(clk)) { |
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err = PTR_ERR(clk); |
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dev_err(dev, "failed to get parent clock for index %u: %d\n", |
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index, err); |
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return err; |
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} |
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/* set the new parent clock to the required rate */ |
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if (clk_get_rate(clk) != config->parent_rate) { |
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err = clk_set_rate(clk, config->parent_rate); |
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if (err < 0) { |
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dev_err(dev, "failed to set rate %lu Hz for %pC: %d\n", |
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config->parent_rate, clk, err); |
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return err; |
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} |
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} |
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/* enable the new parent clock */ |
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if (parent != old) { |
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err = clk_prepare_enable(clk); |
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if (err < 0) { |
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dev_err(dev, "failed to enable parent clock %pC: %d\n", |
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clk, err); |
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return err; |
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} |
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} |
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/* update the EMC source configuration to reflect the new parent */ |
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config->value &= ~CLK_SOURCE_EMC_2X_CLK_SRC; |
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config->value |= FIELD_PREP(CLK_SOURCE_EMC_2X_CLK_SRC, index); |
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/* |
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* Finally, switch the EMC programming with both old and new parent |
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* clocks enabled. |
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*/ |
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err = provider->set_rate(dev, config); |
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if (err < 0) { |
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dev_err(dev, "failed to set EMC rate to %lu Hz: %d\n", rate, |
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err); |
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/* |
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* If we're unable to switch to the new EMC frequency, we no |
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* longer need the new parent to be enabled. |
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*/ |
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if (parent != old) |
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clk_disable_unprepare(clk); |
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return err; |
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} |
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/* reparent to new parent clock and disable the old parent clock */ |
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if (parent != old) { |
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clk = tegra210_clk_emc_find_parent(emc, old_idx); |
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if (IS_ERR(clk)) { |
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err = PTR_ERR(clk); |
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dev_err(dev, |
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"failed to get parent clock for index %u: %d\n", |
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old_idx, err); |
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return err; |
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} |
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clk_hw_reparent(hw, parent); |
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clk_disable_unprepare(clk); |
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} |
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return err; |
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} |
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static const struct clk_ops tegra210_clk_emc_ops = { |
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.get_parent = tegra210_clk_emc_get_parent, |
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.recalc_rate = tegra210_clk_emc_recalc_rate, |
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.round_rate = tegra210_clk_emc_round_rate, |
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.set_rate = tegra210_clk_emc_set_rate, |
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}; |
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struct clk *tegra210_clk_register_emc(struct device_node *np, |
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void __iomem *regs) |
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{ |
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struct tegra210_clk_emc *emc; |
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struct clk_init_data init; |
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struct clk *clk; |
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emc = kzalloc(sizeof(*emc), GFP_KERNEL); |
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if (!emc) |
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return ERR_PTR(-ENOMEM); |
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emc->regs = regs; |
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init.name = "emc"; |
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init.ops = &tegra210_clk_emc_ops; |
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init.flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE; |
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init.parent_names = tegra210_clk_emc_parents; |
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init.num_parents = ARRAY_SIZE(tegra210_clk_emc_parents); |
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emc->hw.init = &init; |
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clk = clk_register(NULL, &emc->hw); |
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if (IS_ERR(clk)) { |
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kfree(emc); |
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return clk; |
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} |
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return clk; |
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} |
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int tegra210_clk_emc_attach(struct clk *clk, |
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struct tegra210_clk_emc_provider *provider) |
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{ |
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struct clk_hw *hw = __clk_get_hw(clk); |
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struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); |
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struct device *dev = provider->dev; |
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unsigned int i; |
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int err; |
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if (!try_module_get(provider->owner)) |
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return -ENODEV; |
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for (i = 0; i < provider->num_configs; i++) { |
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struct tegra210_clk_emc_config *config = &provider->configs[i]; |
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struct clk_hw *parent; |
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bool same_freq; |
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u8 div, src; |
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div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, config->value); |
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src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value); |
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/* do basic sanity checking on the EMC timings */ |
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if (div & 0x1) { |
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dev_err(dev, "invalid odd divider %u for rate %lu Hz\n", |
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div, config->rate); |
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err = -EINVAL; |
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goto put; |
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} |
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same_freq = config->value & CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; |
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if (same_freq != config->same_freq) { |
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dev_err(dev, |
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"ambiguous EMC to MC ratio for rate %lu Hz\n", |
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config->rate); |
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err = -EINVAL; |
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goto put; |
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} |
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parent = clk_hw_get_parent_by_index(hw, src); |
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config->parent = src; |
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if (src == CLK_SRC_PLLM || src == CLK_SRC_PLLM_UD) { |
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config->parent_rate = config->rate * (1 + div / 2); |
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} else { |
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unsigned long rate = config->rate * (1 + div / 2); |
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config->parent_rate = clk_hw_get_rate(parent); |
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if (config->parent_rate != rate) { |
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dev_err(dev, |
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"rate %lu Hz does not match input\n", |
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config->rate); |
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err = -EINVAL; |
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goto put; |
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} |
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} |
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} |
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emc->provider = provider; |
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return 0; |
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put: |
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module_put(provider->owner); |
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return err; |
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} |
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EXPORT_SYMBOL_GPL(tegra210_clk_emc_attach); |
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void tegra210_clk_emc_detach(struct clk *clk) |
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{ |
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struct tegra210_clk_emc *emc = to_tegra210_clk_emc(__clk_get_hw(clk)); |
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module_put(emc->provider->owner); |
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emc->provider = NULL; |
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} |
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EXPORT_SYMBOL_GPL(tegra210_clk_emc_detach);
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