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573 lines
14 KiB
573 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* drivers/clk/tegra/clk-emc.c |
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* |
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. |
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* |
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* Author: |
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* Mikko Perttunen <[email protected]> |
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*/ |
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|
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#include <linux/clk-provider.h> |
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#include <linux/clk.h> |
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#include <linux/clkdev.h> |
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#include <linux/clk/tegra.h> |
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#include <linux/delay.h> |
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#include <linux/export.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/sort.h> |
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#include <linux/string.h> |
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#include <soc/tegra/fuse.h> |
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#include "clk.h" |
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#define CLK_SOURCE_EMC 0x19c |
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#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0 |
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#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff |
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#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \ |
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CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT) |
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#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29 |
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#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7 |
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#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \ |
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CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) |
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static const char * const emc_parent_clk_names[] = { |
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"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", |
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"pll_c2", "pll_c3", "pll_c_ud" |
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}; |
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/* |
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* List of clock sources for various parents the EMC clock can have. |
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* When we change the timing to a timing with a parent that has the same |
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* clock source as the current parent, we must first change to a backup |
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* timing that has a different clock source. |
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*/ |
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#define EMC_SRC_PLL_M 0 |
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#define EMC_SRC_PLL_C 1 |
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#define EMC_SRC_PLL_P 2 |
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#define EMC_SRC_CLK_M 3 |
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#define EMC_SRC_PLL_C2 4 |
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#define EMC_SRC_PLL_C3 5 |
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static const char emc_parent_clk_sources[] = { |
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EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M, |
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EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C |
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}; |
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struct emc_timing { |
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unsigned long rate, parent_rate; |
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u8 parent_index; |
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struct clk *parent; |
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u32 ram_code; |
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}; |
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struct tegra_clk_emc { |
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struct clk_hw hw; |
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void __iomem *clk_regs; |
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struct clk *prev_parent; |
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bool changing_timing; |
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struct device_node *emc_node; |
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struct tegra_emc *emc; |
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int num_timings; |
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struct emc_timing *timings; |
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spinlock_t *lock; |
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tegra124_emc_prepare_timing_change_cb *prepare_timing_change; |
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tegra124_emc_complete_timing_change_cb *complete_timing_change; |
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}; |
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/* Common clock framework callback implementations */ |
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static unsigned long emc_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct tegra_clk_emc *tegra; |
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u32 val, div; |
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tegra = container_of(hw, struct tegra_clk_emc, hw); |
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/* |
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* CCF wrongly assumes that the parent won't change during set_rate, |
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* so get the parent rate explicitly. |
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*/ |
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parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
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val = readl(tegra->clk_regs + CLK_SOURCE_EMC); |
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div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK; |
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return parent_rate / (div + 2) * 2; |
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} |
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/* |
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* Rounds up unless no higher rate exists, in which case down. This way is |
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* safer since things have EMC rate floors. Also don't touch parent_rate |
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* since we don't want the CCF to play with our parent clocks. |
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*/ |
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static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) |
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{ |
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struct tegra_clk_emc *tegra; |
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u8 ram_code = tegra_read_ram_code(); |
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struct emc_timing *timing = NULL; |
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int i, k, t; |
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tegra = container_of(hw, struct tegra_clk_emc, hw); |
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for (k = 0; k < tegra->num_timings; k++) { |
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if (tegra->timings[k].ram_code == ram_code) |
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break; |
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} |
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for (t = k; t < tegra->num_timings; t++) { |
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if (tegra->timings[t].ram_code != ram_code) |
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break; |
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} |
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for (i = k; i < t; i++) { |
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timing = tegra->timings + i; |
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if (timing->rate < req->rate && i != t - 1) |
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continue; |
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if (timing->rate > req->max_rate) { |
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i = max(i, k + 1); |
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req->rate = tegra->timings[i - 1].rate; |
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return 0; |
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} |
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if (timing->rate < req->min_rate) |
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continue; |
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req->rate = timing->rate; |
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return 0; |
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} |
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if (timing) { |
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req->rate = timing->rate; |
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return 0; |
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} |
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req->rate = clk_hw_get_rate(hw); |
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return 0; |
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} |
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static u8 emc_get_parent(struct clk_hw *hw) |
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{ |
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struct tegra_clk_emc *tegra; |
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u32 val; |
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tegra = container_of(hw, struct tegra_clk_emc, hw); |
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val = readl(tegra->clk_regs + CLK_SOURCE_EMC); |
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return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) |
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& CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK; |
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} |
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static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) |
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{ |
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struct platform_device *pdev; |
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if (tegra->emc) |
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return tegra->emc; |
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if (!tegra->prepare_timing_change || !tegra->complete_timing_change) |
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return NULL; |
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if (!tegra->emc_node) |
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return NULL; |
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pdev = of_find_device_by_node(tegra->emc_node); |
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if (!pdev) { |
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pr_err("%s: could not get external memory controller\n", |
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__func__); |
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return NULL; |
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} |
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of_node_put(tegra->emc_node); |
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tegra->emc_node = NULL; |
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tegra->emc = platform_get_drvdata(pdev); |
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if (!tegra->emc) { |
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pr_err("%s: cannot find EMC driver\n", __func__); |
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return NULL; |
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} |
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return tegra->emc; |
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} |
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static int emc_set_timing(struct tegra_clk_emc *tegra, |
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struct emc_timing *timing) |
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{ |
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int err; |
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u8 div; |
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u32 car_value; |
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unsigned long flags = 0; |
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struct tegra_emc *emc = emc_ensure_emc_driver(tegra); |
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if (!emc) |
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return -ENOENT; |
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pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, |
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timing->parent_rate, __clk_get_name(timing->parent)); |
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if (emc_get_parent(&tegra->hw) == timing->parent_index && |
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clk_get_rate(timing->parent) != timing->parent_rate) { |
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WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n", |
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__clk_get_name(timing->parent), |
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clk_get_rate(timing->parent), |
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timing->parent_rate); |
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return -EINVAL; |
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} |
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tegra->changing_timing = true; |
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err = clk_set_rate(timing->parent, timing->parent_rate); |
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if (err) { |
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pr_err("cannot change parent %s rate to %ld: %d\n", |
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__clk_get_name(timing->parent), timing->parent_rate, |
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err); |
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return err; |
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} |
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err = clk_prepare_enable(timing->parent); |
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if (err) { |
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pr_err("cannot enable parent clock: %d\n", err); |
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return err; |
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} |
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div = timing->parent_rate / (timing->rate / 2) - 2; |
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err = tegra->prepare_timing_change(emc, timing->rate); |
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if (err) { |
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clk_disable_unprepare(timing->parent); |
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return err; |
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} |
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spin_lock_irqsave(tegra->lock, flags); |
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car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); |
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car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0); |
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car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index); |
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car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0); |
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car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div); |
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writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); |
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spin_unlock_irqrestore(tegra->lock, flags); |
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tegra->complete_timing_change(emc, timing->rate); |
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clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); |
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clk_disable_unprepare(tegra->prev_parent); |
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tegra->prev_parent = timing->parent; |
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tegra->changing_timing = false; |
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return 0; |
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} |
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/* |
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* Get backup timing to use as an intermediate step when a change between |
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* two timings with the same clock source has been requested. First try to |
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* find a timing with a higher clock rate to avoid a rate below any set rate |
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* floors. If that is not possible, find a lower rate. |
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*/ |
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static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra, |
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int timing_index) |
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{ |
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int i; |
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u32 ram_code = tegra_read_ram_code(); |
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struct emc_timing *timing; |
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for (i = timing_index+1; i < tegra->num_timings; i++) { |
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timing = tegra->timings + i; |
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if (timing->ram_code != ram_code) |
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break; |
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if (emc_parent_clk_sources[timing->parent_index] != |
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emc_parent_clk_sources[ |
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tegra->timings[timing_index].parent_index]) |
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return timing; |
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} |
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for (i = timing_index-1; i >= 0; --i) { |
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timing = tegra->timings + i; |
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if (timing->ram_code != ram_code) |
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break; |
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if (emc_parent_clk_sources[timing->parent_index] != |
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emc_parent_clk_sources[ |
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tegra->timings[timing_index].parent_index]) |
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return timing; |
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} |
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return NULL; |
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} |
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static int emc_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct tegra_clk_emc *tegra; |
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struct emc_timing *timing = NULL; |
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int i, err; |
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u32 ram_code = tegra_read_ram_code(); |
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tegra = container_of(hw, struct tegra_clk_emc, hw); |
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if (clk_hw_get_rate(hw) == rate) |
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return 0; |
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/* |
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* When emc_set_timing changes the parent rate, CCF will propagate |
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* that downward to us, so ignore any set_rate calls while a rate |
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* change is already going on. |
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*/ |
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if (tegra->changing_timing) |
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return 0; |
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for (i = 0; i < tegra->num_timings; i++) { |
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if (tegra->timings[i].rate == rate && |
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tegra->timings[i].ram_code == ram_code) { |
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timing = tegra->timings + i; |
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break; |
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} |
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} |
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if (!timing) { |
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pr_err("cannot switch to rate %ld without emc table\n", rate); |
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return -EINVAL; |
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} |
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if (emc_parent_clk_sources[emc_get_parent(hw)] == |
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emc_parent_clk_sources[timing->parent_index] && |
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clk_get_rate(timing->parent) != timing->parent_rate) { |
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/* |
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* Parent clock source not changed but parent rate has changed, |
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* need to temporarily switch to another parent |
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*/ |
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struct emc_timing *backup_timing; |
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backup_timing = get_backup_timing(tegra, i); |
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if (!backup_timing) { |
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pr_err("cannot find backup timing\n"); |
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return -EINVAL; |
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} |
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pr_debug("using %ld as backup rate when going to %ld\n", |
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backup_timing->rate, rate); |
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err = emc_set_timing(tegra, backup_timing); |
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if (err) { |
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pr_err("cannot set backup timing: %d\n", err); |
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return err; |
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} |
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} |
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return emc_set_timing(tegra, timing); |
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} |
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/* Initialization and deinitialization */ |
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static int load_one_timing_from_dt(struct tegra_clk_emc *tegra, |
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struct emc_timing *timing, |
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struct device_node *node) |
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{ |
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int err, i; |
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u32 tmp; |
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err = of_property_read_u32(node, "clock-frequency", &tmp); |
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if (err) { |
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pr_err("timing %pOF: failed to read rate\n", node); |
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return err; |
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} |
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timing->rate = tmp; |
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err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp); |
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if (err) { |
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pr_err("timing %pOF: failed to read parent rate\n", node); |
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return err; |
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} |
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timing->parent_rate = tmp; |
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timing->parent = of_clk_get_by_name(node, "emc-parent"); |
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if (IS_ERR(timing->parent)) { |
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pr_err("timing %pOF: failed to get parent clock\n", node); |
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return PTR_ERR(timing->parent); |
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} |
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timing->parent_index = 0xff; |
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i = match_string(emc_parent_clk_names, ARRAY_SIZE(emc_parent_clk_names), |
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__clk_get_name(timing->parent)); |
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if (i < 0) { |
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pr_err("timing %pOF: %s is not a valid parent\n", |
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node, __clk_get_name(timing->parent)); |
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clk_put(timing->parent); |
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return -EINVAL; |
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} |
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timing->parent_index = i; |
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return 0; |
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} |
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static int cmp_timings(const void *_a, const void *_b) |
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{ |
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const struct emc_timing *a = _a; |
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const struct emc_timing *b = _b; |
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if (a->rate < b->rate) |
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return -1; |
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else if (a->rate == b->rate) |
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return 0; |
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else |
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return 1; |
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} |
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static int load_timings_from_dt(struct tegra_clk_emc *tegra, |
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struct device_node *node, |
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u32 ram_code) |
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{ |
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struct emc_timing *timings_ptr; |
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struct device_node *child; |
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int child_count = of_get_child_count(node); |
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int i = 0, err; |
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size_t size; |
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size = (tegra->num_timings + child_count) * sizeof(struct emc_timing); |
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tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL); |
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if (!tegra->timings) |
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return -ENOMEM; |
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timings_ptr = tegra->timings + tegra->num_timings; |
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tegra->num_timings += child_count; |
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for_each_child_of_node(node, child) { |
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struct emc_timing *timing = timings_ptr + (i++); |
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err = load_one_timing_from_dt(tegra, timing, child); |
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if (err) { |
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of_node_put(child); |
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return err; |
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} |
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timing->ram_code = ram_code; |
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} |
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sort(timings_ptr, child_count, sizeof(struct emc_timing), |
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cmp_timings, NULL); |
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return 0; |
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} |
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static const struct clk_ops tegra_clk_emc_ops = { |
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.recalc_rate = emc_recalc_rate, |
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.determine_rate = emc_determine_rate, |
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.set_rate = emc_set_rate, |
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.get_parent = emc_get_parent, |
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}; |
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struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, |
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spinlock_t *lock) |
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{ |
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struct tegra_clk_emc *tegra; |
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struct clk_init_data init; |
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struct device_node *node; |
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u32 node_ram_code; |
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struct clk *clk; |
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int err; |
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tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL); |
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if (!tegra) |
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return ERR_PTR(-ENOMEM); |
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tegra->clk_regs = base; |
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tegra->lock = lock; |
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tegra->num_timings = 0; |
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for_each_child_of_node(np, node) { |
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err = of_property_read_u32(node, "nvidia,ram-code", |
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&node_ram_code); |
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if (err) |
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continue; |
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/* |
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* Store timings for all ram codes as we cannot read the |
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* fuses until the apbmisc driver is loaded. |
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*/ |
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err = load_timings_from_dt(tegra, node, node_ram_code); |
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if (err) { |
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of_node_put(node); |
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return ERR_PTR(err); |
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} |
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} |
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if (tegra->num_timings == 0) |
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pr_warn("%s: no memory timings registered\n", __func__); |
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tegra->emc_node = of_parse_phandle(np, |
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"nvidia,external-memory-controller", 0); |
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if (!tegra->emc_node) |
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pr_warn("%s: couldn't find node for EMC driver\n", __func__); |
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init.name = "emc"; |
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init.ops = &tegra_clk_emc_ops; |
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init.flags = CLK_IS_CRITICAL; |
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init.parent_names = emc_parent_clk_names; |
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init.num_parents = ARRAY_SIZE(emc_parent_clk_names); |
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tegra->hw.init = &init; |
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clk = clk_register(NULL, &tegra->hw); |
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if (IS_ERR(clk)) |
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return clk; |
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tegra->prev_parent = clk_hw_get_parent_by_index( |
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&tegra->hw, emc_get_parent(&tegra->hw))->clk; |
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tegra->changing_timing = false; |
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|
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/* Allow debugging tools to see the EMC clock */ |
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clk_register_clkdev(clk, "emc", "tegra-clk-debug"); |
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return clk; |
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}; |
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void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, |
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tegra124_emc_complete_timing_change_cb *complete_cb) |
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{ |
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struct clk *clk = __clk_lookup("emc"); |
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struct tegra_clk_emc *tegra; |
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struct clk_hw *hw; |
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|
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if (clk) { |
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hw = __clk_get_hw(clk); |
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tegra = container_of(hw, struct tegra_clk_emc, hw); |
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|
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tegra->prepare_timing_change = prep_cb; |
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tegra->complete_timing_change = complete_cb; |
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} |
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} |
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EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks); |
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bool tegra124_clk_emc_driver_available(struct clk_hw *hw) |
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{ |
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struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw); |
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|
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return tegra->prepare_timing_change && tegra->complete_timing_change; |
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}
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