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355 lines
8.5 KiB
355 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/qcom,videocc-sdm845.h> |
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#include "common.h" |
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#include "clk-alpha-pll.h" |
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#include "clk-branch.h" |
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#include "clk-rcg.h" |
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#include "clk-regmap.h" |
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#include "clk-pll.h" |
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#include "gdsc.h" |
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enum { |
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P_BI_TCXO, |
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P_VIDEO_PLL0_OUT_MAIN, |
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/* P_VIDEO_PLL0_OUT_EVEN, */ |
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/* P_VIDEO_PLL0_OUT_ODD, */ |
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}; |
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static const struct alpha_pll_config video_pll0_config = { |
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.l = 0x10, |
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.alpha = 0xaaab, |
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}; |
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static struct clk_alpha_pll video_pll0 = { |
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.offset = 0x42c, |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
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.clkr = { |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_pll0", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", .name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_fabia_ops, |
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}, |
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}, |
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}; |
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static const struct parent_map video_cc_parent_map_0[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_VIDEO_PLL0_OUT_MAIN, 1 }, |
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/* { P_VIDEO_PLL0_OUT_EVEN, 2 }, */ |
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/* { P_VIDEO_PLL0_OUT_ODD, 3 }, */ |
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}; |
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static const struct clk_parent_data video_cc_parent_data_0[] = { |
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" }, |
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{ .hw = &video_pll0.clkr.hw }, |
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/* { .name = "video_pll0_out_even" }, */ |
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/* { .name = "video_pll0_out_odd" }, */ |
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}; |
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static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { |
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F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0), |
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F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), |
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F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 video_cc_venus_clk_src = { |
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.cmd_rcgr = 0x7f0, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = video_cc_parent_map_0, |
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.freq_tbl = ftbl_video_cc_venus_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_venus_clk_src", |
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.parent_data = video_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_shared_ops, |
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}, |
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}; |
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static struct clk_branch video_cc_apb_clk = { |
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.halt_reg = 0x990, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x990, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_apb_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_at_clk = { |
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.halt_reg = 0x9f0, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x9f0, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_at_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_qdss_trig_clk = { |
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.halt_reg = 0x970, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x970, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_qdss_trig_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_qdss_tsctr_div8_clk = { |
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.halt_reg = 0x9d0, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x9d0, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_qdss_tsctr_div8_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_vcodec0_axi_clk = { |
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.halt_reg = 0x930, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x930, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_vcodec0_axi_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_vcodec0_core_clk = { |
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.halt_reg = 0x890, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x890, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_vcodec0_core_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_venus_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_vcodec1_axi_clk = { |
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.halt_reg = 0x950, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x950, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_vcodec1_axi_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_vcodec1_core_clk = { |
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.halt_reg = 0x8d0, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x8d0, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_vcodec1_core_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_venus_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_venus_ahb_clk = { |
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.halt_reg = 0x9b0, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x9b0, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_venus_ahb_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_venus_ctl_axi_clk = { |
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.halt_reg = 0x910, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x910, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_venus_ctl_axi_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_venus_ctl_core_clk = { |
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.halt_reg = 0x850, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x850, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_venus_ctl_core_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_venus_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct gdsc venus_gdsc = { |
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.gdscr = 0x814, |
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.pd = { |
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.name = "venus_gdsc", |
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}, |
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.cxcs = (unsigned int []){ 0x850, 0x910 }, |
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.cxc_count = 2, |
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.pwrsts = PWRSTS_OFF_ON, |
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.flags = POLL_CFG_GDSCR, |
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}; |
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static struct gdsc vcodec0_gdsc = { |
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.gdscr = 0x874, |
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.pd = { |
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.name = "vcodec0_gdsc", |
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}, |
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.cxcs = (unsigned int []){ 0x890, 0x930 }, |
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.cxc_count = 2, |
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.flags = HW_CTRL | POLL_CFG_GDSCR, |
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.pwrsts = PWRSTS_OFF_ON, |
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}; |
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static struct gdsc vcodec1_gdsc = { |
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.gdscr = 0x8b4, |
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.pd = { |
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.name = "vcodec1_gdsc", |
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}, |
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.cxcs = (unsigned int []){ 0x8d0, 0x950 }, |
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.cxc_count = 2, |
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.flags = HW_CTRL | POLL_CFG_GDSCR, |
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.pwrsts = PWRSTS_OFF_ON, |
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}; |
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static struct clk_regmap *video_cc_sdm845_clocks[] = { |
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[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr, |
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[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr, |
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[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr, |
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[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr, |
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[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, |
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[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, |
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[VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr, |
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[VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr, |
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[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, |
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[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, |
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[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, |
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[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, |
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[VIDEO_PLL0] = &video_pll0.clkr, |
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}; |
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static struct gdsc *video_cc_sdm845_gdscs[] = { |
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[VENUS_GDSC] = &venus_gdsc, |
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[VCODEC0_GDSC] = &vcodec0_gdsc, |
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[VCODEC1_GDSC] = &vcodec1_gdsc, |
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}; |
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static const struct regmap_config video_cc_sdm845_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = 0xb90, |
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.fast_io = true, |
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}; |
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static const struct qcom_cc_desc video_cc_sdm845_desc = { |
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.config = &video_cc_sdm845_regmap_config, |
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.clks = video_cc_sdm845_clocks, |
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.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks), |
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.gdscs = video_cc_sdm845_gdscs, |
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.num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs), |
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}; |
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static const struct of_device_id video_cc_sdm845_match_table[] = { |
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{ .compatible = "qcom,sdm845-videocc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table); |
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static int video_cc_sdm845_probe(struct platform_device *pdev) |
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{ |
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struct regmap *regmap; |
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regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); |
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return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap); |
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} |
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static struct platform_driver video_cc_sdm845_driver = { |
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.probe = video_cc_sdm845_probe, |
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.driver = { |
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.name = "sdm845-videocc", |
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.of_match_table = video_cc_sdm845_match_table, |
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}, |
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}; |
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static int __init video_cc_sdm845_init(void) |
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{ |
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return platform_driver_register(&video_cc_sdm845_driver); |
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} |
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subsys_initcall(video_cc_sdm845_init); |
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static void __exit video_cc_sdm845_exit(void) |
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{ |
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platform_driver_unregister(&video_cc_sdm845_driver); |
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} |
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module_exit(video_cc_sdm845_exit); |
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MODULE_LICENSE("GPL v2");
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