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325 lines
7.8 KiB
325 lines
7.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2021, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/qcom,videocc-sc7280.h> |
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#include "clk-alpha-pll.h" |
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#include "clk-branch.h" |
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#include "clk-rcg.h" |
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#include "common.h" |
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#include "reset.h" |
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#include "gdsc.h" |
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enum { |
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P_BI_TCXO, |
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P_SLEEP_CLK, |
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P_VIDEO_PLL0_OUT_EVEN, |
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}; |
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static const struct pll_vco lucid_vco[] = { |
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{ 249600000, 2000000000, 0 }, |
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}; |
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/* 400MHz Configuration */ |
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static const struct alpha_pll_config video_pll0_config = { |
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.l = 0x14, |
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.alpha = 0xD555, |
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.config_ctl_val = 0x20485699, |
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.config_ctl_hi_val = 0x00002261, |
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.config_ctl_hi1_val = 0x329A299C, |
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.user_ctl_val = 0x00000001, |
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.user_ctl_hi_val = 0x00000805, |
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.user_ctl_hi1_val = 0x00000000, |
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}; |
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static struct clk_alpha_pll video_pll0 = { |
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.offset = 0x0, |
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.vco_table = lucid_vco, |
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.num_vco = ARRAY_SIZE(lucid_vco), |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
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.clkr = { |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_pll0", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_lucid_ops, |
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}, |
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}, |
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}; |
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static const struct parent_map video_cc_parent_map_0[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_VIDEO_PLL0_OUT_EVEN, 3 }, |
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}; |
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static const struct clk_parent_data video_cc_parent_data_0[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &video_pll0.clkr.hw }, |
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}; |
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static const struct parent_map video_cc_parent_map_1[] = { |
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{ P_SLEEP_CLK, 0 }, |
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}; |
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static const struct clk_parent_data video_cc_parent_data_1[] = { |
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{ .fw_name = "sleep_clk" }, |
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}; |
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static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = { |
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F(133333333, P_VIDEO_PLL0_OUT_EVEN, 3, 0, 0), |
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F(240000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0), |
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F(335000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0), |
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F(424000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0), |
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F(460000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 video_cc_iris_clk_src = { |
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.cmd_rcgr = 0x1000, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = video_cc_parent_map_0, |
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.freq_tbl = ftbl_video_cc_iris_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_iris_clk_src", |
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.parent_data = video_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_shared_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { |
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F(32000, P_SLEEP_CLK, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 video_cc_sleep_clk_src = { |
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.cmd_rcgr = 0x701c, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = video_cc_parent_map_1, |
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.freq_tbl = ftbl_video_cc_sleep_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_sleep_clk_src", |
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.parent_data = video_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(video_cc_parent_data_1), |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_branch video_cc_iris_ahb_clk = { |
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.halt_reg = 0x5004, |
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.halt_check = BRANCH_HALT_VOTED, |
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.clkr = { |
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.enable_reg = 0x5004, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_iris_ahb_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_iris_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvs0_axi_clk = { |
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.halt_reg = 0x800c, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x800c, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs0_axi_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvs0_core_clk = { |
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.halt_reg = 0x3010, |
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.halt_check = BRANCH_HALT_VOTED, |
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.hwcg_reg = 0x3010, |
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.hwcg_bit = 1, |
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.clkr = { |
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.enable_reg = 0x3010, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs0_core_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_iris_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvsc_core_clk = { |
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.halt_reg = 0x2014, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x2014, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvsc_core_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_iris_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvsc_ctl_axi_clk = { |
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.halt_reg = 0x8004, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x8004, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvsc_ctl_axi_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_sleep_clk = { |
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.halt_reg = 0x7034, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x7034, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_sleep_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_sleep_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_venus_ahb_clk = { |
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.halt_reg = 0x801c, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x801c, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_venus_ahb_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct gdsc mvs0_gdsc = { |
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.gdscr = 0x3004, |
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.pd = { |
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.name = "mvs0_gdsc", |
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}, |
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.pwrsts = PWRSTS_OFF_ON, |
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.flags = HW_CTRL | RETAIN_FF_ENABLE, |
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}; |
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static struct gdsc mvsc_gdsc = { |
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.gdscr = 0x2004, |
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.pd = { |
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.name = "mvsc_gdsc", |
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}, |
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.flags = RETAIN_FF_ENABLE, |
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.pwrsts = PWRSTS_OFF_ON, |
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}; |
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static struct clk_regmap *video_cc_sc7280_clocks[] = { |
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[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr, |
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[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr, |
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[VIDEO_CC_MVS0_AXI_CLK] = &video_cc_mvs0_axi_clk.clkr, |
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[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr, |
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[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr, |
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[VIDEO_CC_MVSC_CTL_AXI_CLK] = &video_cc_mvsc_ctl_axi_clk.clkr, |
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[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr, |
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[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, |
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[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, |
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[VIDEO_PLL0] = &video_pll0.clkr, |
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}; |
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static struct gdsc *video_cc_sc7280_gdscs[] = { |
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[MVS0_GDSC] = &mvs0_gdsc, |
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[MVSC_GDSC] = &mvsc_gdsc, |
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}; |
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static const struct regmap_config video_cc_sc7280_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = 0xb000, |
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.fast_io = true, |
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}; |
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static const struct qcom_cc_desc video_cc_sc7280_desc = { |
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.config = &video_cc_sc7280_regmap_config, |
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.clks = video_cc_sc7280_clocks, |
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.num_clks = ARRAY_SIZE(video_cc_sc7280_clocks), |
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.gdscs = video_cc_sc7280_gdscs, |
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.num_gdscs = ARRAY_SIZE(video_cc_sc7280_gdscs), |
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}; |
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static const struct of_device_id video_cc_sc7280_match_table[] = { |
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{ .compatible = "qcom,sc7280-videocc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, video_cc_sc7280_match_table); |
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static int video_cc_sc7280_probe(struct platform_device *pdev) |
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{ |
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struct regmap *regmap; |
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regmap = qcom_cc_map(pdev, &video_cc_sc7280_desc); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); |
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return qcom_cc_really_probe(pdev, &video_cc_sc7280_desc, regmap); |
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} |
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static struct platform_driver video_cc_sc7280_driver = { |
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.probe = video_cc_sc7280_probe, |
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.driver = { |
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.name = "video_cc-sc7280", |
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.of_match_table = video_cc_sc7280_match_table, |
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}, |
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}; |
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static int __init video_cc_sc7280_init(void) |
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{ |
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return platform_driver_register(&video_cc_sc7280_driver); |
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} |
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subsys_initcall(video_cc_sc7280_init); |
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static void __exit video_cc_sc7280_exit(void) |
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{ |
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platform_driver_unregister(&video_cc_sc7280_driver); |
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} |
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module_exit(video_cc_sc7280_exit); |
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MODULE_DESCRIPTION("QTI VIDEO_CC sc7280 Driver"); |
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MODULE_LICENSE("GPL v2");
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