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156 lines
3.5 KiB
156 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2019, Linaro Ltd. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/err.h> |
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#include <linux/platform_device.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/pm_clock.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/qcom,turingcc-qcs404.h> |
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#include "clk-regmap.h" |
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#include "clk-branch.h" |
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#include "common.h" |
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#include "reset.h" |
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static struct clk_branch turing_wrapper_aon_cbcr = { |
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.halt_reg = 0x5098, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x5098, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data) { |
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.name = "turing_wrapper_aon_clk", |
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.ops = &clk_branch2_aon_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch turing_q6ss_ahbm_aon_cbcr = { |
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.halt_reg = 0x9000, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x9000, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data) { |
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.name = "turing_q6ss_ahbm_aon_cbcr", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch turing_q6ss_q6_axim_clk = { |
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.halt_reg = 0xb000, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0xb000, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data) { |
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.name = "turing_q6ss_q6_axim_clk", |
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.ops = &clk_branch2_aon_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch turing_q6ss_ahbs_aon_cbcr = { |
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.halt_reg = 0x10000, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x10000, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data) { |
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.name = "turing_q6ss_ahbs_aon_clk", |
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.ops = &clk_branch2_aon_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch turing_wrapper_qos_ahbs_aon_cbcr = { |
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.halt_reg = 0x11014, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x11014, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data) { |
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.name = "turing_wrapper_qos_ahbs_aon_clk", |
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.ops = &clk_branch2_aon_ops, |
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}, |
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}, |
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}; |
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static struct clk_regmap *turingcc_clocks[] = { |
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[TURING_WRAPPER_AON_CLK] = &turing_wrapper_aon_cbcr.clkr, |
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[TURING_Q6SS_AHBM_AON_CLK] = &turing_q6ss_ahbm_aon_cbcr.clkr, |
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[TURING_Q6SS_Q6_AXIM_CLK] = &turing_q6ss_q6_axim_clk.clkr, |
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[TURING_Q6SS_AHBS_AON_CLK] = &turing_q6ss_ahbs_aon_cbcr.clkr, |
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[TURING_WRAPPER_QOS_AHBS_AON_CLK] = &turing_wrapper_qos_ahbs_aon_cbcr.clkr, |
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}; |
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static const struct regmap_config turingcc_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = 0x23004, |
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.fast_io = true, |
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}; |
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static const struct qcom_cc_desc turingcc_desc = { |
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.config = &turingcc_regmap_config, |
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.clks = turingcc_clocks, |
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.num_clks = ARRAY_SIZE(turingcc_clocks), |
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}; |
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static int turingcc_probe(struct platform_device *pdev) |
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{ |
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int ret; |
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ret = devm_pm_runtime_enable(&pdev->dev); |
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if (ret) |
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return ret; |
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ret = devm_pm_clk_create(&pdev->dev); |
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if (ret) |
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return ret; |
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ret = pm_clk_add(&pdev->dev, NULL); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to acquire iface clock\n"); |
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return ret; |
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} |
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ret = qcom_cc_probe(pdev, &turingcc_desc); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static const struct dev_pm_ops turingcc_pm_ops = { |
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SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) |
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}; |
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static const struct of_device_id turingcc_match_table[] = { |
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{ .compatible = "qcom,qcs404-turingcc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, turingcc_match_table); |
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static struct platform_driver turingcc_driver = { |
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.probe = turingcc_probe, |
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.driver = { |
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.name = "qcs404-turingcc", |
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.of_match_table = turingcc_match_table, |
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.pm = &turingcc_pm_ops, |
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}, |
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}; |
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module_platform_driver(turingcc_driver); |
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MODULE_DESCRIPTION("Qualcomm QCS404 Turing Clock Controller"); |
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MODULE_LICENSE("GPL v2");
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