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1286 lines
34 KiB
1286 lines
34 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/reset-controller.h> |
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#include <dt-bindings/clock/qcom,dispcc-sm8250.h> |
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#include "clk-alpha-pll.h" |
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#include "clk-branch.h" |
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#include "clk-rcg.h" |
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#include "clk-regmap-divider.h" |
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#include "common.h" |
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#include "gdsc.h" |
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#include "reset.h" |
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enum { |
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P_BI_TCXO, |
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P_DISP_CC_PLL0_OUT_MAIN, |
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P_DISP_CC_PLL1_OUT_EVEN, |
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P_DISP_CC_PLL1_OUT_MAIN, |
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P_DP_PHY_PLL_LINK_CLK, |
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P_DP_PHY_PLL_VCO_DIV_CLK, |
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P_DPTX1_PHY_PLL_LINK_CLK, |
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P_DPTX1_PHY_PLL_VCO_DIV_CLK, |
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P_DPTX2_PHY_PLL_LINK_CLK, |
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P_DPTX2_PHY_PLL_VCO_DIV_CLK, |
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P_EDP_PHY_PLL_LINK_CLK, |
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P_EDP_PHY_PLL_VCO_DIV_CLK, |
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P_DSI0_PHY_PLL_OUT_BYTECLK, |
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P_DSI0_PHY_PLL_OUT_DSICLK, |
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P_DSI1_PHY_PLL_OUT_BYTECLK, |
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P_DSI1_PHY_PLL_OUT_DSICLK, |
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}; |
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static struct pll_vco vco_table[] = { |
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{ 249600000, 2000000000, 0 }, |
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}; |
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static struct alpha_pll_config disp_cc_pll0_config = { |
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.l = 0x47, |
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.alpha = 0xE000, |
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.config_ctl_val = 0x20485699, |
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.config_ctl_hi_val = 0x00002261, |
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.config_ctl_hi1_val = 0x329A699C, |
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.user_ctl_val = 0x00000000, |
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.user_ctl_hi_val = 0x00000805, |
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.user_ctl_hi1_val = 0x00000000, |
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}; |
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static struct clk_init_data disp_cc_pll0_init = { |
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.name = "disp_cc_pll0", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_lucid_ops, |
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}; |
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static struct clk_alpha_pll disp_cc_pll0 = { |
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.offset = 0x0, |
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.vco_table = vco_table, |
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.num_vco = ARRAY_SIZE(vco_table), |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
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.clkr.hw.init = &disp_cc_pll0_init |
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}; |
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static struct alpha_pll_config disp_cc_pll1_config = { |
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.l = 0x1F, |
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.alpha = 0x4000, |
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.config_ctl_val = 0x20485699, |
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.config_ctl_hi_val = 0x00002261, |
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.config_ctl_hi1_val = 0x329A699C, |
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.user_ctl_val = 0x00000000, |
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.user_ctl_hi_val = 0x00000805, |
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.user_ctl_hi1_val = 0x00000000, |
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}; |
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static struct clk_init_data disp_cc_pll1_init = { |
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.name = "disp_cc_pll1", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_lucid_ops, |
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}; |
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static struct clk_alpha_pll disp_cc_pll1 = { |
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.offset = 0x1000, |
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.vco_table = vco_table, |
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.num_vco = ARRAY_SIZE(vco_table), |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
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.clkr.hw.init = &disp_cc_pll1_init |
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}; |
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static const struct parent_map disp_cc_parent_map_0[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DP_PHY_PLL_LINK_CLK, 1 }, |
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{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, |
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{ P_DPTX1_PHY_PLL_LINK_CLK, 3 }, |
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{ P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, |
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{ P_DPTX2_PHY_PLL_LINK_CLK, 5 }, |
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{ P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_0[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "dp_phy_pll_link_clk" }, |
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{ .fw_name = "dp_phy_pll_vco_div_clk" }, |
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{ .fw_name = "dptx1_phy_pll_link_clk" }, |
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{ .fw_name = "dptx1_phy_pll_vco_div_clk" }, |
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{ .fw_name = "dptx2_phy_pll_link_clk" }, |
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{ .fw_name = "dptx2_phy_pll_vco_div_clk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_1[] = { |
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{ P_BI_TCXO, 0 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_1[] = { |
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{ .fw_name = "bi_tcxo" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_2[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, |
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_2[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "dsi0_phy_pll_out_byteclk" }, |
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{ .fw_name = "dsi1_phy_pll_out_byteclk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_3[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_3[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &disp_cc_pll1.clkr.hw }, |
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}; |
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static const struct parent_map disp_cc_parent_map_4[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_EDP_PHY_PLL_LINK_CLK, 1 }, |
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{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_4[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "edp_phy_pll_link_clk" }, |
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{ .fw_name = "edp_phy_pll_vco_div_clk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_5[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 }, |
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_5[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &disp_cc_pll0.clkr.hw }, |
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{ .hw = &disp_cc_pll1.clkr.hw }, |
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}; |
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static const struct parent_map disp_cc_parent_map_6[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, |
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_6[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "dsi0_phy_pll_out_dsiclk" }, |
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{ .fw_name = "dsi1_phy_pll_out_dsiclk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_7[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DISP_CC_PLL1_OUT_MAIN, 4 }, |
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/* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_7[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &disp_cc_pll1.clkr.hw }, |
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/* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), |
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F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { |
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.cmd_rcgr = 0x22bc, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_3, |
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_ahb_clk_src", |
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.parent_data = disp_cc_parent_data_3, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_shared_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { |
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.cmd_rcgr = 0x2110, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_2, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_byte0_clk_src", |
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.parent_data = disp_cc_parent_data_2, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_byte2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { |
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.cmd_rcgr = 0x212c, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_2, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_byte1_clk_src", |
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.parent_data = disp_cc_parent_data_2, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_byte2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { |
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.cmd_rcgr = 0x2240, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_1, |
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.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_aux1_clk_src", |
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.parent_data = disp_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { |
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.cmd_rcgr = 0x21dc, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_1, |
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.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_aux_clk_src", |
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.parent_data = disp_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { |
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.cmd_rcgr = 0x220c, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_link1_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.ops = &clk_byte2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { |
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.cmd_rcgr = 0x2178, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_link_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.ops = &clk_byte2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { |
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.cmd_rcgr = 0x21c4, |
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.mnd_width = 16, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_pixel1_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.ops = &clk_dp_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { |
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.cmd_rcgr = 0x21f4, |
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.mnd_width = 16, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_pixel2_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.ops = &clk_dp_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { |
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.cmd_rcgr = 0x21ac, |
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.mnd_width = 16, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_pixel_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.ops = &clk_dp_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { |
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.cmd_rcgr = 0x228c, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_1, |
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.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_aux_clk_src", |
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.parent_data = disp_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { |
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.cmd_rcgr = 0x22a4, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_7, |
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.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_gtc_clk_src", |
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.parent_data = disp_cc_parent_data_7, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_7), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { |
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.cmd_rcgr = 0x2270, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_4, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_link_clk_src", |
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.parent_data = disp_cc_parent_data_4, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_byte2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { |
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.cmd_rcgr = 0x2258, |
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.mnd_width = 16, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_4, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_pixel_clk_src", |
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.parent_data = disp_cc_parent_data_4, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4), |
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.ops = &clk_dp_ops, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_edp_aux_clk = { |
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.halt_reg = 0x2078, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x2078, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_aux_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_edp_aux_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_edp_gtc_clk = { |
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.halt_reg = 0x207c, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x207c, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_gtc_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_edp_gtc_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_edp_link_clk = { |
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.halt_reg = 0x2070, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x2070, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_link_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_edp_link_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { |
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.halt_reg = 0x2074, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x2074, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_edp_link_intf_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_edp_link_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_GET_RATE_NOCACHE, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_edp_pixel_clk = { |
|
.halt_reg = 0x206c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x206c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_edp_pixel_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_edp_pixel_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { |
|
.cmd_rcgr = 0x2148, |
|
.mnd_width = 0, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_2, |
|
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_esc0_clk_src", |
|
.parent_data = disp_cc_parent_data_2, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_rcg2_ops, |
|
}, |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { |
|
.cmd_rcgr = 0x2160, |
|
.mnd_width = 0, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_2, |
|
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_esc1_clk_src", |
|
.parent_data = disp_cc_parent_data_2, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_rcg2_ops, |
|
}, |
|
}; |
|
|
|
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { |
|
F(19200000, P_BI_TCXO, 1, 0, 0), |
|
F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), |
|
F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), |
|
F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), |
|
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), |
|
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), |
|
F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), |
|
F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), |
|
{ } |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { |
|
.cmd_rcgr = 0x20c8, |
|
.mnd_width = 0, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_5, |
|
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_mdp_clk_src", |
|
.parent_data = disp_cc_parent_data_5, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_rcg2_shared_ops, |
|
}, |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { |
|
.cmd_rcgr = 0x2098, |
|
.mnd_width = 8, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_6, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_pclk0_clk_src", |
|
.parent_data = disp_cc_parent_data_6, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_pixel_ops, |
|
}, |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { |
|
.cmd_rcgr = 0x20b0, |
|
.mnd_width = 8, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_6, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_pclk1_clk_src", |
|
.parent_data = disp_cc_parent_data_6, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_pixel_ops, |
|
}, |
|
}; |
|
|
|
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { |
|
F(19200000, P_BI_TCXO, 1, 0, 0), |
|
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), |
|
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), |
|
F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), |
|
F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), |
|
{ } |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { |
|
.cmd_rcgr = 0x20e0, |
|
.mnd_width = 0, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_5, |
|
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rot_clk_src", |
|
.parent_data = disp_cc_parent_data_5, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_rcg2_shared_ops, |
|
}, |
|
}; |
|
|
|
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { |
|
.cmd_rcgr = 0x20f8, |
|
.mnd_width = 0, |
|
.hid_width = 5, |
|
.parent_map = disp_cc_parent_map_1, |
|
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, |
|
.clkr.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_vsync_clk_src", |
|
.parent_data = disp_cc_parent_data_1, |
|
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1), |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_rcg2_ops, |
|
}, |
|
}; |
|
|
|
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { |
|
.reg = 0x2128, |
|
.shift = 0, |
|
.width = 2, |
|
.clkr.hw.init = &(struct clk_init_data) { |
|
.name = "disp_cc_mdss_byte0_div_clk_src", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_byte0_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_regmap_div_ops, |
|
}, |
|
}; |
|
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { |
|
.reg = 0x2144, |
|
.shift = 0, |
|
.width = 2, |
|
.clkr.hw.init = &(struct clk_init_data) { |
|
.name = "disp_cc_mdss_byte1_div_clk_src", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_byte1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_regmap_div_ops, |
|
}, |
|
}; |
|
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { |
|
.reg = 0x2224, |
|
.shift = 0, |
|
.width = 2, |
|
.clkr.hw.init = &(struct clk_init_data) { |
|
.name = "disp_cc_mdss_dp_link1_div_clk_src", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_regmap_div_ro_ops, |
|
}, |
|
}; |
|
|
|
|
|
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { |
|
.reg = 0x2190, |
|
.shift = 0, |
|
.width = 2, |
|
.clkr.hw.init = &(struct clk_init_data) { |
|
.name = "disp_cc_mdss_dp_link_div_clk_src", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_regmap_div_ro_ops, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_ahb_clk = { |
|
.halt_reg = 0x2080, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2080, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_ahb_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_ahb_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_byte0_clk = { |
|
.halt_reg = 0x2028, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2028, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_byte0_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_byte0_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_byte0_intf_clk = { |
|
.halt_reg = 0x202c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x202c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_byte0_intf_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_byte0_div_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_byte1_clk = { |
|
.halt_reg = 0x2030, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2030, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_byte1_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_byte1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_byte1_intf_clk = { |
|
.halt_reg = 0x2034, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2034, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_byte1_intf_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_byte1_div_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_aux1_clk = { |
|
.halt_reg = 0x2068, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2068, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_aux1_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_aux1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_aux_clk = { |
|
.halt_reg = 0x2054, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2054, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_aux_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_aux_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_link1_clk = { |
|
.halt_reg = 0x205c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x205c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_link1_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { |
|
.halt_reg = 0x2060, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2060, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_link1_intf_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_link_clk = { |
|
.halt_reg = 0x2040, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2040, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_link_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { |
|
.halt_reg = 0x2044, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2044, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_link_intf_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { |
|
.halt_reg = 0x2050, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2050, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_pixel1_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { |
|
.halt_reg = 0x2058, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2058, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_pixel2_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel_clk = { |
|
.halt_reg = 0x204c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x204c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_pixel_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_esc0_clk = { |
|
.halt_reg = 0x2038, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2038, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_esc0_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_esc0_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_esc1_clk = { |
|
.halt_reg = 0x203c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x203c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_esc1_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_esc1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_mdp_clk = { |
|
.halt_reg = 0x200c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x200c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_mdp_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_mdp_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut_clk = { |
|
.halt_reg = 0x201c, |
|
.halt_check = BRANCH_VOTED, |
|
.clkr = { |
|
.enable_reg = 0x201c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_mdp_lut_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_mdp_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { |
|
.halt_reg = 0x4004, |
|
.halt_check = BRANCH_VOTED, |
|
.clkr = { |
|
.enable_reg = 0x4004, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_non_gdsc_ahb_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_ahb_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_pclk0_clk = { |
|
.halt_reg = 0x2004, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2004, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_pclk0_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_pclk0_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_pclk1_clk = { |
|
.halt_reg = 0x2008, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2008, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_pclk1_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_pclk1_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_rot_clk = { |
|
.halt_reg = 0x2014, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2014, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rot_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_rot_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { |
|
.halt_reg = 0x400c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x400c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rscc_ahb_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_ahb_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { |
|
.halt_reg = 0x4008, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x4008, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rscc_vsync_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_vsync_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = { |
|
.halt_reg = 0x2024, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2024, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_vsync_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_vsync_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct gdsc mdss_gdsc = { |
|
.gdscr = 0x3000, |
|
.pd = { |
|
.name = "mdss_gdsc", |
|
}, |
|
.pwrsts = PWRSTS_OFF_ON, |
|
.flags = HW_CTRL, |
|
.supply = "mmcx", |
|
}; |
|
|
|
static struct clk_regmap *disp_cc_sm8250_clocks[] = { |
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, |
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, |
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, |
|
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, |
|
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, |
|
[DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, |
|
[DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, |
|
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, |
|
[DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, |
|
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, |
|
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, |
|
[DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, |
|
[DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, |
|
[DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, |
|
[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, |
|
[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, |
|
[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, |
|
[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, |
|
[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, |
|
[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, |
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, |
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, |
|
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, |
|
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, |
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, |
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, |
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, |
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, |
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, |
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, |
|
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, |
|
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, |
|
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, |
|
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, |
|
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, |
|
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, |
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, |
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, |
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr, |
|
[DISP_CC_PLL1] = &disp_cc_pll1.clkr, |
|
}; |
|
|
|
static const struct qcom_reset_map disp_cc_sm8250_resets[] = { |
|
[DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, |
|
[DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, |
|
}; |
|
|
|
static struct gdsc *disp_cc_sm8250_gdscs[] = { |
|
[MDSS_GDSC] = &mdss_gdsc, |
|
}; |
|
|
|
static const struct regmap_config disp_cc_sm8250_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.max_register = 0x10000, |
|
.fast_io = true, |
|
}; |
|
|
|
static const struct qcom_cc_desc disp_cc_sm8250_desc = { |
|
.config = &disp_cc_sm8250_regmap_config, |
|
.clks = disp_cc_sm8250_clocks, |
|
.num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks), |
|
.resets = disp_cc_sm8250_resets, |
|
.num_resets = ARRAY_SIZE(disp_cc_sm8250_resets), |
|
.gdscs = disp_cc_sm8250_gdscs, |
|
.num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs), |
|
}; |
|
|
|
static const struct of_device_id disp_cc_sm8250_match_table[] = { |
|
{ .compatible = "qcom,sc8180x-dispcc" }, |
|
{ .compatible = "qcom,sm8150-dispcc" }, |
|
{ .compatible = "qcom,sm8250-dispcc" }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); |
|
|
|
static int disp_cc_sm8250_probe(struct platform_device *pdev) |
|
{ |
|
struct regmap *regmap; |
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); |
|
if (IS_ERR(regmap)) |
|
return PTR_ERR(regmap); |
|
|
|
/* note: trion == lucid, except for the prepare() op */ |
|
BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); |
|
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || |
|
of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { |
|
disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; |
|
disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; |
|
disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; |
|
disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; |
|
disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; |
|
disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; |
|
disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; |
|
disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; |
|
} |
|
|
|
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); |
|
clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); |
|
|
|
/* Enable clock gating for MDP clocks */ |
|
regmap_update_bits(regmap, 0x8000, 0x10, 0x10); |
|
|
|
/* DISP_CC_XO_CLK always-on */ |
|
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); |
|
|
|
return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); |
|
} |
|
|
|
static struct platform_driver disp_cc_sm8250_driver = { |
|
.probe = disp_cc_sm8250_probe, |
|
.driver = { |
|
.name = "disp_cc-sm8250", |
|
.of_match_table = disp_cc_sm8250_match_table, |
|
}, |
|
}; |
|
|
|
static int __init disp_cc_sm8250_init(void) |
|
{ |
|
return platform_driver_register(&disp_cc_sm8250_driver); |
|
} |
|
subsys_initcall(disp_cc_sm8250_init); |
|
|
|
static void __exit disp_cc_sm8250_exit(void) |
|
{ |
|
platform_driver_unregister(&disp_cc_sm8250_driver); |
|
} |
|
module_exit(disp_cc_sm8250_exit); |
|
|
|
MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|