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85 lines
2.7 KiB
85 lines
2.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// |
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// Copyright (c) 2021 MediaTek Inc. |
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// Author: Chun-Jie Chen <[email protected]> |
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#include <linux/clk-provider.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt8192-clk.h> |
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static const struct mtk_gate_regs msdc_cg_regs = { |
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.set_ofs = 0xb4, |
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.clr_ofs = 0xb4, |
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.sta_ofs = 0xb4, |
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}; |
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static const struct mtk_gate_regs msdc_top_cg_regs = { |
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.set_ofs = 0x0, |
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.clr_ofs = 0x0, |
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.sta_ofs = 0x0, |
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}; |
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#define GATE_MSDC(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
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#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
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static const struct mtk_gate msdc_clks[] = { |
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GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22), |
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}; |
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static const struct mtk_gate msdc_top_clks[] = { |
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GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p", "infra_msdc1_src", 2), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p", "infra_msdc2_src", 3), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0", "axi_sel", 4), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1", "axi_sel", 5), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2", "axi_sel", 6), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p", "infra_msdc0", 9), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p", "infra_msdc1", 10), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p", "infra_msdc2", 11), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m", "clk26m", 12), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k", "clk32k", 13), |
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GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14), |
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}; |
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static const struct mtk_clk_desc msdc_desc = { |
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.clks = msdc_clks, |
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.num_clks = ARRAY_SIZE(msdc_clks), |
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}; |
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static const struct mtk_clk_desc msdc_top_desc = { |
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.clks = msdc_top_clks, |
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.num_clks = ARRAY_SIZE(msdc_top_clks), |
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}; |
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static const struct of_device_id of_match_clk_mt8192_msdc[] = { |
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{ |
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.compatible = "mediatek,mt8192-msdc", |
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.data = &msdc_desc, |
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}, { |
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.compatible = "mediatek,mt8192-msdc_top", |
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.data = &msdc_top_desc, |
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}, { |
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/* sentinel */ |
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} |
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}; |
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static struct platform_driver clk_mt8192_msdc_drv = { |
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.probe = mtk_clk_simple_probe, |
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.driver = { |
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.name = "clk-mt8192-msdc", |
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.of_match_table = of_match_clk_mt8192_msdc, |
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}, |
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}; |
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builtin_platform_driver(clk_mt8192_msdc_drv);
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