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123 lines
3.5 KiB
123 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Copyright (c) 2018 MediaTek Inc. |
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// Author: Weiyi Lu <[email protected]> |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt8183-clk.h> |
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static const struct mtk_gate_regs ipu_conn_cg_regs = { |
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.set_ofs = 0x4, |
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.clr_ofs = 0x8, |
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.sta_ofs = 0x0, |
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}; |
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static const struct mtk_gate_regs ipu_conn_apb_cg_regs = { |
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.set_ofs = 0x10, |
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.clr_ofs = 0x10, |
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.sta_ofs = 0x10, |
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}; |
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static const struct mtk_gate_regs ipu_conn_axi_cg_regs = { |
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.set_ofs = 0x18, |
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.clr_ofs = 0x18, |
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.sta_ofs = 0x18, |
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}; |
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static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = { |
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.set_ofs = 0x1c, |
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.clr_ofs = 0x1c, |
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.sta_ofs = 0x1c, |
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}; |
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static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = { |
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.set_ofs = 0x20, |
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.clr_ofs = 0x20, |
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.sta_ofs = 0x20, |
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}; |
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#define GATE_IPU_CONN(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \ |
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&mtk_clk_gate_ops_setclr) |
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#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \ |
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&mtk_clk_gate_ops_no_setclr) |
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#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \ |
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&mtk_clk_gate_ops_no_setclr_inv) |
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#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \ |
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&mtk_clk_gate_ops_no_setclr_inv) |
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#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ |
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GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \ |
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&mtk_clk_gate_ops_no_setclr_inv) |
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static const struct mtk_gate ipu_conn_clks[] = { |
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GATE_IPU_CONN(CLK_IPU_CONN_IPU, |
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"ipu_conn_ipu", "dsp_sel", 0), |
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GATE_IPU_CONN(CLK_IPU_CONN_AHB, |
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"ipu_conn_ahb", "dsp_sel", 1), |
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GATE_IPU_CONN(CLK_IPU_CONN_AXI, |
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"ipu_conn_axi", "dsp_sel", 2), |
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GATE_IPU_CONN(CLK_IPU_CONN_ISP, |
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"ipu_conn_isp", "dsp_sel", 3), |
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GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL, |
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"ipu_conn_cam_adl", "dsp_sel", 4), |
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GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL, |
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"ipu_conn_img_adl", "dsp_sel", 5), |
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GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX, |
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"ipu_conn_dap_rx", "dsp1_sel", 0), |
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GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI, |
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"ipu_conn_apb2axi", "dsp1_sel", 3), |
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GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB, |
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"ipu_conn_apb2ahb", "dsp1_sel", 20), |
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GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2, |
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"ipu_conn_ipu_cab1to2", "dsp1_sel", 6), |
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GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2, |
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"ipu_conn_ipu1_cab1to2", "dsp1_sel", 13), |
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GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2, |
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"ipu_conn_ipu2_cab1to2", "dsp1_sel", 20), |
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GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3, |
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"ipu_conn_cab3to3", "dsp1_sel", 0), |
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GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1, |
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"ipu_conn_cab2to1", "dsp1_sel", 14), |
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GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE, |
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"ipu_conn_cab3to1_slice", "dsp1_sel", 17), |
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}; |
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static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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struct device_node *node = pdev->dev.of_node; |
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clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK); |
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mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks), |
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clk_data); |
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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} |
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static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = { |
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{ .compatible = "mediatek,mt8183-ipu_conn", }, |
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{} |
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}; |
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static struct platform_driver clk_mt8183_ipu_conn_drv = { |
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.probe = clk_mt8183_ipu_conn_probe, |
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.driver = { |
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.name = "clk-mt8183-ipu_conn", |
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.of_match_table = of_match_clk_mt8183_ipu_conn, |
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}, |
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}; |
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builtin_platform_driver(clk_mt8183_ipu_conn_drv);
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