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94 lines
3.1 KiB
94 lines
3.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2017 MediaTek Inc. |
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* Author: Weiyi Lu <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt2712-clk.h> |
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static const struct mtk_gate_regs bdp_cg_regs = { |
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.set_ofs = 0x100, |
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.clr_ofs = 0x100, |
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.sta_ofs = 0x100, |
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}; |
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#define GATE_BDP(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &bdp_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_no_setclr, \ |
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} |
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static const struct mtk_gate bdp_clks[] = { |
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GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), |
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GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1), |
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GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2), |
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GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3), |
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GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4), |
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GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5), |
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GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9), |
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GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10), |
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GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11), |
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GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12), |
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GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13), |
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GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14), |
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GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15), |
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GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16), |
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GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17), |
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GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18), |
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GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19), |
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GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20), |
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GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21), |
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GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22), |
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GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23), |
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GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24), |
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GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25), |
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GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26), |
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GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27), |
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GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28), |
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GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29), |
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GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30), |
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}; |
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static int clk_mt2712_bdp_probe(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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int r; |
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struct device_node *node = pdev->dev.of_node; |
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clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK); |
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mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r != 0) |
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pr_err("%s(): could not register clock provider: %d\n", |
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__func__, r); |
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return r; |
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} |
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static const struct of_device_id of_match_clk_mt2712_bdp[] = { |
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{ .compatible = "mediatek,mt2712-bdpsys", }, |
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{} |
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}; |
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static struct platform_driver clk_mt2712_bdp_drv = { |
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.probe = clk_mt2712_bdp_probe, |
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.driver = { |
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.name = "clk-mt2712-bdp", |
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.of_match_table = of_match_clk_mt2712_bdp, |
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}, |
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}; |
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builtin_platform_driver(clk_mt2712_bdp_drv);
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