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25 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2019-20 Sean Anderson <[email protected]> |
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* Copyright (c) 2019 Western Digital Corporation or its affiliates. |
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*/ |
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#define pr_fmt(fmt) "k210-clk: " fmt |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/platform_device.h> |
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#include <linux/of.h> |
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#include <linux/of_clk.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_address.h> |
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#include <linux/clk-provider.h> |
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#include <linux/bitfield.h> |
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#include <linux/delay.h> |
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#include <soc/canaan/k210-sysctl.h> |
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#include <dt-bindings/clock/k210-clk.h> |
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struct k210_sysclk; |
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struct k210_clk { |
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int id; |
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struct k210_sysclk *ksc; |
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struct clk_hw hw; |
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}; |
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struct k210_clk_cfg { |
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const char *name; |
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u8 gate_reg; |
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u8 gate_bit; |
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u8 div_reg; |
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u8 div_shift; |
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u8 div_width; |
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u8 div_type; |
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u8 mux_reg; |
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u8 mux_bit; |
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}; |
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enum k210_clk_div_type { |
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K210_DIV_NONE, |
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K210_DIV_ONE_BASED, |
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K210_DIV_DOUBLE_ONE_BASED, |
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K210_DIV_POWER_OF_TWO, |
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}; |
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#define K210_GATE(_reg, _bit) \ |
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.gate_reg = (_reg), \ |
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.gate_bit = (_bit) |
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#define K210_DIV(_reg, _shift, _width, _type) \ |
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.div_reg = (_reg), \ |
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.div_shift = (_shift), \ |
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.div_width = (_width), \ |
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.div_type = (_type) |
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#define K210_MUX(_reg, _bit) \ |
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.mux_reg = (_reg), \ |
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.mux_bit = (_bit) |
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static struct k210_clk_cfg k210_clk_cfgs[K210_NUM_CLKS] = { |
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/* Gated clocks, no mux, no divider */ |
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[K210_CLK_CPU] = { |
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.name = "cpu", |
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K210_GATE(K210_SYSCTL_EN_CENT, 0) |
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}, |
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[K210_CLK_DMA] = { |
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.name = "dma", |
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K210_GATE(K210_SYSCTL_EN_PERI, 1) |
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}, |
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[K210_CLK_FFT] = { |
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.name = "fft", |
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K210_GATE(K210_SYSCTL_EN_PERI, 4) |
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}, |
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[K210_CLK_GPIO] = { |
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.name = "gpio", |
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K210_GATE(K210_SYSCTL_EN_PERI, 5) |
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}, |
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[K210_CLK_UART1] = { |
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.name = "uart1", |
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K210_GATE(K210_SYSCTL_EN_PERI, 16) |
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}, |
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[K210_CLK_UART2] = { |
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.name = "uart2", |
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K210_GATE(K210_SYSCTL_EN_PERI, 17) |
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}, |
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[K210_CLK_UART3] = { |
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.name = "uart3", |
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K210_GATE(K210_SYSCTL_EN_PERI, 18) |
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}, |
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[K210_CLK_FPIOA] = { |
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.name = "fpioa", |
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K210_GATE(K210_SYSCTL_EN_PERI, 20) |
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}, |
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[K210_CLK_SHA] = { |
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.name = "sha", |
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K210_GATE(K210_SYSCTL_EN_PERI, 26) |
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}, |
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[K210_CLK_AES] = { |
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.name = "aes", |
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K210_GATE(K210_SYSCTL_EN_PERI, 19) |
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}, |
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[K210_CLK_OTP] = { |
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.name = "otp", |
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K210_GATE(K210_SYSCTL_EN_PERI, 27) |
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}, |
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[K210_CLK_RTC] = { |
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.name = "rtc", |
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K210_GATE(K210_SYSCTL_EN_PERI, 29) |
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}, |
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/* Gated divider clocks */ |
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[K210_CLK_SRAM0] = { |
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.name = "sram0", |
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K210_GATE(K210_SYSCTL_EN_CENT, 1), |
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K210_DIV(K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_SRAM1] = { |
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.name = "sram1", |
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K210_GATE(K210_SYSCTL_EN_CENT, 2), |
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K210_DIV(K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_ROM] = { |
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.name = "rom", |
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K210_GATE(K210_SYSCTL_EN_PERI, 0), |
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K210_DIV(K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_DVP] = { |
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.name = "dvp", |
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K210_GATE(K210_SYSCTL_EN_PERI, 3), |
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K210_DIV(K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_APB0] = { |
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.name = "apb0", |
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K210_GATE(K210_SYSCTL_EN_CENT, 3), |
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K210_DIV(K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_APB1] = { |
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.name = "apb1", |
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K210_GATE(K210_SYSCTL_EN_CENT, 4), |
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K210_DIV(K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_APB2] = { |
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.name = "apb2", |
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K210_GATE(K210_SYSCTL_EN_CENT, 5), |
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K210_DIV(K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_AI] = { |
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.name = "ai", |
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K210_GATE(K210_SYSCTL_EN_PERI, 2), |
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K210_DIV(K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE_BASED) |
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}, |
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[K210_CLK_SPI0] = { |
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.name = "spi0", |
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K210_GATE(K210_SYSCTL_EN_PERI, 6), |
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K210_DIV(K210_SYSCTL_THR1, 0, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_SPI1] = { |
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.name = "spi1", |
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K210_GATE(K210_SYSCTL_EN_PERI, 7), |
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K210_DIV(K210_SYSCTL_THR1, 8, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_SPI2] = { |
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.name = "spi2", |
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K210_GATE(K210_SYSCTL_EN_PERI, 8), |
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K210_DIV(K210_SYSCTL_THR1, 16, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2C0] = { |
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.name = "i2c0", |
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K210_GATE(K210_SYSCTL_EN_PERI, 13), |
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K210_DIV(K210_SYSCTL_THR5, 8, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2C1] = { |
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.name = "i2c1", |
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K210_GATE(K210_SYSCTL_EN_PERI, 14), |
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K210_DIV(K210_SYSCTL_THR5, 16, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2C2] = { |
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.name = "i2c2", |
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K210_GATE(K210_SYSCTL_EN_PERI, 15), |
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K210_DIV(K210_SYSCTL_THR5, 24, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_WDT0] = { |
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.name = "wdt0", |
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K210_GATE(K210_SYSCTL_EN_PERI, 24), |
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K210_DIV(K210_SYSCTL_THR6, 0, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_WDT1] = { |
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.name = "wdt1", |
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K210_GATE(K210_SYSCTL_EN_PERI, 25), |
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K210_DIV(K210_SYSCTL_THR6, 8, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2S0] = { |
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.name = "i2s0", |
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K210_GATE(K210_SYSCTL_EN_PERI, 10), |
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K210_DIV(K210_SYSCTL_THR3, 0, 16, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2S1] = { |
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.name = "i2s1", |
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K210_GATE(K210_SYSCTL_EN_PERI, 11), |
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K210_DIV(K210_SYSCTL_THR3, 16, 16, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2S2] = { |
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.name = "i2s2", |
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K210_GATE(K210_SYSCTL_EN_PERI, 12), |
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K210_DIV(K210_SYSCTL_THR4, 0, 16, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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/* Divider clocks, no gate, no mux */ |
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[K210_CLK_I2S0_M] = { |
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.name = "i2s0_m", |
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K210_DIV(K210_SYSCTL_THR4, 16, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2S1_M] = { |
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.name = "i2s1_m", |
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K210_DIV(K210_SYSCTL_THR4, 24, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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[K210_CLK_I2S2_M] = { |
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.name = "i2s2_m", |
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K210_DIV(K210_SYSCTL_THR4, 0, 8, K210_DIV_DOUBLE_ONE_BASED) |
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}, |
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/* Muxed gated divider clocks */ |
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[K210_CLK_SPI3] = { |
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.name = "spi3", |
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K210_GATE(K210_SYSCTL_EN_PERI, 9), |
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K210_DIV(K210_SYSCTL_THR1, 24, 8, K210_DIV_DOUBLE_ONE_BASED), |
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K210_MUX(K210_SYSCTL_SEL0, 12) |
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}, |
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[K210_CLK_TIMER0] = { |
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.name = "timer0", |
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K210_GATE(K210_SYSCTL_EN_PERI, 21), |
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K210_DIV(K210_SYSCTL_THR2, 0, 8, K210_DIV_DOUBLE_ONE_BASED), |
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K210_MUX(K210_SYSCTL_SEL0, 13) |
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}, |
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[K210_CLK_TIMER1] = { |
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.name = "timer1", |
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K210_GATE(K210_SYSCTL_EN_PERI, 22), |
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K210_DIV(K210_SYSCTL_THR2, 8, 8, K210_DIV_DOUBLE_ONE_BASED), |
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K210_MUX(K210_SYSCTL_SEL0, 14) |
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}, |
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[K210_CLK_TIMER2] = { |
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.name = "timer2", |
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K210_GATE(K210_SYSCTL_EN_PERI, 23), |
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K210_DIV(K210_SYSCTL_THR2, 16, 8, K210_DIV_DOUBLE_ONE_BASED), |
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K210_MUX(K210_SYSCTL_SEL0, 15) |
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}, |
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}; |
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/* |
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* PLL control register bits. |
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*/ |
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#define K210_PLL_CLKR GENMASK(3, 0) |
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#define K210_PLL_CLKF GENMASK(9, 4) |
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#define K210_PLL_CLKOD GENMASK(13, 10) |
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#define K210_PLL_BWADJ GENMASK(19, 14) |
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#define K210_PLL_RESET (1 << 20) |
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#define K210_PLL_PWRD (1 << 21) |
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#define K210_PLL_INTFB (1 << 22) |
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#define K210_PLL_BYPASS (1 << 23) |
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#define K210_PLL_TEST (1 << 24) |
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#define K210_PLL_EN (1 << 25) |
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#define K210_PLL_SEL GENMASK(27, 26) /* PLL2 only */ |
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/* |
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* PLL lock register bits. |
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*/ |
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#define K210_PLL_LOCK 0 |
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#define K210_PLL_CLEAR_SLIP 2 |
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#define K210_PLL_TEST_OUT 3 |
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/* |
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* Clock selector register bits. |
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*/ |
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#define K210_ACLK_SEL BIT(0) |
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#define K210_ACLK_DIV GENMASK(2, 1) |
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/* |
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* PLLs. |
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*/ |
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enum k210_pll_id { |
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K210_PLL0, K210_PLL1, K210_PLL2, K210_PLL_NUM |
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}; |
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struct k210_pll { |
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enum k210_pll_id id; |
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struct k210_sysclk *ksc; |
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void __iomem *base; |
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void __iomem *reg; |
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void __iomem *lock; |
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u8 lock_shift; |
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u8 lock_width; |
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struct clk_hw hw; |
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}; |
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#define to_k210_pll(_hw) container_of(_hw, struct k210_pll, hw) |
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/* |
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* PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz. |
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* The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0 |
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* rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the |
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* same clock as the first 2. |
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*/ |
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struct k210_pll_cfg { |
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u32 reg; |
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u8 lock_shift; |
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u8 lock_width; |
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u32 r; |
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u32 f; |
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u32 od; |
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u32 bwadj; |
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}; |
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static struct k210_pll_cfg k210_plls_cfg[] = { |
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{ K210_SYSCTL_PLL0, 0, 2, 0, 59, 1, 59 }, /* 780 MHz */ |
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{ K210_SYSCTL_PLL1, 8, 1, 0, 59, 3, 59 }, /* 390 MHz */ |
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{ K210_SYSCTL_PLL2, 16, 1, 0, 22, 1, 22 }, /* 299 MHz */ |
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}; |
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/** |
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* struct k210_sysclk - sysclk driver data |
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* @regs: system controller registers start address |
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* @clk_lock: clock setting spinlock |
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* @plls: SoC PLLs descriptors |
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* @aclk: ACLK clock |
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* @clks: All other clocks |
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*/ |
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struct k210_sysclk { |
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void __iomem *regs; |
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spinlock_t clk_lock; |
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struct k210_pll plls[K210_PLL_NUM]; |
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struct clk_hw aclk; |
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struct k210_clk clks[K210_NUM_CLKS]; |
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}; |
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#define to_k210_sysclk(_hw) container_of(_hw, struct k210_sysclk, aclk) |
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/* |
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* Set ACLK parent selector: 0 for IN0, 1 for PLL0. |
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*/ |
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static void k210_aclk_set_selector(void __iomem *regs, u8 sel) |
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{ |
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u32 reg = readl(regs + K210_SYSCTL_SEL0); |
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if (sel) |
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reg |= K210_ACLK_SEL; |
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else |
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reg &= K210_ACLK_SEL; |
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writel(reg, regs + K210_SYSCTL_SEL0); |
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} |
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static void k210_init_pll(void __iomem *regs, enum k210_pll_id pllid, |
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struct k210_pll *pll) |
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{ |
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pll->id = pllid; |
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pll->reg = regs + k210_plls_cfg[pllid].reg; |
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pll->lock = regs + K210_SYSCTL_PLL_LOCK; |
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pll->lock_shift = k210_plls_cfg[pllid].lock_shift; |
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pll->lock_width = k210_plls_cfg[pllid].lock_width; |
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} |
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static void k210_pll_wait_for_lock(struct k210_pll *pll) |
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{ |
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u32 reg, mask = GENMASK(pll->lock_shift + pll->lock_width - 1, |
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pll->lock_shift); |
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while (true) { |
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reg = readl(pll->lock); |
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if ((reg & mask) == mask) |
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break; |
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reg |= BIT(pll->lock_shift + K210_PLL_CLEAR_SLIP); |
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writel(reg, pll->lock); |
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} |
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} |
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static bool k210_pll_hw_is_enabled(struct k210_pll *pll) |
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{ |
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u32 reg = readl(pll->reg); |
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u32 mask = K210_PLL_PWRD | K210_PLL_EN; |
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if (reg & K210_PLL_RESET) |
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return false; |
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return (reg & mask) == mask; |
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} |
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static void k210_pll_enable_hw(void __iomem *regs, struct k210_pll *pll) |
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{ |
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struct k210_pll_cfg *pll_cfg = &k210_plls_cfg[pll->id]; |
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u32 reg; |
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if (k210_pll_hw_is_enabled(pll)) |
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return; |
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/* |
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* For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and |
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* SRAM running. |
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*/ |
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if (pll->id == K210_PLL0) |
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k210_aclk_set_selector(regs, 0); |
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/* Set PLL factors */ |
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reg = readl(pll->reg); |
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reg &= ~GENMASK(19, 0); |
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reg |= FIELD_PREP(K210_PLL_CLKR, pll_cfg->r); |
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reg |= FIELD_PREP(K210_PLL_CLKF, pll_cfg->f); |
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reg |= FIELD_PREP(K210_PLL_CLKOD, pll_cfg->od); |
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reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj); |
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reg |= K210_PLL_PWRD; |
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writel(reg, pll->reg); |
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/* |
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* Reset the PLL: ensure reset is low before asserting it. |
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* The magic NOPs come from the Kendryte reference SDK. |
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*/ |
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reg &= ~K210_PLL_RESET; |
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writel(reg, pll->reg); |
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reg |= K210_PLL_RESET; |
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writel(reg, pll->reg); |
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nop(); |
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nop(); |
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reg &= ~K210_PLL_RESET; |
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writel(reg, pll->reg); |
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k210_pll_wait_for_lock(pll); |
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reg &= ~K210_PLL_BYPASS; |
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reg |= K210_PLL_EN; |
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writel(reg, pll->reg); |
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if (pll->id == K210_PLL0) |
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k210_aclk_set_selector(regs, 1); |
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} |
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static int k210_pll_enable(struct clk_hw *hw) |
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{ |
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struct k210_pll *pll = to_k210_pll(hw); |
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struct k210_sysclk *ksc = pll->ksc; |
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unsigned long flags; |
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spin_lock_irqsave(&ksc->clk_lock, flags); |
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k210_pll_enable_hw(ksc->regs, pll); |
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spin_unlock_irqrestore(&ksc->clk_lock, flags); |
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return 0; |
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} |
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static void k210_pll_disable(struct clk_hw *hw) |
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{ |
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struct k210_pll *pll = to_k210_pll(hw); |
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struct k210_sysclk *ksc = pll->ksc; |
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unsigned long flags; |
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u32 reg; |
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/* |
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* Bypassing before powering off is important so child clocks do not |
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* stop working. This is especially important for pll0, the indirect |
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* parent of the cpu clock. |
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*/ |
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spin_lock_irqsave(&ksc->clk_lock, flags); |
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reg = readl(pll->reg); |
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reg |= K210_PLL_BYPASS; |
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writel(reg, pll->reg); |
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reg &= ~K210_PLL_PWRD; |
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reg &= ~K210_PLL_EN; |
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writel(reg, pll->reg); |
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spin_unlock_irqrestore(&ksc->clk_lock, flags); |
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} |
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static int k210_pll_is_enabled(struct clk_hw *hw) |
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{ |
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return k210_pll_hw_is_enabled(to_k210_pll(hw)); |
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} |
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static unsigned long k210_pll_get_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct k210_pll *pll = to_k210_pll(hw); |
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u32 reg = readl(pll->reg); |
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u32 r, f, od; |
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if (reg & K210_PLL_BYPASS) |
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return parent_rate; |
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if (!(reg & K210_PLL_PWRD)) |
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return 0; |
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r = FIELD_GET(K210_PLL_CLKR, reg) + 1; |
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f = FIELD_GET(K210_PLL_CLKF, reg) + 1; |
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od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; |
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return (u64)parent_rate * f / (r * od); |
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} |
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static const struct clk_ops k210_pll_ops = { |
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.enable = k210_pll_enable, |
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.disable = k210_pll_disable, |
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.is_enabled = k210_pll_is_enabled, |
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.recalc_rate = k210_pll_get_rate, |
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}; |
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static int k210_pll2_set_parent(struct clk_hw *hw, u8 index) |
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{ |
|
struct k210_pll *pll = to_k210_pll(hw); |
|
struct k210_sysclk *ksc = pll->ksc; |
|
unsigned long flags; |
|
u32 reg; |
|
|
|
spin_lock_irqsave(&ksc->clk_lock, flags); |
|
|
|
reg = readl(pll->reg); |
|
reg &= ~K210_PLL_SEL; |
|
reg |= FIELD_PREP(K210_PLL_SEL, index); |
|
writel(reg, pll->reg); |
|
|
|
spin_unlock_irqrestore(&ksc->clk_lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static u8 k210_pll2_get_parent(struct clk_hw *hw) |
|
{ |
|
struct k210_pll *pll = to_k210_pll(hw); |
|
u32 reg = readl(pll->reg); |
|
|
|
return FIELD_GET(K210_PLL_SEL, reg); |
|
} |
|
|
|
static const struct clk_ops k210_pll2_ops = { |
|
.enable = k210_pll_enable, |
|
.disable = k210_pll_disable, |
|
.is_enabled = k210_pll_is_enabled, |
|
.recalc_rate = k210_pll_get_rate, |
|
.set_parent = k210_pll2_set_parent, |
|
.get_parent = k210_pll2_get_parent, |
|
}; |
|
|
|
static int __init k210_register_pll(struct device_node *np, |
|
struct k210_sysclk *ksc, |
|
enum k210_pll_id pllid, const char *name, |
|
int num_parents, const struct clk_ops *ops) |
|
{ |
|
struct k210_pll *pll = &ksc->plls[pllid]; |
|
struct clk_init_data init = {}; |
|
const struct clk_parent_data parent_data[] = { |
|
{ /* .index = 0 for in0 */ }, |
|
{ .hw = &ksc->plls[K210_PLL0].hw }, |
|
{ .hw = &ksc->plls[K210_PLL1].hw }, |
|
}; |
|
|
|
init.name = name; |
|
init.parent_data = parent_data; |
|
init.num_parents = num_parents; |
|
init.ops = ops; |
|
|
|
pll->hw.init = &init; |
|
pll->ksc = ksc; |
|
|
|
return of_clk_hw_register(np, &pll->hw); |
|
} |
|
|
|
static int __init k210_register_plls(struct device_node *np, |
|
struct k210_sysclk *ksc) |
|
{ |
|
int i, ret; |
|
|
|
for (i = 0; i < K210_PLL_NUM; i++) |
|
k210_init_pll(ksc->regs, i, &ksc->plls[i]); |
|
|
|
/* PLL0 and PLL1 only have IN0 as parent */ |
|
ret = k210_register_pll(np, ksc, K210_PLL0, "pll0", 1, &k210_pll_ops); |
|
if (ret) { |
|
pr_err("%pOFP: register PLL0 failed\n", np); |
|
return ret; |
|
} |
|
ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops); |
|
if (ret) { |
|
pr_err("%pOFP: register PLL1 failed\n", np); |
|
return ret; |
|
} |
|
|
|
/* PLL2 has IN0, PLL0 and PLL1 as parents */ |
|
ret = k210_register_pll(np, ksc, K210_PLL2, "pll2", 3, &k210_pll2_ops); |
|
if (ret) { |
|
pr_err("%pOFP: register PLL2 failed\n", np); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int k210_aclk_set_parent(struct clk_hw *hw, u8 index) |
|
{ |
|
struct k210_sysclk *ksc = to_k210_sysclk(hw); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&ksc->clk_lock, flags); |
|
|
|
k210_aclk_set_selector(ksc->regs, index); |
|
|
|
spin_unlock_irqrestore(&ksc->clk_lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static u8 k210_aclk_get_parent(struct clk_hw *hw) |
|
{ |
|
struct k210_sysclk *ksc = to_k210_sysclk(hw); |
|
u32 sel; |
|
|
|
sel = readl(ksc->regs + K210_SYSCTL_SEL0) & K210_ACLK_SEL; |
|
|
|
return sel ? 1 : 0; |
|
} |
|
|
|
static unsigned long k210_aclk_get_rate(struct clk_hw *hw, |
|
unsigned long parent_rate) |
|
{ |
|
struct k210_sysclk *ksc = to_k210_sysclk(hw); |
|
u32 reg = readl(ksc->regs + K210_SYSCTL_SEL0); |
|
unsigned int shift; |
|
|
|
if (!(reg & 0x1)) |
|
return parent_rate; |
|
|
|
shift = FIELD_GET(K210_ACLK_DIV, reg); |
|
|
|
return parent_rate / (2UL << shift); |
|
} |
|
|
|
static const struct clk_ops k210_aclk_ops = { |
|
.set_parent = k210_aclk_set_parent, |
|
.get_parent = k210_aclk_get_parent, |
|
.recalc_rate = k210_aclk_get_rate, |
|
}; |
|
|
|
/* |
|
* ACLK has IN0 and PLL0 as parents. |
|
*/ |
|
static int __init k210_register_aclk(struct device_node *np, |
|
struct k210_sysclk *ksc) |
|
{ |
|
struct clk_init_data init = {}; |
|
const struct clk_parent_data parent_data[] = { |
|
{ /* .index = 0 for in0 */ }, |
|
{ .hw = &ksc->plls[K210_PLL0].hw }, |
|
}; |
|
int ret; |
|
|
|
init.name = "aclk"; |
|
init.parent_data = parent_data; |
|
init.num_parents = 2; |
|
init.ops = &k210_aclk_ops; |
|
ksc->aclk.init = &init; |
|
|
|
ret = of_clk_hw_register(np, &ksc->aclk); |
|
if (ret) { |
|
pr_err("%pOFP: register aclk failed\n", np); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
#define to_k210_clk(_hw) container_of(_hw, struct k210_clk, hw) |
|
|
|
static int k210_clk_enable(struct clk_hw *hw) |
|
{ |
|
struct k210_clk *kclk = to_k210_clk(hw); |
|
struct k210_sysclk *ksc = kclk->ksc; |
|
struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id]; |
|
unsigned long flags; |
|
u32 reg; |
|
|
|
if (!cfg->gate_reg) |
|
return 0; |
|
|
|
spin_lock_irqsave(&ksc->clk_lock, flags); |
|
reg = readl(ksc->regs + cfg->gate_reg); |
|
reg |= BIT(cfg->gate_bit); |
|
writel(reg, ksc->regs + cfg->gate_reg); |
|
spin_unlock_irqrestore(&ksc->clk_lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static void k210_clk_disable(struct clk_hw *hw) |
|
{ |
|
struct k210_clk *kclk = to_k210_clk(hw); |
|
struct k210_sysclk *ksc = kclk->ksc; |
|
struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id]; |
|
unsigned long flags; |
|
u32 reg; |
|
|
|
if (!cfg->gate_reg) |
|
return; |
|
|
|
spin_lock_irqsave(&ksc->clk_lock, flags); |
|
reg = readl(ksc->regs + cfg->gate_reg); |
|
reg &= ~BIT(cfg->gate_bit); |
|
writel(reg, ksc->regs + cfg->gate_reg); |
|
spin_unlock_irqrestore(&ksc->clk_lock, flags); |
|
} |
|
|
|
static int k210_clk_set_parent(struct clk_hw *hw, u8 index) |
|
{ |
|
struct k210_clk *kclk = to_k210_clk(hw); |
|
struct k210_sysclk *ksc = kclk->ksc; |
|
struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id]; |
|
unsigned long flags; |
|
u32 reg; |
|
|
|
spin_lock_irqsave(&ksc->clk_lock, flags); |
|
reg = readl(ksc->regs + cfg->mux_reg); |
|
if (index) |
|
reg |= BIT(cfg->mux_bit); |
|
else |
|
reg &= ~BIT(cfg->mux_bit); |
|
writel(reg, ksc->regs + cfg->mux_reg); |
|
spin_unlock_irqrestore(&ksc->clk_lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static u8 k210_clk_get_parent(struct clk_hw *hw) |
|
{ |
|
struct k210_clk *kclk = to_k210_clk(hw); |
|
struct k210_sysclk *ksc = kclk->ksc; |
|
struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id]; |
|
unsigned long flags; |
|
u32 reg, idx; |
|
|
|
spin_lock_irqsave(&ksc->clk_lock, flags); |
|
reg = readl(ksc->regs + cfg->mux_reg); |
|
idx = (reg & BIT(cfg->mux_bit)) ? 1 : 0; |
|
spin_unlock_irqrestore(&ksc->clk_lock, flags); |
|
|
|
return idx; |
|
} |
|
|
|
static unsigned long k210_clk_get_rate(struct clk_hw *hw, |
|
unsigned long parent_rate) |
|
{ |
|
struct k210_clk *kclk = to_k210_clk(hw); |
|
struct k210_sysclk *ksc = kclk->ksc; |
|
struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id]; |
|
u32 reg, div_val; |
|
|
|
if (!cfg->div_reg) |
|
return parent_rate; |
|
|
|
reg = readl(ksc->regs + cfg->div_reg); |
|
div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); |
|
|
|
switch (cfg->div_type) { |
|
case K210_DIV_ONE_BASED: |
|
return parent_rate / (div_val + 1); |
|
case K210_DIV_DOUBLE_ONE_BASED: |
|
return parent_rate / ((div_val + 1) * 2); |
|
case K210_DIV_POWER_OF_TWO: |
|
return parent_rate / (2UL << div_val); |
|
case K210_DIV_NONE: |
|
default: |
|
return 0; |
|
} |
|
} |
|
|
|
static const struct clk_ops k210_clk_mux_ops = { |
|
.enable = k210_clk_enable, |
|
.disable = k210_clk_disable, |
|
.set_parent = k210_clk_set_parent, |
|
.get_parent = k210_clk_get_parent, |
|
.recalc_rate = k210_clk_get_rate, |
|
}; |
|
|
|
static const struct clk_ops k210_clk_ops = { |
|
.enable = k210_clk_enable, |
|
.disable = k210_clk_disable, |
|
.recalc_rate = k210_clk_get_rate, |
|
}; |
|
|
|
static void __init k210_register_clk(struct device_node *np, |
|
struct k210_sysclk *ksc, int id, |
|
const struct clk_parent_data *parent_data, |
|
int num_parents, unsigned long flags) |
|
{ |
|
struct k210_clk *kclk = &ksc->clks[id]; |
|
struct clk_init_data init = {}; |
|
int ret; |
|
|
|
init.name = k210_clk_cfgs[id].name; |
|
init.flags = flags; |
|
init.parent_data = parent_data; |
|
init.num_parents = num_parents; |
|
if (num_parents > 1) |
|
init.ops = &k210_clk_mux_ops; |
|
else |
|
init.ops = &k210_clk_ops; |
|
|
|
kclk->id = id; |
|
kclk->ksc = ksc; |
|
kclk->hw.init = &init; |
|
|
|
ret = of_clk_hw_register(np, &kclk->hw); |
|
if (ret) { |
|
pr_err("%pOFP: register clock %s failed\n", |
|
np, k210_clk_cfgs[id].name); |
|
kclk->id = -1; |
|
} |
|
} |
|
|
|
/* |
|
* All muxed clocks have IN0 and PLL0 as parents. |
|
*/ |
|
static inline void __init k210_register_mux_clk(struct device_node *np, |
|
struct k210_sysclk *ksc, int id) |
|
{ |
|
const struct clk_parent_data parent_data[2] = { |
|
{ /* .index = 0 for in0 */ }, |
|
{ .hw = &ksc->plls[K210_PLL0].hw } |
|
}; |
|
|
|
k210_register_clk(np, ksc, id, parent_data, 2, 0); |
|
} |
|
|
|
static inline void __init k210_register_in0_child(struct device_node *np, |
|
struct k210_sysclk *ksc, int id) |
|
{ |
|
const struct clk_parent_data parent_data = { |
|
/* .index = 0 for in0 */ |
|
}; |
|
|
|
k210_register_clk(np, ksc, id, &parent_data, 1, 0); |
|
} |
|
|
|
static inline void __init k210_register_pll_child(struct device_node *np, |
|
struct k210_sysclk *ksc, int id, |
|
enum k210_pll_id pllid, |
|
unsigned long flags) |
|
{ |
|
const struct clk_parent_data parent_data = { |
|
.hw = &ksc->plls[pllid].hw, |
|
}; |
|
|
|
k210_register_clk(np, ksc, id, &parent_data, 1, flags); |
|
} |
|
|
|
static inline void __init k210_register_aclk_child(struct device_node *np, |
|
struct k210_sysclk *ksc, int id, |
|
unsigned long flags) |
|
{ |
|
const struct clk_parent_data parent_data = { |
|
.hw = &ksc->aclk, |
|
}; |
|
|
|
k210_register_clk(np, ksc, id, &parent_data, 1, flags); |
|
} |
|
|
|
static inline void __init k210_register_clk_child(struct device_node *np, |
|
struct k210_sysclk *ksc, int id, |
|
int parent_id) |
|
{ |
|
const struct clk_parent_data parent_data = { |
|
.hw = &ksc->clks[parent_id].hw, |
|
}; |
|
|
|
k210_register_clk(np, ksc, id, &parent_data, 1, 0); |
|
} |
|
|
|
static struct clk_hw *k210_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
|
void *data) |
|
{ |
|
struct k210_sysclk *ksc = data; |
|
unsigned int idx = clkspec->args[0]; |
|
|
|
if (idx >= K210_NUM_CLKS) |
|
return ERR_PTR(-EINVAL); |
|
|
|
return &ksc->clks[idx].hw; |
|
} |
|
|
|
static void __init k210_clk_init(struct device_node *np) |
|
{ |
|
struct device_node *sysctl_np; |
|
struct k210_sysclk *ksc; |
|
int i, ret; |
|
|
|
ksc = kzalloc(sizeof(*ksc), GFP_KERNEL); |
|
if (!ksc) |
|
return; |
|
|
|
spin_lock_init(&ksc->clk_lock); |
|
sysctl_np = of_get_parent(np); |
|
ksc->regs = of_iomap(sysctl_np, 0); |
|
of_node_put(sysctl_np); |
|
if (!ksc->regs) { |
|
pr_err("%pOFP: failed to map registers\n", np); |
|
return; |
|
} |
|
|
|
ret = k210_register_plls(np, ksc); |
|
if (ret) |
|
return; |
|
|
|
ret = k210_register_aclk(np, ksc); |
|
if (ret) |
|
return; |
|
|
|
/* |
|
* Critical clocks: there are no consumers of the SRAM clocks, |
|
* including the AI clock for the third SRAM bank. The CPU clock |
|
* is only referenced by the uarths serial device and so would be |
|
* disabled if the serial console is disabled to switch to another |
|
* console. Mark all these clocks as critical so that they are never |
|
* disabled by the core clock management. |
|
*/ |
|
k210_register_aclk_child(np, ksc, K210_CLK_CPU, CLK_IS_CRITICAL); |
|
k210_register_aclk_child(np, ksc, K210_CLK_SRAM0, CLK_IS_CRITICAL); |
|
k210_register_aclk_child(np, ksc, K210_CLK_SRAM1, CLK_IS_CRITICAL); |
|
k210_register_pll_child(np, ksc, K210_CLK_AI, K210_PLL1, |
|
CLK_IS_CRITICAL); |
|
|
|
/* Clocks with aclk as source */ |
|
k210_register_aclk_child(np, ksc, K210_CLK_DMA, 0); |
|
k210_register_aclk_child(np, ksc, K210_CLK_FFT, 0); |
|
k210_register_aclk_child(np, ksc, K210_CLK_ROM, 0); |
|
k210_register_aclk_child(np, ksc, K210_CLK_DVP, 0); |
|
k210_register_aclk_child(np, ksc, K210_CLK_APB0, 0); |
|
k210_register_aclk_child(np, ksc, K210_CLK_APB1, 0); |
|
k210_register_aclk_child(np, ksc, K210_CLK_APB2, 0); |
|
|
|
/* Clocks with PLL0 as source */ |
|
k210_register_pll_child(np, ksc, K210_CLK_SPI0, K210_PLL0, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_SPI1, K210_PLL0, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_SPI2, K210_PLL0, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2C0, K210_PLL0, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2C1, K210_PLL0, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2C2, K210_PLL0, 0); |
|
|
|
/* Clocks with PLL2 as source */ |
|
k210_register_pll_child(np, ksc, K210_CLK_I2S0, K210_PLL2, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2S1, K210_PLL2, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2S2, K210_PLL2, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2S0_M, K210_PLL2, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2S1_M, K210_PLL2, 0); |
|
k210_register_pll_child(np, ksc, K210_CLK_I2S2_M, K210_PLL2, 0); |
|
|
|
/* Clocks with IN0 as source */ |
|
k210_register_in0_child(np, ksc, K210_CLK_WDT0); |
|
k210_register_in0_child(np, ksc, K210_CLK_WDT1); |
|
k210_register_in0_child(np, ksc, K210_CLK_RTC); |
|
|
|
/* Clocks with APB0 as source */ |
|
k210_register_clk_child(np, ksc, K210_CLK_GPIO, K210_CLK_APB0); |
|
k210_register_clk_child(np, ksc, K210_CLK_UART1, K210_CLK_APB0); |
|
k210_register_clk_child(np, ksc, K210_CLK_UART2, K210_CLK_APB0); |
|
k210_register_clk_child(np, ksc, K210_CLK_UART3, K210_CLK_APB0); |
|
k210_register_clk_child(np, ksc, K210_CLK_FPIOA, K210_CLK_APB0); |
|
k210_register_clk_child(np, ksc, K210_CLK_SHA, K210_CLK_APB0); |
|
|
|
/* Clocks with APB1 as source */ |
|
k210_register_clk_child(np, ksc, K210_CLK_AES, K210_CLK_APB1); |
|
k210_register_clk_child(np, ksc, K210_CLK_OTP, K210_CLK_APB1); |
|
|
|
/* Mux clocks with in0 or pll0 as source */ |
|
k210_register_mux_clk(np, ksc, K210_CLK_SPI3); |
|
k210_register_mux_clk(np, ksc, K210_CLK_TIMER0); |
|
k210_register_mux_clk(np, ksc, K210_CLK_TIMER1); |
|
k210_register_mux_clk(np, ksc, K210_CLK_TIMER2); |
|
|
|
/* Check for registration errors */ |
|
for (i = 0; i < K210_NUM_CLKS; i++) { |
|
if (ksc->clks[i].id != i) |
|
return; |
|
} |
|
|
|
ret = of_clk_add_hw_provider(np, k210_clk_hw_onecell_get, ksc); |
|
if (ret) { |
|
pr_err("%pOFP: add clock provider failed %d\n", np, ret); |
|
return; |
|
} |
|
|
|
pr_info("%pOFP: CPU running at %lu MHz\n", |
|
np, clk_hw_get_rate(&ksc->clks[K210_CLK_CPU].hw) / 1000000); |
|
} |
|
|
|
CLK_OF_DECLARE(k210_clk, "canaan,k210-clk", k210_clk_init); |
|
|
|
/* |
|
* Enable PLL1 to be able to use the AI SRAM. |
|
*/ |
|
void __init k210_clk_early_init(void __iomem *regs) |
|
{ |
|
struct k210_pll pll1; |
|
|
|
/* Make sure ACLK selector is set to PLL0 */ |
|
k210_aclk_set_selector(regs, 1); |
|
|
|
/* Startup PLL1 to enable the aisram bank for general memory use */ |
|
k210_init_pll(regs, K210_PLL1, &pll1); |
|
k210_pll_enable_hw(regs, &pll1); |
|
}
|
|
|