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283 lines
7.5 KiB
283 lines
7.5 KiB
/* |
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* Copyright (C) 2014 Broadcom Corporation |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/clkdev.h> |
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#include <linux/of_address.h> |
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#include "clk-iproc.h" |
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#define IPROC_CLK_MAX_FREQ_POLICY 0x3 |
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#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008 |
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#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8 |
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#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7 |
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#define IPROC_CLK_PLLARMA_OFFSET 0xc00 |
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#define IPROC_CLK_PLLARMA_LOCK_SHIFT 28 |
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#define IPROC_CLK_PLLARMA_PDIV_SHIFT 24 |
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#define IPROC_CLK_PLLARMA_PDIV_MASK 0xf |
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#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8 |
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#define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff |
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#define IPROC_CLK_PLLARMB_OFFSET 0xc04 |
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#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff |
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#define IPROC_CLK_PLLARMC_OFFSET 0xc08 |
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#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8 |
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#define IPROC_CLK_PLLARMC_MDIV_MASK 0xff |
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#define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20 |
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#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff |
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#define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24 |
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#define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29 |
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#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20 |
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#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff |
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#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff |
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#define IPROC_CLK_ARM_DIV_OFFSET 0xe00 |
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#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4 |
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#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf |
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#define IPROC_CLK_POLICY_DBG_OFFSET 0xec0 |
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#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12 |
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#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7 |
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enum iproc_arm_pll_fid { |
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ARM_PLL_FID_CRYSTAL_CLK = 0, |
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ARM_PLL_FID_SYS_CLK = 2, |
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ARM_PLL_FID_CH0_SLOW_CLK = 6, |
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ARM_PLL_FID_CH1_FAST_CLK = 7 |
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}; |
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struct iproc_arm_pll { |
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struct clk_hw hw; |
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void __iomem *base; |
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unsigned long rate; |
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}; |
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#define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw) |
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static unsigned int __get_fid(struct iproc_arm_pll *pll) |
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{ |
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u32 val; |
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unsigned int policy, fid, active_fid; |
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val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); |
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if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT)) |
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policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK; |
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else |
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policy = 0; |
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/* something is seriously wrong */ |
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BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY); |
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val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); |
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fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) & |
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IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK; |
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val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); |
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active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK & |
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(val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT); |
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if (fid != active_fid) { |
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pr_debug("%s: fid override %u->%u\n", __func__, fid, |
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active_fid); |
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fid = active_fid; |
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} |
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pr_debug("%s: active fid: %u\n", __func__, fid); |
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return fid; |
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} |
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/* |
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* Determine the mdiv (post divider) based on the frequency ID being used. |
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* There are 4 sources that can be used to derive the output clock rate: |
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* - 25 MHz Crystal |
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* - System clock |
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* - PLL channel 0 (slow clock) |
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* - PLL channel 1 (fast clock) |
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*/ |
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static int __get_mdiv(struct iproc_arm_pll *pll) |
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{ |
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unsigned int fid; |
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int mdiv; |
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u32 val; |
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fid = __get_fid(pll); |
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switch (fid) { |
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case ARM_PLL_FID_CRYSTAL_CLK: |
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case ARM_PLL_FID_SYS_CLK: |
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mdiv = 1; |
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break; |
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case ARM_PLL_FID_CH0_SLOW_CLK: |
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val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); |
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mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; |
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if (mdiv == 0) |
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mdiv = 256; |
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break; |
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case ARM_PLL_FID_CH1_FAST_CLK: |
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val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); |
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mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; |
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if (mdiv == 0) |
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mdiv = 256; |
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break; |
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default: |
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mdiv = -EFAULT; |
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} |
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return mdiv; |
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} |
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static unsigned int __get_ndiv(struct iproc_arm_pll *pll) |
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{ |
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u32 val; |
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unsigned int ndiv_int, ndiv_frac, ndiv; |
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val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); |
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if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) { |
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/* |
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* offset mode is active. Read the ndiv from the PLLARM OFFSET |
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* register |
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*/ |
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ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) & |
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IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK; |
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if (ndiv_int == 0) |
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ndiv_int = 256; |
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ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK; |
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} else { |
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/* offset mode not active */ |
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val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); |
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ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) & |
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IPROC_CLK_PLLARMA_NDIV_INT_MASK; |
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if (ndiv_int == 0) |
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ndiv_int = 1024; |
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val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET); |
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ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK; |
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} |
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ndiv = (ndiv_int << 20) | ndiv_frac; |
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return ndiv; |
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} |
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/* |
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* The output frequency of the ARM PLL is calculated based on the ARM PLL |
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* divider values: |
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* pdiv = ARM PLL pre-divider |
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* ndiv = ARM PLL multiplier |
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* mdiv = ARM PLL post divider |
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* |
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* The frequency is calculated by: |
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* ((ndiv * parent clock rate) / pdiv) / mdiv |
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*/ |
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static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct iproc_arm_pll *pll = to_iproc_arm_pll(hw); |
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u32 val; |
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int mdiv; |
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u64 ndiv; |
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unsigned int pdiv; |
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/* in bypass mode, use parent rate */ |
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val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); |
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if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) { |
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pll->rate = parent_rate; |
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return pll->rate; |
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} |
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/* PLL needs to be locked */ |
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val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); |
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if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) { |
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pll->rate = 0; |
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return 0; |
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} |
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pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) & |
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IPROC_CLK_PLLARMA_PDIV_MASK; |
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if (pdiv == 0) |
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pdiv = 16; |
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ndiv = __get_ndiv(pll); |
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mdiv = __get_mdiv(pll); |
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if (mdiv <= 0) { |
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pll->rate = 0; |
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return 0; |
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} |
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pll->rate = (ndiv * parent_rate) >> 20; |
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pll->rate = (pll->rate / pdiv) / mdiv; |
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pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__, |
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pll->rate, parent_rate); |
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pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__, |
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(unsigned int)(ndiv >> 20), pdiv, mdiv); |
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return pll->rate; |
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} |
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static const struct clk_ops iproc_arm_pll_ops = { |
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.recalc_rate = iproc_arm_pll_recalc_rate, |
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}; |
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void __init iproc_armpll_setup(struct device_node *node) |
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{ |
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int ret; |
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struct iproc_arm_pll *pll; |
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struct clk_init_data init; |
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const char *parent_name; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (WARN_ON(!pll)) |
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return; |
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pll->base = of_iomap(node, 0); |
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if (WARN_ON(!pll->base)) |
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goto err_free_pll; |
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init.name = node->name; |
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init.ops = &iproc_arm_pll_ops; |
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init.flags = 0; |
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parent_name = of_clk_get_parent_name(node, 0); |
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init.parent_names = (parent_name ? &parent_name : NULL); |
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init.num_parents = (parent_name ? 1 : 0); |
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pll->hw.init = &init; |
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ret = clk_hw_register(NULL, &pll->hw); |
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if (WARN_ON(ret)) |
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goto err_iounmap; |
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ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw); |
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if (WARN_ON(ret)) |
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goto err_clk_unregister; |
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return; |
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err_clk_unregister: |
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clk_hw_unregister(&pll->hw); |
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err_iounmap: |
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iounmap(pll->base); |
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err_free_pll: |
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kfree(pll); |
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}
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