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376 lines
11 KiB
376 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/clk-provider.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/clock/at91.h> |
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#include "pmc.h" |
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static DEFINE_SPINLOCK(mck_lock); |
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static const struct clk_master_characteristics mck_characteristics = { |
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.output = { .min = 124000000, .max = 166000000 }, |
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.divisors = { 1, 2, 4, 3 }, |
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}; |
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static u8 plla_out[] = { 0 }; |
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static u16 plla_icpll[] = { 0 }; |
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static const struct clk_range plla_outputs[] = { |
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{ .min = 600000000, .max = 1200000000 }, |
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}; |
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static const struct clk_pll_characteristics plla_characteristics = { |
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.input = { .min = 12000000, .max = 24000000 }, |
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.num_output = ARRAY_SIZE(plla_outputs), |
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.output = plla_outputs, |
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.icpll = plla_icpll, |
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.out = plla_out, |
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}; |
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static const struct clk_pcr_layout sama5d2_pcr_layout = { |
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.offset = 0x10c, |
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.cmd = BIT(12), |
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.gckcss_mask = GENMASK(10, 8), |
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.pid_mask = GENMASK(6, 0), |
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}; |
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static const struct { |
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char *n; |
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char *p; |
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u8 id; |
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} sama5d2_systemck[] = { |
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{ .n = "ddrck", .p = "masterck_div", .id = 2 }, |
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{ .n = "lcdck", .p = "masterck_div", .id = 3 }, |
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{ .n = "uhpck", .p = "usbck", .id = 6 }, |
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{ .n = "udpck", .p = "usbck", .id = 7 }, |
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{ .n = "pck0", .p = "prog0", .id = 8 }, |
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{ .n = "pck1", .p = "prog1", .id = 9 }, |
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{ .n = "pck2", .p = "prog2", .id = 10 }, |
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{ .n = "iscck", .p = "masterck_div", .id = 18 }, |
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}; |
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static const struct { |
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char *n; |
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u8 id; |
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struct clk_range r; |
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} sama5d2_periph32ck[] = { |
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{ .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "matrix1_clk", .id = 14, }, |
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{ .n = "hsmc_clk", .id = 17, }, |
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{ .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "securam_clk", .id = 51, }, |
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{ .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, }, |
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}; |
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static const struct { |
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char *n; |
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u8 id; |
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} sama5d2_periphck[] = { |
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{ .n = "dma0_clk", .id = 6, }, |
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{ .n = "dma1_clk", .id = 7, }, |
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{ .n = "aes_clk", .id = 9, }, |
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{ .n = "aesb_clk", .id = 10, }, |
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{ .n = "sha_clk", .id = 12, }, |
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{ .n = "mpddr_clk", .id = 13, }, |
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{ .n = "matrix0_clk", .id = 15, }, |
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{ .n = "sdmmc0_hclk", .id = 31, }, |
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{ .n = "sdmmc1_hclk", .id = 32, }, |
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{ .n = "lcdc_clk", .id = 45, }, |
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{ .n = "isc_clk", .id = 46, }, |
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{ .n = "qspi0_clk", .id = 52, }, |
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{ .n = "qspi1_clk", .id = 53, }, |
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}; |
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static const struct { |
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char *n; |
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u8 id; |
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struct clk_range r; |
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int chg_pid; |
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} sama5d2_gck[] = { |
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{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, }, |
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{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, }, |
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{ .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, |
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{ .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, }, |
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{ .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, }, |
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{ .n = "i2s0_gclk", .id = 54, .chg_pid = 5, }, |
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{ .n = "i2s1_gclk", .id = 55, .chg_pid = 5, }, |
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{ .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, }, |
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{ .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, }, |
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{ .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, }, |
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}; |
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static const struct clk_programmable_layout sama5d2_programmable_layout = { |
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.pres_mask = 0xff, |
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.pres_shift = 4, |
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.css_mask = 0x7, |
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.have_slck_mck = 0, |
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.is_pres_direct = 1, |
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}; |
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static void __init sama5d2_pmc_setup(struct device_node *np) |
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{ |
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struct clk_range range = CLK_RANGE(0, 0); |
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const char *slck_name, *mainxtal_name; |
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struct pmc_data *sama5d2_pmc; |
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const char *parent_names[6]; |
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struct regmap *regmap, *regmap_sfr; |
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struct clk_hw *hw; |
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int i; |
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bool bypass; |
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i = of_property_match_string(np, "clock-names", "slow_clk"); |
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if (i < 0) |
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return; |
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slck_name = of_clk_get_parent_name(np, i); |
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i = of_property_match_string(np, "clock-names", "main_xtal"); |
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if (i < 0) |
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return; |
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mainxtal_name = of_clk_get_parent_name(np, i); |
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regmap = device_node_to_regmap(np); |
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if (IS_ERR(regmap)) |
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return; |
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sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1, |
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nck(sama5d2_systemck), |
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nck(sama5d2_periph32ck), |
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nck(sama5d2_gck), 3); |
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if (!sama5d2_pmc) |
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return; |
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hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, |
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100000000); |
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if (IS_ERR(hw)) |
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goto err_free; |
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bypass = of_property_read_bool(np, "atmel,osc-bypass"); |
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hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, |
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bypass); |
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if (IS_ERR(hw)) |
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goto err_free; |
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parent_names[0] = "main_rc_osc"; |
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parent_names[1] = "main_osc"; |
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hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_MAIN] = hw; |
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hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, |
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&sama5d3_pll_layout, &plla_characteristics); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_PLLACK] = hw; |
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hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", |
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"mainck"); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", |
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"audiopll_fracck"); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", |
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"audiopll_fracck"); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw; |
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regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); |
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if (IS_ERR(regmap_sfr)) |
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regmap_sfr = NULL; |
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hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck"); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_UTMI] = hw; |
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parent_names[0] = slck_name; |
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parent_names[1] = "mainck"; |
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parent_names[2] = "plladivck"; |
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parent_names[3] = "utmick"; |
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, |
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parent_names, |
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&at91sam9x5_master_layout, |
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&mck_characteristics, &mck_lock, |
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CLK_SET_RATE_GATE, INT_MIN); |
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if (IS_ERR(hw)) |
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goto err_free; |
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hw = at91_clk_register_master_div(regmap, "masterck_div", |
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"masterck_pres", |
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&at91sam9x5_master_layout, |
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&mck_characteristics, &mck_lock, |
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CLK_SET_RATE_GATE); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_MCK] = hw; |
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hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_MCK2] = hw; |
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parent_names[0] = "plladivck"; |
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parent_names[1] = "utmick"; |
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hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); |
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if (IS_ERR(hw)) |
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goto err_free; |
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parent_names[0] = slck_name; |
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parent_names[1] = "mainck"; |
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parent_names[2] = "plladivck"; |
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parent_names[3] = "utmick"; |
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parent_names[4] = "masterck_div"; |
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parent_names[5] = "audiopll_pmcck"; |
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for (i = 0; i < 3; i++) { |
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char name[6]; |
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snprintf(name, sizeof(name), "prog%d", i); |
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hw = at91_clk_register_programmable(regmap, name, |
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parent_names, 6, i, |
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&sama5d2_programmable_layout, |
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NULL); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->pchws[i] = hw; |
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} |
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for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) { |
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hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n, |
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sama5d2_systemck[i].p, |
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sama5d2_systemck[i].id); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw; |
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} |
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for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) { |
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hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, |
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&sama5d2_pcr_layout, |
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sama5d2_periphck[i].n, |
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"masterck_div", |
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sama5d2_periphck[i].id, |
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&range, INT_MIN); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw; |
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} |
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for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) { |
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hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, |
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&sama5d2_pcr_layout, |
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sama5d2_periph32ck[i].n, |
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"h32mxck", |
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sama5d2_periph32ck[i].id, |
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&sama5d2_periph32ck[i].r, |
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INT_MIN); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw; |
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} |
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parent_names[0] = slck_name; |
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parent_names[1] = "mainck"; |
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parent_names[2] = "plladivck"; |
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parent_names[3] = "utmick"; |
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parent_names[4] = "masterck_div"; |
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parent_names[5] = "audiopll_pmcck"; |
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for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { |
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, |
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&sama5d2_pcr_layout, |
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sama5d2_gck[i].n, |
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parent_names, NULL, 6, |
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sama5d2_gck[i].id, |
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&sama5d2_gck[i].r, |
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sama5d2_gck[i].chg_pid); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw; |
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} |
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if (regmap_sfr) { |
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parent_names[0] = "i2s0_clk"; |
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parent_names[1] = "i2s0_gclk"; |
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hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", |
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parent_names, 2, 0); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_I2S0_MUX] = hw; |
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parent_names[0] = "i2s1_clk"; |
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parent_names[1] = "i2s1_gclk"; |
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hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk", |
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parent_names, 2, 1); |
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if (IS_ERR(hw)) |
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goto err_free; |
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sama5d2_pmc->chws[PMC_I2S1_MUX] = hw; |
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} |
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of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc); |
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return; |
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err_free: |
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kfree(sama5d2_pmc); |
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} |
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CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
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