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191 lines
5.2 KiB
191 lines
5.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_IA64_MMU_CONTEXT_H |
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#define _ASM_IA64_MMU_CONTEXT_H |
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/* |
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* Copyright (C) 1998-2002 Hewlett-Packard Co |
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* David Mosberger-Tang <[email protected]> |
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*/ |
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/* |
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* Routines to manage the allocation of task context numbers. Task context |
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* numbers are used to reduce or eliminate the need to perform TLB flushes |
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* due to context switches. Context numbers are implemented using ia-64 |
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* region ids. Since the IA-64 TLB does not consider the region number when |
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* performing a TLB lookup, we need to assign a unique region id to each |
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* region in a process. We use the least significant three bits in aregion |
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* id for this purpose. |
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*/ |
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#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */ |
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#define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61)) |
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# include <asm/page.h> |
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# ifndef __ASSEMBLY__ |
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#include <linux/compiler.h> |
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#include <linux/percpu.h> |
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#include <linux/sched.h> |
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#include <linux/mm_types.h> |
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#include <linux/spinlock.h> |
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#include <asm/processor.h> |
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#include <asm-generic/mm_hooks.h> |
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struct ia64_ctx { |
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spinlock_t lock; |
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unsigned int next; /* next context number to use */ |
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unsigned int limit; /* available free range */ |
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unsigned int max_ctx; /* max. context value supported by all CPUs */ |
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/* call wrap_mmu_context when next >= max */ |
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unsigned long *bitmap; /* bitmap size is max_ctx+1 */ |
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unsigned long *flushmap;/* pending rid to be flushed */ |
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}; |
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extern struct ia64_ctx ia64_ctx; |
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DECLARE_PER_CPU(u8, ia64_need_tlb_flush); |
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extern void mmu_context_init (void); |
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extern void wrap_mmu_context (struct mm_struct *mm); |
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/* |
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* When the context counter wraps around all TLBs need to be flushed because |
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* an old context number might have been reused. This is signalled by the |
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* ia64_need_tlb_flush per-CPU variable, which is checked in the routine |
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* below. Called by activate_mm(). <[email protected]> |
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*/ |
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static inline void |
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delayed_tlb_flush (void) |
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{ |
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extern void local_flush_tlb_all (void); |
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unsigned long flags; |
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if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) { |
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spin_lock_irqsave(&ia64_ctx.lock, flags); |
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if (__ia64_per_cpu_var(ia64_need_tlb_flush)) { |
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local_flush_tlb_all(); |
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__ia64_per_cpu_var(ia64_need_tlb_flush) = 0; |
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} |
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spin_unlock_irqrestore(&ia64_ctx.lock, flags); |
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} |
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} |
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static inline nv_mm_context_t |
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get_mmu_context (struct mm_struct *mm) |
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{ |
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unsigned long flags; |
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nv_mm_context_t context = mm->context; |
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if (likely(context)) |
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goto out; |
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spin_lock_irqsave(&ia64_ctx.lock, flags); |
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/* re-check, now that we've got the lock: */ |
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context = mm->context; |
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if (context == 0) { |
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cpumask_clear(mm_cpumask(mm)); |
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if (ia64_ctx.next >= ia64_ctx.limit) { |
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ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap, |
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ia64_ctx.max_ctx, ia64_ctx.next); |
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ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap, |
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ia64_ctx.max_ctx, ia64_ctx.next); |
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if (ia64_ctx.next >= ia64_ctx.max_ctx) |
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wrap_mmu_context(mm); |
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} |
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mm->context = context = ia64_ctx.next++; |
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__set_bit(context, ia64_ctx.bitmap); |
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} |
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spin_unlock_irqrestore(&ia64_ctx.lock, flags); |
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out: |
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/* |
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* Ensure we're not starting to use "context" before any old |
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* uses of it are gone from our TLB. |
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*/ |
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delayed_tlb_flush(); |
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return context; |
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} |
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/* |
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* Initialize context number to some sane value. MM is guaranteed to be a |
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* brand-new address-space, so no TLB flushing is needed, ever. |
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*/ |
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#define init_new_context init_new_context |
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static inline int |
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init_new_context (struct task_struct *p, struct mm_struct *mm) |
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{ |
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mm->context = 0; |
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return 0; |
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} |
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static inline void |
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reload_context (nv_mm_context_t context) |
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{ |
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unsigned long rid; |
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unsigned long rid_incr = 0; |
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unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4; |
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old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE)); |
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rid = context << 3; /* make space for encoding the region number */ |
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rid_incr = 1 << 8; |
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/* encode the region id, preferred page size, and VHPT enable bit: */ |
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rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1; |
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rr1 = rr0 + 1*rid_incr; |
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rr2 = rr0 + 2*rid_incr; |
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rr3 = rr0 + 3*rid_incr; |
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rr4 = rr0 + 4*rid_incr; |
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#ifdef CONFIG_HUGETLB_PAGE |
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rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc); |
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# if RGN_HPAGE != 4 |
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# error "reload_context assumes RGN_HPAGE is 4" |
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# endif |
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#endif |
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ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4); |
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ia64_srlz_i(); /* srlz.i implies srlz.d */ |
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} |
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/* |
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* Must be called with preemption off |
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*/ |
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static inline void |
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activate_context (struct mm_struct *mm) |
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{ |
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nv_mm_context_t context; |
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do { |
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context = get_mmu_context(mm); |
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if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) |
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); |
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reload_context(context); |
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/* |
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* in the unlikely event of a TLB-flush by another thread, |
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* redo the load. |
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*/ |
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} while (unlikely(context != mm->context)); |
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} |
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/* |
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* Switch from address space PREV to address space NEXT. |
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*/ |
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#define activate_mm activate_mm |
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static inline void |
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activate_mm (struct mm_struct *prev, struct mm_struct *next) |
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{ |
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/* |
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* We may get interrupts here, but that's OK because interrupt |
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* handlers cannot touch user-space. |
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*/ |
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ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd)); |
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activate_context(next); |
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} |
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#define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm) |
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#include <asm-generic/mmu_context.h> |
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# endif /* ! __ASSEMBLY__ */ |
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#endif /* _ASM_IA64_MMU_CONTEXT_H */
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