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999 lines
23 KiB
999 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* wm0010.c -- WM0010 DSP Driver |
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* |
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* Copyright 2012 Wolfson Microelectronics PLC. |
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* |
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* Authors: Mark Brown <[email protected]> |
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* Dimitris Papastamos <[email protected]> |
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* Scott Ling <[email protected]> |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqreturn.h> |
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#include <linux/init.h> |
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#include <linux/spi/spi.h> |
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#include <linux/firmware.h> |
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#include <linux/delay.h> |
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#include <linux/fs.h> |
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#include <linux/gpio.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/mutex.h> |
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#include <linux/workqueue.h> |
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|
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#include <sound/soc.h> |
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#include <sound/wm0010.h> |
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#define DEVICE_ID_WM0010 10 |
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|
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/* We only support v1 of the .dfw INFO record */ |
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#define INFO_VERSION 1 |
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|
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enum dfw_cmd { |
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DFW_CMD_FUSE = 0x01, |
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DFW_CMD_CODE_HDR, |
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DFW_CMD_CODE_DATA, |
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DFW_CMD_PLL, |
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DFW_CMD_INFO = 0xff |
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}; |
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struct dfw_binrec { |
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u8 command; |
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u32 length:24; |
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u32 address; |
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uint8_t data[]; |
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} __packed; |
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struct dfw_inforec { |
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u8 info_version; |
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u8 tool_major_version; |
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u8 tool_minor_version; |
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u8 dsp_target; |
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}; |
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struct dfw_pllrec { |
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u8 command; |
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u32 length:24; |
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u32 address; |
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u32 clkctrl1; |
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u32 clkctrl2; |
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u32 clkctrl3; |
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u32 ldetctrl; |
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u32 uart_div; |
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u32 spi_div; |
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} __packed; |
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|
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static struct pll_clock_map { |
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int max_sysclk; |
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int max_pll_spi_speed; |
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u32 pll_clkctrl1; |
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} pll_clock_map[] = { /* Dividers */ |
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{ 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ |
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{ 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ |
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{ 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ |
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{ 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ |
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{ 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ |
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{ 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ |
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}; |
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enum wm0010_state { |
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WM0010_POWER_OFF, |
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WM0010_OUT_OF_RESET, |
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WM0010_BOOTROM, |
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WM0010_STAGE2, |
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WM0010_FIRMWARE, |
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}; |
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struct wm0010_priv { |
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struct snd_soc_component *component; |
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struct mutex lock; |
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struct device *dev; |
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struct wm0010_pdata pdata; |
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int gpio_reset; |
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int gpio_reset_value; |
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struct regulator_bulk_data core_supplies[2]; |
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struct regulator *dbvdd; |
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int sysclk; |
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enum wm0010_state state; |
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bool boot_failed; |
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bool ready; |
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bool pll_running; |
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int max_spi_freq; |
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int board_max_spi_speed; |
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u32 pll_clkctrl1; |
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spinlock_t irq_lock; |
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int irq; |
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struct completion boot_completion; |
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}; |
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struct wm0010_spi_msg { |
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struct spi_message m; |
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struct spi_transfer t; |
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u8 *tx_buf; |
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u8 *rx_buf; |
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size_t len; |
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}; |
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static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { |
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SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), |
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}; |
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static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { |
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{ "SDI2 Capture", NULL, "SDI1 Playback" }, |
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{ "SDI1 Capture", NULL, "SDI2 Playback" }, |
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{ "SDI1 Capture", NULL, "CLKIN" }, |
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{ "SDI2 Capture", NULL, "CLKIN" }, |
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{ "SDI1 Playback", NULL, "CLKIN" }, |
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{ "SDI2 Playback", NULL, "CLKIN" }, |
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}; |
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static const char *wm0010_state_to_str(enum wm0010_state state) |
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{ |
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static const char * const state_to_str[] = { |
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"Power off", |
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"Out of reset", |
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"Boot ROM", |
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"Stage2", |
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"Firmware" |
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}; |
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if (state < 0 || state >= ARRAY_SIZE(state_to_str)) |
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return "null"; |
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return state_to_str[state]; |
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} |
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/* Called with wm0010->lock held */ |
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static void wm0010_halt(struct snd_soc_component *component) |
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{ |
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struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
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unsigned long flags; |
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enum wm0010_state state; |
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|
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/* Fetch the wm0010 state */ |
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spin_lock_irqsave(&wm0010->irq_lock, flags); |
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state = wm0010->state; |
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spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
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switch (state) { |
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case WM0010_POWER_OFF: |
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/* If there's nothing to do, bail out */ |
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return; |
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case WM0010_OUT_OF_RESET: |
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case WM0010_BOOTROM: |
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case WM0010_STAGE2: |
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case WM0010_FIRMWARE: |
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/* Remember to put chip back into reset */ |
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gpio_set_value_cansleep(wm0010->gpio_reset, |
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wm0010->gpio_reset_value); |
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/* Disable the regulators */ |
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regulator_disable(wm0010->dbvdd); |
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regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), |
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wm0010->core_supplies); |
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break; |
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} |
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spin_lock_irqsave(&wm0010->irq_lock, flags); |
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wm0010->state = WM0010_POWER_OFF; |
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spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
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} |
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struct wm0010_boot_xfer { |
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struct list_head list; |
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struct snd_soc_component *component; |
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struct completion *done; |
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struct spi_message m; |
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struct spi_transfer t; |
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}; |
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/* Called with wm0010->lock held */ |
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static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) |
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{ |
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enum wm0010_state state; |
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unsigned long flags; |
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spin_lock_irqsave(&wm0010->irq_lock, flags); |
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state = wm0010->state; |
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spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
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dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", |
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wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); |
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wm0010->boot_failed = true; |
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} |
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static void wm0010_boot_xfer_complete(void *data) |
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{ |
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struct wm0010_boot_xfer *xfer = data; |
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struct snd_soc_component *component = xfer->component; |
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struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
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u32 *out32 = xfer->t.rx_buf; |
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int i; |
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if (xfer->m.status != 0) { |
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dev_err(component->dev, "SPI transfer failed: %d\n", |
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xfer->m.status); |
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wm0010_mark_boot_failure(wm0010); |
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if (xfer->done) |
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complete(xfer->done); |
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return; |
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} |
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for (i = 0; i < xfer->t.len / 4; i++) { |
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dev_dbg(component->dev, "%d: %04x\n", i, out32[i]); |
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|
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switch (be32_to_cpu(out32[i])) { |
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case 0xe0e0e0e0: |
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dev_err(component->dev, |
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"%d: ROM error reported in stage 2\n", i); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x55555555: |
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if (wm0010->state < WM0010_STAGE2) |
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break; |
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dev_err(component->dev, |
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"%d: ROM bootloader running in stage 2\n", i); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0000: |
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dev_dbg(component->dev, "Stage2 loader running\n"); |
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break; |
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case 0x0fed0007: |
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dev_dbg(component->dev, "CODE_HDR packet received\n"); |
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break; |
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case 0x0fed0008: |
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dev_dbg(component->dev, "CODE_DATA packet received\n"); |
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break; |
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case 0x0fed0009: |
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dev_dbg(component->dev, "Download complete\n"); |
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break; |
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case 0x0fed000c: |
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dev_dbg(component->dev, "Application start\n"); |
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break; |
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case 0x0fed000e: |
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dev_dbg(component->dev, "PLL packet received\n"); |
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wm0010->pll_running = true; |
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break; |
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case 0x0fed0025: |
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dev_err(component->dev, "Device reports image too long\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed002c: |
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dev_err(component->dev, "Device reports bad SPI packet\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0031: |
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dev_err(component->dev, "Device reports SPI read overflow\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0032: |
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dev_err(component->dev, "Device reports SPI underclock\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0033: |
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dev_err(component->dev, "Device reports bad header packet\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0034: |
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dev_err(component->dev, "Device reports invalid packet type\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0035: |
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dev_err(component->dev, "Device reports data before header error\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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case 0x0fed0038: |
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dev_err(component->dev, "Device reports invalid PLL packet\n"); |
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break; |
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case 0x0fed003a: |
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dev_err(component->dev, "Device reports packet alignment error\n"); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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default: |
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dev_err(component->dev, "Unrecognised return 0x%x\n", |
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be32_to_cpu(out32[i])); |
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wm0010_mark_boot_failure(wm0010); |
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break; |
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} |
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if (wm0010->boot_failed) |
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break; |
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} |
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if (xfer->done) |
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complete(xfer->done); |
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} |
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static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) |
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{ |
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int i; |
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for (i = 0; i < len / 8; i++) |
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data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); |
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} |
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static int wm0010_firmware_load(const char *name, struct snd_soc_component *component) |
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{ |
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struct spi_device *spi = to_spi_device(component->dev); |
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struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
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struct list_head xfer_list; |
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struct wm0010_boot_xfer *xfer; |
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int ret; |
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DECLARE_COMPLETION_ONSTACK(done); |
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const struct firmware *fw; |
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const struct dfw_binrec *rec; |
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const struct dfw_inforec *inforec; |
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u64 *img; |
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u8 *out, dsp; |
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u32 len, offset; |
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INIT_LIST_HEAD(&xfer_list); |
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ret = request_firmware(&fw, name, component->dev); |
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if (ret != 0) { |
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dev_err(component->dev, "Failed to request application(%s): %d\n", |
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name, ret); |
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return ret; |
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} |
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rec = (const struct dfw_binrec *)fw->data; |
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inforec = (const struct dfw_inforec *)rec->data; |
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offset = 0; |
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dsp = inforec->dsp_target; |
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wm0010->boot_failed = false; |
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if (WARN_ON(!list_empty(&xfer_list))) |
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return -EINVAL; |
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/* First record should be INFO */ |
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if (rec->command != DFW_CMD_INFO) { |
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dev_err(component->dev, "First record not INFO\r\n"); |
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ret = -EINVAL; |
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goto abort; |
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} |
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if (inforec->info_version != INFO_VERSION) { |
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dev_err(component->dev, |
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"Unsupported version (%02d) of INFO record\r\n", |
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inforec->info_version); |
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ret = -EINVAL; |
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goto abort; |
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} |
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dev_dbg(component->dev, "Version v%02d INFO record found\r\n", |
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inforec->info_version); |
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/* Check it's a DSP file */ |
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if (dsp != DEVICE_ID_WM0010) { |
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dev_err(component->dev, "Not a WM0010 firmware file.\r\n"); |
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ret = -EINVAL; |
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goto abort; |
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} |
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/* Skip the info record as we don't need to send it */ |
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offset += ((rec->length) + 8); |
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rec = (void *)&rec->data[rec->length]; |
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while (offset < fw->size) { |
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dev_dbg(component->dev, |
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"Packet: command %d, data length = 0x%x\r\n", |
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rec->command, rec->length); |
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len = rec->length + 8; |
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xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); |
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if (!xfer) { |
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ret = -ENOMEM; |
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goto abort; |
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} |
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xfer->component = component; |
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list_add_tail(&xfer->list, &xfer_list); |
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out = kzalloc(len, GFP_KERNEL | GFP_DMA); |
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if (!out) { |
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ret = -ENOMEM; |
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goto abort1; |
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} |
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xfer->t.rx_buf = out; |
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img = kzalloc(len, GFP_KERNEL | GFP_DMA); |
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if (!img) { |
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ret = -ENOMEM; |
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goto abort1; |
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} |
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xfer->t.tx_buf = img; |
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byte_swap_64((u64 *)&rec->command, img, len); |
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spi_message_init(&xfer->m); |
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xfer->m.complete = wm0010_boot_xfer_complete; |
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xfer->m.context = xfer; |
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xfer->t.len = len; |
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xfer->t.bits_per_word = 8; |
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if (!wm0010->pll_running) { |
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xfer->t.speed_hz = wm0010->sysclk / 6; |
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} else { |
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xfer->t.speed_hz = wm0010->max_spi_freq; |
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|
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if (wm0010->board_max_spi_speed && |
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(wm0010->board_max_spi_speed < wm0010->max_spi_freq)) |
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xfer->t.speed_hz = wm0010->board_max_spi_speed; |
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} |
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/* Store max usable spi frequency for later use */ |
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wm0010->max_spi_freq = xfer->t.speed_hz; |
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spi_message_add_tail(&xfer->t, &xfer->m); |
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offset += ((rec->length) + 8); |
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rec = (void *)&rec->data[rec->length]; |
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if (offset >= fw->size) { |
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dev_dbg(component->dev, "All transfers scheduled\n"); |
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xfer->done = &done; |
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} |
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ret = spi_async(spi, &xfer->m); |
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if (ret != 0) { |
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dev_err(component->dev, "Write failed: %d\n", ret); |
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goto abort1; |
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} |
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if (wm0010->boot_failed) { |
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dev_dbg(component->dev, "Boot fail!\n"); |
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ret = -EINVAL; |
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goto abort1; |
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} |
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} |
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wait_for_completion(&done); |
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ret = 0; |
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abort1: |
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while (!list_empty(&xfer_list)) { |
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xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, |
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list); |
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kfree(xfer->t.rx_buf); |
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kfree(xfer->t.tx_buf); |
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list_del(&xfer->list); |
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kfree(xfer); |
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} |
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abort: |
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release_firmware(fw); |
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return ret; |
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} |
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static int wm0010_stage2_load(struct snd_soc_component *component) |
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{ |
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struct spi_device *spi = to_spi_device(component->dev); |
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struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
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const struct firmware *fw; |
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struct spi_message m; |
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struct spi_transfer t; |
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u32 *img; |
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u8 *out; |
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int i; |
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int ret = 0; |
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ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev); |
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if (ret != 0) { |
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dev_err(component->dev, "Failed to request stage2 loader: %d\n", |
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ret); |
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return ret; |
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} |
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dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size); |
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|
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/* Copy to local buffer first as vmalloc causes problems for dma */ |
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img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA); |
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if (!img) { |
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ret = -ENOMEM; |
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goto abort2; |
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} |
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|
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out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); |
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if (!out) { |
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ret = -ENOMEM; |
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goto abort1; |
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} |
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|
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spi_message_init(&m); |
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memset(&t, 0, sizeof(t)); |
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t.rx_buf = out; |
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t.tx_buf = img; |
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t.len = fw->size; |
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t.bits_per_word = 8; |
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t.speed_hz = wm0010->sysclk / 10; |
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spi_message_add_tail(&t, &m); |
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|
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dev_dbg(component->dev, "Starting initial download at %dHz\n", |
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t.speed_hz); |
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|
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ret = spi_sync(spi, &m); |
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if (ret != 0) { |
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dev_err(component->dev, "Initial download failed: %d\n", ret); |
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goto abort; |
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} |
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|
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/* Look for errors from the boot ROM */ |
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for (i = 0; i < fw->size; i++) { |
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if (out[i] != 0x55) { |
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dev_err(component->dev, "Boot ROM error: %x in %d\n", |
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out[i], i); |
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wm0010_mark_boot_failure(wm0010); |
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ret = -EBUSY; |
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goto abort; |
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} |
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} |
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abort: |
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kfree(out); |
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abort1: |
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kfree(img); |
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abort2: |
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release_firmware(fw); |
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|
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return ret; |
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} |
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|
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static int wm0010_boot(struct snd_soc_component *component) |
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{ |
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struct spi_device *spi = to_spi_device(component->dev); |
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struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
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unsigned long flags; |
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int ret; |
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struct spi_message m; |
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struct spi_transfer t; |
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struct dfw_pllrec pll_rec; |
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u32 *p, len; |
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u64 *img_swap; |
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u8 *out; |
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int i; |
|
|
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spin_lock_irqsave(&wm0010->irq_lock, flags); |
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if (wm0010->state != WM0010_POWER_OFF) |
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dev_warn(wm0010->dev, "DSP already powered up!\n"); |
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spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
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|
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if (wm0010->sysclk > 26000000) { |
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dev_err(component->dev, "Max DSP clock frequency is 26MHz\n"); |
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ret = -ECANCELED; |
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goto err; |
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} |
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|
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mutex_lock(&wm0010->lock); |
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wm0010->pll_running = false; |
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|
|
dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); |
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), |
|
wm0010->core_supplies); |
|
if (ret != 0) { |
|
dev_err(&spi->dev, "Failed to enable core supplies: %d\n", |
|
ret); |
|
mutex_unlock(&wm0010->lock); |
|
goto err; |
|
} |
|
|
|
ret = regulator_enable(wm0010->dbvdd); |
|
if (ret != 0) { |
|
dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); |
|
goto err_core; |
|
} |
|
|
|
/* Release reset */ |
|
gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value); |
|
spin_lock_irqsave(&wm0010->irq_lock, flags); |
|
wm0010->state = WM0010_OUT_OF_RESET; |
|
spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
|
|
|
if (!wait_for_completion_timeout(&wm0010->boot_completion, |
|
msecs_to_jiffies(20))) |
|
dev_err(component->dev, "Failed to get interrupt from DSP\n"); |
|
|
|
spin_lock_irqsave(&wm0010->irq_lock, flags); |
|
wm0010->state = WM0010_BOOTROM; |
|
spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
|
|
|
ret = wm0010_stage2_load(component); |
|
if (ret) |
|
goto abort; |
|
|
|
if (!wait_for_completion_timeout(&wm0010->boot_completion, |
|
msecs_to_jiffies(20))) |
|
dev_err(component->dev, "Failed to get interrupt from DSP loader.\n"); |
|
|
|
spin_lock_irqsave(&wm0010->irq_lock, flags); |
|
wm0010->state = WM0010_STAGE2; |
|
spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
|
|
|
/* Only initialise PLL if max_spi_freq initialised */ |
|
if (wm0010->max_spi_freq) { |
|
|
|
/* Initialise a PLL record */ |
|
memset(&pll_rec, 0, sizeof(pll_rec)); |
|
pll_rec.command = DFW_CMD_PLL; |
|
pll_rec.length = (sizeof(pll_rec) - 8); |
|
|
|
/* On wm0010 only the CLKCTRL1 value is used */ |
|
pll_rec.clkctrl1 = wm0010->pll_clkctrl1; |
|
|
|
ret = -ENOMEM; |
|
len = pll_rec.length + 8; |
|
out = kzalloc(len, GFP_KERNEL | GFP_DMA); |
|
if (!out) |
|
goto abort; |
|
|
|
img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); |
|
if (!img_swap) |
|
goto abort_out; |
|
|
|
/* We need to re-order for 0010 */ |
|
byte_swap_64((u64 *)&pll_rec, img_swap, len); |
|
|
|
spi_message_init(&m); |
|
memset(&t, 0, sizeof(t)); |
|
t.rx_buf = out; |
|
t.tx_buf = img_swap; |
|
t.len = len; |
|
t.bits_per_word = 8; |
|
t.speed_hz = wm0010->sysclk / 6; |
|
spi_message_add_tail(&t, &m); |
|
|
|
ret = spi_sync(spi, &m); |
|
if (ret) { |
|
dev_err(component->dev, "First PLL write failed: %d\n", ret); |
|
goto abort_swap; |
|
} |
|
|
|
/* Use a second send of the message to get the return status */ |
|
ret = spi_sync(spi, &m); |
|
if (ret) { |
|
dev_err(component->dev, "Second PLL write failed: %d\n", ret); |
|
goto abort_swap; |
|
} |
|
|
|
p = (u32 *)out; |
|
|
|
/* Look for PLL active code from the DSP */ |
|
for (i = 0; i < len / 4; i++) { |
|
if (*p == 0x0e00ed0f) { |
|
dev_dbg(component->dev, "PLL packet received\n"); |
|
wm0010->pll_running = true; |
|
break; |
|
} |
|
p++; |
|
} |
|
|
|
kfree(img_swap); |
|
kfree(out); |
|
} else |
|
dev_dbg(component->dev, "Not enabling DSP PLL."); |
|
|
|
ret = wm0010_firmware_load("wm0010.dfw", component); |
|
|
|
if (ret != 0) |
|
goto abort; |
|
|
|
spin_lock_irqsave(&wm0010->irq_lock, flags); |
|
wm0010->state = WM0010_FIRMWARE; |
|
spin_unlock_irqrestore(&wm0010->irq_lock, flags); |
|
|
|
mutex_unlock(&wm0010->lock); |
|
|
|
return 0; |
|
|
|
abort_swap: |
|
kfree(img_swap); |
|
abort_out: |
|
kfree(out); |
|
abort: |
|
/* Put the chip back into reset */ |
|
wm0010_halt(component); |
|
mutex_unlock(&wm0010->lock); |
|
return ret; |
|
|
|
err_core: |
|
mutex_unlock(&wm0010->lock); |
|
regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), |
|
wm0010->core_supplies); |
|
err: |
|
return ret; |
|
} |
|
|
|
static int wm0010_set_bias_level(struct snd_soc_component *component, |
|
enum snd_soc_bias_level level) |
|
{ |
|
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
|
|
|
switch (level) { |
|
case SND_SOC_BIAS_ON: |
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) |
|
wm0010_boot(component); |
|
break; |
|
case SND_SOC_BIAS_PREPARE: |
|
break; |
|
case SND_SOC_BIAS_STANDBY: |
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) { |
|
mutex_lock(&wm0010->lock); |
|
wm0010_halt(component); |
|
mutex_unlock(&wm0010->lock); |
|
} |
|
break; |
|
case SND_SOC_BIAS_OFF: |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int wm0010_set_sysclk(struct snd_soc_component *component, int source, |
|
int clk_id, unsigned int freq, int dir) |
|
{ |
|
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
|
unsigned int i; |
|
|
|
wm0010->sysclk = freq; |
|
|
|
if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { |
|
wm0010->max_spi_freq = 0; |
|
} else { |
|
for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) |
|
if (freq >= pll_clock_map[i].max_sysclk) { |
|
wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; |
|
wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; |
|
break; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int wm0010_probe(struct snd_soc_component *component); |
|
|
|
static const struct snd_soc_component_driver soc_component_dev_wm0010 = { |
|
.probe = wm0010_probe, |
|
.set_bias_level = wm0010_set_bias_level, |
|
.set_sysclk = wm0010_set_sysclk, |
|
.dapm_widgets = wm0010_dapm_widgets, |
|
.num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), |
|
.dapm_routes = wm0010_dapm_routes, |
|
.num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), |
|
.use_pmdown_time = 1, |
|
.endianness = 1, |
|
.non_legacy_dai_naming = 1, |
|
}; |
|
|
|
#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) |
|
#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ |
|
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ |
|
SNDRV_PCM_FMTBIT_S32_LE) |
|
|
|
static struct snd_soc_dai_driver wm0010_dai[] = { |
|
{ |
|
.name = "wm0010-sdi1", |
|
.playback = { |
|
.stream_name = "SDI1 Playback", |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = WM0010_RATES, |
|
.formats = WM0010_FORMATS, |
|
}, |
|
.capture = { |
|
.stream_name = "SDI1 Capture", |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = WM0010_RATES, |
|
.formats = WM0010_FORMATS, |
|
}, |
|
}, |
|
{ |
|
.name = "wm0010-sdi2", |
|
.playback = { |
|
.stream_name = "SDI2 Playback", |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = WM0010_RATES, |
|
.formats = WM0010_FORMATS, |
|
}, |
|
.capture = { |
|
.stream_name = "SDI2 Capture", |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = WM0010_RATES, |
|
.formats = WM0010_FORMATS, |
|
}, |
|
}, |
|
}; |
|
|
|
static irqreturn_t wm0010_irq(int irq, void *data) |
|
{ |
|
struct wm0010_priv *wm0010 = data; |
|
|
|
switch (wm0010->state) { |
|
case WM0010_OUT_OF_RESET: |
|
case WM0010_BOOTROM: |
|
case WM0010_STAGE2: |
|
spin_lock(&wm0010->irq_lock); |
|
complete(&wm0010->boot_completion); |
|
spin_unlock(&wm0010->irq_lock); |
|
return IRQ_HANDLED; |
|
default: |
|
return IRQ_NONE; |
|
} |
|
|
|
return IRQ_NONE; |
|
} |
|
|
|
static int wm0010_probe(struct snd_soc_component *component) |
|
{ |
|
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); |
|
|
|
wm0010->component = component; |
|
|
|
return 0; |
|
} |
|
|
|
static int wm0010_spi_probe(struct spi_device *spi) |
|
{ |
|
unsigned long gpio_flags; |
|
int ret; |
|
int trigger; |
|
int irq; |
|
struct wm0010_priv *wm0010; |
|
|
|
wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), |
|
GFP_KERNEL); |
|
if (!wm0010) |
|
return -ENOMEM; |
|
|
|
mutex_init(&wm0010->lock); |
|
spin_lock_init(&wm0010->irq_lock); |
|
|
|
spi_set_drvdata(spi, wm0010); |
|
wm0010->dev = &spi->dev; |
|
|
|
if (dev_get_platdata(&spi->dev)) |
|
memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), |
|
sizeof(wm0010->pdata)); |
|
|
|
init_completion(&wm0010->boot_completion); |
|
|
|
wm0010->core_supplies[0].supply = "AVDD"; |
|
wm0010->core_supplies[1].supply = "DCVDD"; |
|
ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), |
|
wm0010->core_supplies); |
|
if (ret != 0) { |
|
dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", |
|
ret); |
|
return ret; |
|
} |
|
|
|
wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); |
|
if (IS_ERR(wm0010->dbvdd)) { |
|
ret = PTR_ERR(wm0010->dbvdd); |
|
dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
if (wm0010->pdata.gpio_reset) { |
|
wm0010->gpio_reset = wm0010->pdata.gpio_reset; |
|
|
|
if (wm0010->pdata.reset_active_high) |
|
wm0010->gpio_reset_value = 1; |
|
else |
|
wm0010->gpio_reset_value = 0; |
|
|
|
if (wm0010->gpio_reset_value) |
|
gpio_flags = GPIOF_OUT_INIT_HIGH; |
|
else |
|
gpio_flags = GPIOF_OUT_INIT_LOW; |
|
|
|
ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset, |
|
gpio_flags, "wm0010 reset"); |
|
if (ret < 0) { |
|
dev_err(wm0010->dev, |
|
"Failed to request GPIO for DSP reset: %d\n", |
|
ret); |
|
return ret; |
|
} |
|
} else { |
|
dev_err(wm0010->dev, "No reset GPIO configured\n"); |
|
return -EINVAL; |
|
} |
|
|
|
wm0010->state = WM0010_POWER_OFF; |
|
|
|
irq = spi->irq; |
|
if (wm0010->pdata.irq_flags) |
|
trigger = wm0010->pdata.irq_flags; |
|
else |
|
trigger = IRQF_TRIGGER_FALLING; |
|
trigger |= IRQF_ONESHOT; |
|
|
|
ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, |
|
"wm0010", wm0010); |
|
if (ret) { |
|
dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", |
|
irq, ret); |
|
return ret; |
|
} |
|
wm0010->irq = irq; |
|
|
|
ret = irq_set_irq_wake(irq, 1); |
|
if (ret) { |
|
dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", |
|
irq, ret); |
|
return ret; |
|
} |
|
|
|
if (spi->max_speed_hz) |
|
wm0010->board_max_spi_speed = spi->max_speed_hz; |
|
else |
|
wm0010->board_max_spi_speed = 0; |
|
|
|
ret = devm_snd_soc_register_component(&spi->dev, |
|
&soc_component_dev_wm0010, wm0010_dai, |
|
ARRAY_SIZE(wm0010_dai)); |
|
if (ret < 0) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int wm0010_spi_remove(struct spi_device *spi) |
|
{ |
|
struct wm0010_priv *wm0010 = spi_get_drvdata(spi); |
|
|
|
gpio_set_value_cansleep(wm0010->gpio_reset, |
|
wm0010->gpio_reset_value); |
|
|
|
irq_set_irq_wake(wm0010->irq, 0); |
|
|
|
if (wm0010->irq) |
|
free_irq(wm0010->irq, wm0010); |
|
|
|
return 0; |
|
} |
|
|
|
static struct spi_driver wm0010_spi_driver = { |
|
.driver = { |
|
.name = "wm0010", |
|
}, |
|
.probe = wm0010_spi_probe, |
|
.remove = wm0010_spi_remove, |
|
}; |
|
|
|
module_spi_driver(wm0010_spi_driver); |
|
|
|
MODULE_DESCRIPTION("ASoC WM0010 driver"); |
|
MODULE_AUTHOR("Mark Brown <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|