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147 lines
3.4 KiB
147 lines
3.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (C) 2005-2006 by Texas Instruments */ |
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#ifndef _CPPI_DMA_H_ |
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#define _CPPI_DMA_H_ |
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#include <linux/slab.h> |
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#include <linux/list.h> |
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#include <linux/errno.h> |
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#include <linux/dmapool.h> |
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#include <linux/dmaengine.h> |
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#include "musb_core.h" |
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#include "musb_dma.h" |
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/* CPPI RX/TX state RAM */ |
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struct cppi_tx_stateram { |
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u32 tx_head; /* "DMA packet" head descriptor */ |
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u32 tx_buf; |
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u32 tx_current; /* current descriptor */ |
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u32 tx_buf_current; |
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u32 tx_info; /* flags, remaining buflen */ |
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u32 tx_rem_len; |
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u32 tx_dummy; /* unused */ |
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u32 tx_complete; |
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}; |
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struct cppi_rx_stateram { |
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u32 rx_skipbytes; |
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u32 rx_head; |
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u32 rx_sop; /* "DMA packet" head descriptor */ |
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u32 rx_current; /* current descriptor */ |
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u32 rx_buf_current; |
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u32 rx_len_len; |
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u32 rx_cnt_cnt; |
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u32 rx_complete; |
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}; |
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/* hw_options bits in CPPI buffer descriptors */ |
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#define CPPI_SOP_SET ((u32)(1 << 31)) |
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#define CPPI_EOP_SET ((u32)(1 << 30)) |
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#define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */ |
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#define CPPI_EOQ_MASK ((u32)(1 << 28)) |
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#define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */ |
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#define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */ |
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#define CPPI_RECV_PKTLEN_MASK 0xFFFF |
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#define CPPI_BUFFER_LEN_MASK 0xFFFF |
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#define CPPI_TEAR_READY ((u32)(1 << 31)) |
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/* CPPI data structure definitions */ |
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#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */ |
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struct cppi_descriptor { |
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/* hardware overlay */ |
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u32 hw_next; /* next buffer descriptor Pointer */ |
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u32 hw_bufp; /* i/o buffer pointer */ |
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u32 hw_off_len; /* buffer_offset16, buffer_length16 */ |
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u32 hw_options; /* flags: SOP, EOP etc*/ |
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struct cppi_descriptor *next; |
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dma_addr_t dma; /* address of this descriptor */ |
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u32 buflen; /* for RX: original buffer length */ |
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} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN))); |
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struct cppi; |
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/* CPPI Channel Control structure */ |
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struct cppi_channel { |
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struct dma_channel channel; |
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/* back pointer to the DMA controller structure */ |
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struct cppi *controller; |
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/* which direction of which endpoint? */ |
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struct musb_hw_ep *hw_ep; |
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bool transmit; |
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u8 index; |
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/* DMA modes: RNDIS or "transparent" */ |
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u8 is_rndis; |
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/* book keeping for current transfer request */ |
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dma_addr_t buf_dma; |
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u32 buf_len; |
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u32 maxpacket; |
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u32 offset; /* dma requested */ |
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void __iomem *state_ram; /* CPPI state */ |
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struct cppi_descriptor *freelist; |
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/* BD management fields */ |
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struct cppi_descriptor *head; |
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struct cppi_descriptor *tail; |
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struct cppi_descriptor *last_processed; |
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/* use tx_complete in host role to track endpoints waiting for |
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* FIFONOTEMPTY to clear. |
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*/ |
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struct list_head tx_complete; |
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}; |
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/* CPPI DMA controller object */ |
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struct cppi { |
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struct dma_controller controller; |
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void __iomem *mregs; /* Mentor regs */ |
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void __iomem *tibase; /* TI/CPPI regs */ |
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int irq; |
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struct cppi_channel tx[4]; |
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struct cppi_channel rx[4]; |
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struct dma_pool *pool; |
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struct list_head tx_complete; |
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}; |
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/* CPPI IRQ handler */ |
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extern irqreturn_t cppi_interrupt(int, void *); |
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struct cppi41_dma_channel { |
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struct dma_channel channel; |
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struct cppi41_dma_controller *controller; |
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struct musb_hw_ep *hw_ep; |
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struct dma_chan *dc; |
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dma_cookie_t cookie; |
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u8 port_num; |
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u8 is_tx; |
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u8 is_allocated; |
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u8 usb_toggle; |
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dma_addr_t buf_addr; |
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u32 total_len; |
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u32 prog_len; |
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u32 transferred; |
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u32 packet_sz; |
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struct list_head tx_check; |
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int tx_zlp; |
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}; |
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#endif /* end of ifndef _CPPI_DMA_H_ */
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