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703 lines
17 KiB
703 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* MediaTek xHCI Host Controller Driver |
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* |
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* Copyright (c) 2015 MediaTek Inc. |
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* Author: |
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* Chunfeng Yun <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/regulator/consumer.h> |
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|
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#include "xhci.h" |
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#include "xhci-mtk.h" |
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|
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/* ip_pw_ctrl0 register */ |
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#define CTRL0_IP_SW_RST BIT(0) |
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|
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/* ip_pw_ctrl1 register */ |
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#define CTRL1_IP_HOST_PDN BIT(0) |
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|
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/* ip_pw_ctrl2 register */ |
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#define CTRL2_IP_DEV_PDN BIT(0) |
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|
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/* ip_pw_sts1 register */ |
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#define STS1_IP_SLEEP_STS BIT(30) |
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#define STS1_U3_MAC_RST BIT(16) |
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#define STS1_XHCI_RST BIT(11) |
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#define STS1_SYS125_RST BIT(10) |
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#define STS1_REF_RST BIT(8) |
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#define STS1_SYSPLL_STABLE BIT(0) |
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|
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/* ip_xhci_cap register */ |
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#define CAP_U3_PORT_NUM(p) ((p) & 0xff) |
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#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) |
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|
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/* u3_ctrl_p register */ |
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#define CTRL_U3_PORT_HOST_SEL BIT(2) |
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#define CTRL_U3_PORT_PDN BIT(1) |
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#define CTRL_U3_PORT_DIS BIT(0) |
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|
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/* u2_ctrl_p register */ |
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#define CTRL_U2_PORT_HOST_SEL BIT(2) |
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#define CTRL_U2_PORT_PDN BIT(1) |
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#define CTRL_U2_PORT_DIS BIT(0) |
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|
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/* u2_phy_pll register */ |
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#define CTRL_U2_FORCE_PLL_STB BIT(28) |
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|
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/* usb remote wakeup registers in syscon */ |
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/* mt8173 etc */ |
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#define PERI_WK_CTRL1 0x4 |
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#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ |
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#define WC1_IS_EN BIT(25) |
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#define WC1_IS_P BIT(6) /* polarity for ip sleep */ |
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|
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/* mt2712 etc */ |
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#define PERI_SSUSB_SPM_CTRL 0x0 |
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#define SSC_IP_SLEEP_EN BIT(4) |
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#define SSC_SPM_INT_EN BIT(1) |
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|
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enum ssusb_uwk_vers { |
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SSUSB_UWK_V1 = 1, |
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SSUSB_UWK_V2, |
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}; |
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static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) |
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{ |
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struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; |
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u32 value, check_val; |
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int u3_ports_disabled = 0; |
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int ret; |
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int i; |
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if (!mtk->has_ippc) |
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return 0; |
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/* power on host ip */ |
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value = readl(&ippc->ip_pw_ctr1); |
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value &= ~CTRL1_IP_HOST_PDN; |
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writel(value, &ippc->ip_pw_ctr1); |
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|
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/* power on and enable u3 ports except skipped ones */ |
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for (i = 0; i < mtk->num_u3_ports; i++) { |
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if ((0x1 << i) & mtk->u3p_dis_msk) { |
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u3_ports_disabled++; |
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continue; |
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} |
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value = readl(&ippc->u3_ctrl_p[i]); |
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value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); |
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value |= CTRL_U3_PORT_HOST_SEL; |
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writel(value, &ippc->u3_ctrl_p[i]); |
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} |
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/* power on and enable all u2 ports */ |
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for (i = 0; i < mtk->num_u2_ports; i++) { |
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value = readl(&ippc->u2_ctrl_p[i]); |
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value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); |
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value |= CTRL_U2_PORT_HOST_SEL; |
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writel(value, &ippc->u2_ctrl_p[i]); |
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} |
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/* |
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* wait for clocks to be stable, and clock domains reset to |
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* be inactive after power on and enable ports |
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*/ |
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check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | |
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STS1_SYS125_RST | STS1_XHCI_RST; |
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if (mtk->num_u3_ports > u3_ports_disabled) |
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check_val |= STS1_U3_MAC_RST; |
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ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, |
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(check_val == (value & check_val)), 100, 20000); |
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if (ret) { |
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dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); |
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return ret; |
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} |
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return 0; |
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} |
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static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) |
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{ |
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struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; |
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u32 value; |
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int ret; |
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int i; |
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if (!mtk->has_ippc) |
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return 0; |
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/* power down u3 ports except skipped ones */ |
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for (i = 0; i < mtk->num_u3_ports; i++) { |
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if ((0x1 << i) & mtk->u3p_dis_msk) |
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continue; |
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value = readl(&ippc->u3_ctrl_p[i]); |
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value |= CTRL_U3_PORT_PDN; |
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writel(value, &ippc->u3_ctrl_p[i]); |
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} |
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/* power down all u2 ports */ |
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for (i = 0; i < mtk->num_u2_ports; i++) { |
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value = readl(&ippc->u2_ctrl_p[i]); |
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value |= CTRL_U2_PORT_PDN; |
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writel(value, &ippc->u2_ctrl_p[i]); |
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} |
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/* power down host ip */ |
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value = readl(&ippc->ip_pw_ctr1); |
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value |= CTRL1_IP_HOST_PDN; |
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writel(value, &ippc->ip_pw_ctr1); |
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/* wait for host ip to sleep */ |
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ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, |
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(value & STS1_IP_SLEEP_STS), 100, 100000); |
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if (ret) { |
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dev_err(mtk->dev, "ip sleep failed!!!\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) |
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{ |
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struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; |
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u32 value; |
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if (!mtk->has_ippc) |
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return 0; |
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/* reset whole ip */ |
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value = readl(&ippc->ip_pw_ctr0); |
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value |= CTRL0_IP_SW_RST; |
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writel(value, &ippc->ip_pw_ctr0); |
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udelay(1); |
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value = readl(&ippc->ip_pw_ctr0); |
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value &= ~CTRL0_IP_SW_RST; |
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writel(value, &ippc->ip_pw_ctr0); |
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/* |
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* device ip is default power-on in fact |
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* power down device ip, otherwise ip-sleep will fail |
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*/ |
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value = readl(&ippc->ip_pw_ctr2); |
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value |= CTRL2_IP_DEV_PDN; |
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writel(value, &ippc->ip_pw_ctr2); |
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value = readl(&ippc->ip_xhci_cap); |
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mtk->num_u3_ports = CAP_U3_PORT_NUM(value); |
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mtk->num_u2_ports = CAP_U2_PORT_NUM(value); |
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dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, |
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mtk->num_u2_ports, mtk->num_u3_ports); |
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return xhci_mtk_host_enable(mtk); |
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} |
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static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) |
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{ |
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struct device *dev = mtk->dev; |
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mtk->sys_clk = devm_clk_get(dev, "sys_ck"); |
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if (IS_ERR(mtk->sys_clk)) { |
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dev_err(dev, "fail to get sys_ck\n"); |
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return PTR_ERR(mtk->sys_clk); |
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} |
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mtk->xhci_clk = devm_clk_get_optional(dev, "xhci_ck"); |
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if (IS_ERR(mtk->xhci_clk)) |
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return PTR_ERR(mtk->xhci_clk); |
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mtk->ref_clk = devm_clk_get_optional(dev, "ref_ck"); |
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if (IS_ERR(mtk->ref_clk)) |
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return PTR_ERR(mtk->ref_clk); |
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mtk->mcu_clk = devm_clk_get_optional(dev, "mcu_ck"); |
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if (IS_ERR(mtk->mcu_clk)) |
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return PTR_ERR(mtk->mcu_clk); |
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mtk->dma_clk = devm_clk_get_optional(dev, "dma_ck"); |
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return PTR_ERR_OR_ZERO(mtk->dma_clk); |
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} |
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static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk) |
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{ |
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int ret; |
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ret = clk_prepare_enable(mtk->ref_clk); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable ref_clk\n"); |
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goto ref_clk_err; |
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} |
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ret = clk_prepare_enable(mtk->sys_clk); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable sys_clk\n"); |
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goto sys_clk_err; |
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} |
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ret = clk_prepare_enable(mtk->xhci_clk); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable xhci_clk\n"); |
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goto xhci_clk_err; |
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} |
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ret = clk_prepare_enable(mtk->mcu_clk); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable mcu_clk\n"); |
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goto mcu_clk_err; |
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} |
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ret = clk_prepare_enable(mtk->dma_clk); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable dma_clk\n"); |
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goto dma_clk_err; |
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} |
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return 0; |
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dma_clk_err: |
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clk_disable_unprepare(mtk->mcu_clk); |
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mcu_clk_err: |
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clk_disable_unprepare(mtk->xhci_clk); |
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xhci_clk_err: |
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clk_disable_unprepare(mtk->sys_clk); |
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sys_clk_err: |
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clk_disable_unprepare(mtk->ref_clk); |
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ref_clk_err: |
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return ret; |
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} |
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static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) |
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{ |
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clk_disable_unprepare(mtk->dma_clk); |
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clk_disable_unprepare(mtk->mcu_clk); |
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clk_disable_unprepare(mtk->xhci_clk); |
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clk_disable_unprepare(mtk->sys_clk); |
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clk_disable_unprepare(mtk->ref_clk); |
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} |
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/* only clocks can be turn off for ip-sleep wakeup mode */ |
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static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) |
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{ |
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u32 reg, msk, val; |
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switch (mtk->uwk_vers) { |
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case SSUSB_UWK_V1: |
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reg = mtk->uwk_reg_base + PERI_WK_CTRL1; |
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msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; |
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val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; |
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break; |
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case SSUSB_UWK_V2: |
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reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; |
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msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; |
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val = enable ? msk : 0; |
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break; |
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default: |
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return; |
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} |
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regmap_update_bits(mtk->uwk, reg, msk, val); |
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} |
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static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, |
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struct device_node *dn) |
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{ |
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struct of_phandle_args args; |
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int ret; |
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|
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/* Wakeup function is optional */ |
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mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); |
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if (!mtk->uwk_en) |
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return 0; |
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ret = of_parse_phandle_with_fixed_args(dn, |
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"mediatek,syscon-wakeup", 2, 0, &args); |
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if (ret) |
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return ret; |
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mtk->uwk_reg_base = args.args[0]; |
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mtk->uwk_vers = args.args[1]; |
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mtk->uwk = syscon_node_to_regmap(args.np); |
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of_node_put(args.np); |
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dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", |
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mtk->uwk_reg_base, mtk->uwk_vers); |
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return PTR_ERR_OR_ZERO(mtk->uwk); |
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} |
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static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) |
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{ |
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if (mtk->uwk_en) |
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usb_wakeup_ip_sleep_set(mtk, enable); |
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} |
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static int xhci_mtk_setup(struct usb_hcd *hcd); |
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static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { |
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.reset = xhci_mtk_setup, |
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.check_bandwidth = xhci_mtk_check_bandwidth, |
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.reset_bandwidth = xhci_mtk_reset_bandwidth, |
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}; |
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static struct hc_driver __read_mostly xhci_mtk_hc_driver; |
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static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) |
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{ |
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int ret; |
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ret = regulator_enable(mtk->vbus); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable vbus\n"); |
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return ret; |
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} |
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ret = regulator_enable(mtk->vusb33); |
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if (ret) { |
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dev_err(mtk->dev, "failed to enable vusb33\n"); |
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regulator_disable(mtk->vbus); |
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return ret; |
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} |
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return 0; |
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} |
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static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) |
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{ |
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regulator_disable(mtk->vbus); |
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regulator_disable(mtk->vusb33); |
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} |
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static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) |
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{ |
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struct usb_hcd *hcd = xhci_to_hcd(xhci); |
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struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); |
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|
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/* |
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* As of now platform drivers don't provide MSI support so we ensure |
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* here that the generic code does not try to make a pci_dev from our |
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* dev struct in order to setup MSI |
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*/ |
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xhci->quirks |= XHCI_PLAT; |
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xhci->quirks |= XHCI_MTK_HOST; |
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/* |
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* MTK host controller gives a spurious successful event after a |
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* short transfer. Ignore it. |
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*/ |
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xhci->quirks |= XHCI_SPURIOUS_SUCCESS; |
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if (mtk->lpm_support) |
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xhci->quirks |= XHCI_LPM_SUPPORT; |
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if (mtk->u2_lpm_disable) |
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xhci->quirks |= XHCI_HW_LPM_DISABLE; |
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/* |
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* MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream, |
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* and it's 3 when support it. |
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*/ |
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if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4) |
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xhci->quirks |= XHCI_BROKEN_STREAMS; |
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} |
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/* called during probe() after chip reset completes */ |
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static int xhci_mtk_setup(struct usb_hcd *hcd) |
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{ |
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struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); |
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int ret; |
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if (usb_hcd_is_primary_hcd(hcd)) { |
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ret = xhci_mtk_ssusb_config(mtk); |
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if (ret) |
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return ret; |
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} |
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ret = xhci_gen_setup(hcd, xhci_mtk_quirks); |
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if (ret) |
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return ret; |
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if (usb_hcd_is_primary_hcd(hcd)) { |
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ret = xhci_mtk_sch_init(mtk); |
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if (ret) |
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return ret; |
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} |
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return ret; |
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} |
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static int xhci_mtk_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->of_node; |
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struct xhci_hcd_mtk *mtk; |
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const struct hc_driver *driver; |
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struct xhci_hcd *xhci; |
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struct resource *res; |
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struct usb_hcd *hcd; |
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int ret = -ENODEV; |
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int irq; |
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|
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if (usb_disabled()) |
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return -ENODEV; |
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driver = &xhci_mtk_hc_driver; |
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mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); |
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if (!mtk) |
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return -ENOMEM; |
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|
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mtk->dev = dev; |
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mtk->vbus = devm_regulator_get(dev, "vbus"); |
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if (IS_ERR(mtk->vbus)) { |
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dev_err(dev, "fail to get vbus\n"); |
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return PTR_ERR(mtk->vbus); |
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} |
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mtk->vusb33 = devm_regulator_get(dev, "vusb33"); |
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if (IS_ERR(mtk->vusb33)) { |
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dev_err(dev, "fail to get vusb33\n"); |
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return PTR_ERR(mtk->vusb33); |
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} |
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|
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ret = xhci_mtk_clks_get(mtk); |
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if (ret) |
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return ret; |
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|
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mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); |
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mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable"); |
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/* optional property, ignore the error if it does not exist */ |
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of_property_read_u32(node, "mediatek,u3p-dis-msk", |
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&mtk->u3p_dis_msk); |
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|
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ret = usb_wakeup_of_property_parse(mtk, node); |
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if (ret) { |
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dev_err(dev, "failed to parse uwk property\n"); |
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return ret; |
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} |
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|
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pm_runtime_enable(dev); |
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pm_runtime_get_sync(dev); |
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device_enable_async_suspend(dev); |
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ret = xhci_mtk_ldos_enable(mtk); |
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if (ret) |
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goto disable_pm; |
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ret = xhci_mtk_clks_enable(mtk); |
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if (ret) |
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goto disable_ldos; |
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|
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) { |
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ret = irq; |
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goto disable_clk; |
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} |
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hcd = usb_create_hcd(driver, dev, dev_name(dev)); |
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if (!hcd) { |
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ret = -ENOMEM; |
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goto disable_clk; |
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} |
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|
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/* |
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* USB 2.0 roothub is stored in the platform_device. |
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* Swap it with mtk HCD. |
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*/ |
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mtk->hcd = platform_get_drvdata(pdev); |
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platform_set_drvdata(pdev, mtk); |
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|
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); |
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hcd->regs = devm_ioremap_resource(dev, res); |
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if (IS_ERR(hcd->regs)) { |
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ret = PTR_ERR(hcd->regs); |
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goto put_usb2_hcd; |
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} |
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hcd->rsrc_start = res->start; |
|
hcd->rsrc_len = resource_size(res); |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); |
|
if (res) { /* ippc register is optional */ |
|
mtk->ippc_regs = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(mtk->ippc_regs)) { |
|
ret = PTR_ERR(mtk->ippc_regs); |
|
goto put_usb2_hcd; |
|
} |
|
mtk->has_ippc = true; |
|
} else { |
|
mtk->has_ippc = false; |
|
} |
|
|
|
device_init_wakeup(dev, true); |
|
|
|
xhci = hcd_to_xhci(hcd); |
|
xhci->main_hcd = hcd; |
|
|
|
/* |
|
* imod_interval is the interrupt moderation value in nanoseconds. |
|
* The increment interval is 8 times as much as that defined in |
|
* the xHCI spec on MTK's controller. |
|
*/ |
|
xhci->imod_interval = 5000; |
|
device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); |
|
|
|
xhci->shared_hcd = usb_create_shared_hcd(driver, dev, |
|
dev_name(dev), hcd); |
|
if (!xhci->shared_hcd) { |
|
ret = -ENOMEM; |
|
goto disable_device_wakeup; |
|
} |
|
|
|
ret = usb_add_hcd(hcd, irq, IRQF_SHARED); |
|
if (ret) |
|
goto put_usb3_hcd; |
|
|
|
if (HCC_MAX_PSA(xhci->hcc_params) >= 4 && |
|
!(xhci->quirks & XHCI_BROKEN_STREAMS)) |
|
xhci->shared_hcd->can_do_streams = 1; |
|
|
|
ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); |
|
if (ret) |
|
goto dealloc_usb2_hcd; |
|
|
|
return 0; |
|
|
|
dealloc_usb2_hcd: |
|
usb_remove_hcd(hcd); |
|
|
|
put_usb3_hcd: |
|
xhci_mtk_sch_exit(mtk); |
|
usb_put_hcd(xhci->shared_hcd); |
|
|
|
disable_device_wakeup: |
|
device_init_wakeup(dev, false); |
|
|
|
put_usb2_hcd: |
|
usb_put_hcd(hcd); |
|
|
|
disable_clk: |
|
xhci_mtk_clks_disable(mtk); |
|
|
|
disable_ldos: |
|
xhci_mtk_ldos_disable(mtk); |
|
|
|
disable_pm: |
|
pm_runtime_put_sync(dev); |
|
pm_runtime_disable(dev); |
|
return ret; |
|
} |
|
|
|
static int xhci_mtk_remove(struct platform_device *dev) |
|
{ |
|
struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev); |
|
struct usb_hcd *hcd = mtk->hcd; |
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
|
struct usb_hcd *shared_hcd = xhci->shared_hcd; |
|
|
|
pm_runtime_put_noidle(&dev->dev); |
|
pm_runtime_disable(&dev->dev); |
|
|
|
usb_remove_hcd(shared_hcd); |
|
xhci->shared_hcd = NULL; |
|
device_init_wakeup(&dev->dev, false); |
|
|
|
usb_remove_hcd(hcd); |
|
usb_put_hcd(shared_hcd); |
|
usb_put_hcd(hcd); |
|
xhci_mtk_sch_exit(mtk); |
|
xhci_mtk_clks_disable(mtk); |
|
xhci_mtk_ldos_disable(mtk); |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* if ip sleep fails, and all clocks are disabled, access register will hang |
|
* AHB bus, so stop polling roothubs to avoid regs access on bus suspend. |
|
* and no need to check whether ip sleep failed or not; this will cause SPM |
|
* to wake up system immediately after system suspend complete if ip sleep |
|
* fails, it is what we wanted. |
|
*/ |
|
static int __maybe_unused xhci_mtk_suspend(struct device *dev) |
|
{ |
|
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
|
struct usb_hcd *hcd = mtk->hcd; |
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
|
|
|
xhci_dbg(xhci, "%s: stop port polling\n", __func__); |
|
clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
|
del_timer_sync(&hcd->rh_timer); |
|
clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
|
del_timer_sync(&xhci->shared_hcd->rh_timer); |
|
|
|
xhci_mtk_host_disable(mtk); |
|
xhci_mtk_clks_disable(mtk); |
|
usb_wakeup_set(mtk, true); |
|
return 0; |
|
} |
|
|
|
static int __maybe_unused xhci_mtk_resume(struct device *dev) |
|
{ |
|
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
|
struct usb_hcd *hcd = mtk->hcd; |
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
|
|
|
usb_wakeup_set(mtk, false); |
|
xhci_mtk_clks_enable(mtk); |
|
xhci_mtk_host_enable(mtk); |
|
|
|
xhci_dbg(xhci, "%s: restart port polling\n", __func__); |
|
set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
|
usb_hcd_poll_rh_status(xhci->shared_hcd); |
|
set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
|
usb_hcd_poll_rh_status(hcd); |
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops xhci_mtk_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) |
|
}; |
|
#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id mtk_xhci_of_match[] = { |
|
{ .compatible = "mediatek,mt8173-xhci"}, |
|
{ .compatible = "mediatek,mtk-xhci"}, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); |
|
#endif |
|
|
|
static struct platform_driver mtk_xhci_driver = { |
|
.probe = xhci_mtk_probe, |
|
.remove = xhci_mtk_remove, |
|
.driver = { |
|
.name = "xhci-mtk", |
|
.pm = DEV_PM_OPS, |
|
.of_match_table = of_match_ptr(mtk_xhci_of_match), |
|
}, |
|
}; |
|
MODULE_ALIAS("platform:xhci-mtk"); |
|
|
|
static int __init xhci_mtk_init(void) |
|
{ |
|
xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); |
|
return platform_driver_register(&mtk_xhci_driver); |
|
} |
|
module_init(xhci_mtk_init); |
|
|
|
static void __exit xhci_mtk_exit(void) |
|
{ |
|
platform_driver_unregister(&mtk_xhci_driver); |
|
} |
|
module_exit(xhci_mtk_exit); |
|
|
|
MODULE_AUTHOR("Chunfeng Yun <[email protected]>"); |
|
MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|