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110 lines
2.5 KiB
110 lines
2.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* XHCI extended capability handling |
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* |
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* Copyright (c) 2017 Hans de Goede <[email protected]> |
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*/ |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#include <linux/pci.h> |
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#include "xhci.h" |
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#define USB_SW_DRV_NAME "intel_xhci_usb_sw" |
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#define USB_SW_RESOURCE_SIZE 0x400 |
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#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
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static const struct property_entry role_switch_props[] = { |
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PROPERTY_ENTRY_BOOL("sw_switch_disable"), |
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{}, |
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}; |
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static void xhci_intel_unregister_pdev(void *arg) |
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{ |
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platform_device_unregister(arg); |
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} |
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static int xhci_create_intel_xhci_sw_pdev(struct xhci_hcd *xhci, u32 cap_offset) |
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{ |
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struct usb_hcd *hcd = xhci_to_hcd(xhci); |
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struct device *dev = hcd->self.controller; |
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struct platform_device *pdev; |
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struct pci_dev *pci = to_pci_dev(dev); |
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struct resource res = { 0, }; |
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int ret; |
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pdev = platform_device_alloc(USB_SW_DRV_NAME, PLATFORM_DEVID_NONE); |
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if (!pdev) { |
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xhci_err(xhci, "couldn't allocate %s platform device\n", |
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USB_SW_DRV_NAME); |
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return -ENOMEM; |
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} |
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res.start = hcd->rsrc_start + cap_offset; |
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res.end = res.start + USB_SW_RESOURCE_SIZE - 1; |
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res.name = USB_SW_DRV_NAME; |
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res.flags = IORESOURCE_MEM; |
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ret = platform_device_add_resources(pdev, &res, 1); |
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if (ret) { |
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dev_err(dev, "couldn't add resources to intel_xhci_usb_sw pdev\n"); |
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platform_device_put(pdev); |
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return ret; |
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} |
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if (pci->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { |
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ret = device_create_managed_software_node(&pdev->dev, role_switch_props, |
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NULL); |
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if (ret) { |
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dev_err(dev, "failed to register device properties\n"); |
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platform_device_put(pdev); |
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return ret; |
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} |
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} |
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pdev->dev.parent = dev; |
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ret = platform_device_add(pdev); |
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if (ret) { |
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dev_err(dev, "couldn't register intel_xhci_usb_sw pdev\n"); |
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platform_device_put(pdev); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(dev, xhci_intel_unregister_pdev, pdev); |
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if (ret) { |
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dev_err(dev, "couldn't add unregister action for intel_xhci_usb_sw pdev\n"); |
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return ret; |
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} |
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return 0; |
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} |
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int xhci_ext_cap_init(struct xhci_hcd *xhci) |
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{ |
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void __iomem *base = &xhci->cap_regs->hc_capbase; |
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u32 offset, val; |
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int ret; |
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offset = xhci_find_next_ext_cap(base, 0, 0); |
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while (offset) { |
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val = readl(base + offset); |
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switch (XHCI_EXT_CAPS_ID(val)) { |
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case XHCI_EXT_CAPS_VENDOR_INTEL: |
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if (xhci->quirks & XHCI_INTEL_USB_ROLE_SW) { |
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ret = xhci_create_intel_xhci_sw_pdev(xhci, |
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offset); |
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if (ret) |
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return ret; |
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} |
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break; |
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} |
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offset = xhci_find_next_ext_cap(base, offset, 0); |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(xhci_ext_cap_init);
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