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894 lines
28 KiB
894 lines
28 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Copyright (c) 2001-2002 by David Brownell |
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*/ |
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#ifndef __LINUX_EHCI_HCD_H |
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#define __LINUX_EHCI_HCD_H |
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|
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/* definitions used for the EHCI driver */ |
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/* |
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* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to |
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* __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on |
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* the host controller implementation. |
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* |
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* To facilitate the strongest possible byte-order checking from "sparse" |
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* and so on, we use __leXX unless that's not practical. |
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*/ |
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC |
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typedef __u32 __bitwise __hc32; |
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typedef __u16 __bitwise __hc16; |
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#else |
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#define __hc32 __le32 |
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#define __hc16 __le16 |
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#endif |
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/* statistics can be kept for tuning/monitoring */ |
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#ifdef CONFIG_DYNAMIC_DEBUG |
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#define EHCI_STATS |
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#endif |
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struct ehci_stats { |
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/* irq usage */ |
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unsigned long normal; |
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unsigned long error; |
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unsigned long iaa; |
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unsigned long lost_iaa; |
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/* termination of urbs from core */ |
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unsigned long complete; |
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unsigned long unlink; |
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}; |
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/* |
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* Scheduling and budgeting information for periodic transfers, for both |
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* high-speed devices and full/low-speed devices lying behind a TT. |
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*/ |
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struct ehci_per_sched { |
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struct usb_device *udev; /* access to the TT */ |
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struct usb_host_endpoint *ep; |
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struct list_head ps_list; /* node on ehci_tt's ps_list */ |
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u16 tt_usecs; /* time on the FS/LS bus */ |
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u16 cs_mask; /* C-mask and S-mask bytes */ |
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u16 period; /* actual period in frames */ |
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u16 phase; /* actual phase, frame part */ |
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u8 bw_phase; /* same, for bandwidth |
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reservation */ |
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u8 phase_uf; /* uframe part of the phase */ |
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u8 usecs, c_usecs; /* times on the HS bus */ |
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u8 bw_uperiod; /* period in microframes, for |
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bandwidth reservation */ |
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u8 bw_period; /* same, in frames */ |
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}; |
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#define NO_FRAME 29999 /* frame not assigned yet */ |
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/* ehci_hcd->lock guards shared data against other CPUs: |
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* ehci_hcd: async, unlink, periodic (and shadow), ... |
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* usb_host_endpoint: hcpriv |
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* ehci_qh: qh_next, qtd_list |
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* ehci_qtd: qtd_list |
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* |
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* Also, hold this lock when talking to HC registers or |
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* when updating hw_* fields in shared qh/qtd/... structures. |
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*/ |
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#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ |
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/* |
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* ehci_rh_state values of EHCI_RH_RUNNING or above mean that the |
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* controller may be doing DMA. Lower values mean there's no DMA. |
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*/ |
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enum ehci_rh_state { |
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EHCI_RH_HALTED, |
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EHCI_RH_SUSPENDED, |
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EHCI_RH_RUNNING, |
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EHCI_RH_STOPPING |
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}; |
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/* |
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* Timer events, ordered by increasing delay length. |
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* Always update event_delays_ns[] and event_handlers[] (defined in |
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* ehci-timer.c) in parallel with this list. |
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*/ |
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enum ehci_hrtimer_event { |
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EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ |
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EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ |
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EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ |
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EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ |
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EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ |
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EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */ |
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EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ |
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EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ |
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EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ |
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EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ |
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EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ |
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EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ |
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EHCI_HRTIMER_NUM_EVENTS /* Must come last */ |
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}; |
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#define EHCI_HRTIMER_NO_EVENT 99 |
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struct ehci_hcd { /* one per controller */ |
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/* timing support */ |
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enum ehci_hrtimer_event next_hrtimer_event; |
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unsigned enabled_hrtimer_events; |
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ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; |
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struct hrtimer hrtimer; |
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int PSS_poll_count; |
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int ASS_poll_count; |
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int died_poll_count; |
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/* glue to PCI and HCD framework */ |
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struct ehci_caps __iomem *caps; |
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struct ehci_regs __iomem *regs; |
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struct ehci_dbg_port __iomem *debug; |
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__u32 hcs_params; /* cached register copy */ |
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spinlock_t lock; |
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enum ehci_rh_state rh_state; |
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/* general schedule support */ |
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bool scanning:1; |
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bool need_rescan:1; |
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bool intr_unlinking:1; |
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bool iaa_in_progress:1; |
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bool async_unlinking:1; |
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bool shutdown:1; |
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struct ehci_qh *qh_scan_next; |
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/* async schedule support */ |
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struct ehci_qh *async; |
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struct ehci_qh *dummy; /* For AMD quirk use */ |
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struct list_head async_unlink; |
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struct list_head async_idle; |
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unsigned async_unlink_cycle; |
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unsigned async_count; /* async activity count */ |
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__hc32 old_current; /* Test for QH becoming */ |
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__hc32 old_token; /* inactive during unlink */ |
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/* periodic schedule support */ |
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#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ |
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unsigned periodic_size; |
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__hc32 *periodic; /* hw periodic table */ |
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dma_addr_t periodic_dma; |
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struct list_head intr_qh_list; |
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unsigned i_thresh; /* uframes HC might cache */ |
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union ehci_shadow *pshadow; /* mirror hw periodic table */ |
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struct list_head intr_unlink_wait; |
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struct list_head intr_unlink; |
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unsigned intr_unlink_wait_cycle; |
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unsigned intr_unlink_cycle; |
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unsigned now_frame; /* frame from HC hardware */ |
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unsigned last_iso_frame; /* last frame scanned for iso */ |
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unsigned intr_count; /* intr activity count */ |
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unsigned isoc_count; /* isoc activity count */ |
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unsigned periodic_count; /* periodic activity count */ |
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unsigned uframe_periodic_max; /* max periodic time per uframe */ |
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/* list of itds & sitds completed while now_frame was still active */ |
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struct list_head cached_itd_list; |
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struct ehci_itd *last_itd_to_free; |
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struct list_head cached_sitd_list; |
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struct ehci_sitd *last_sitd_to_free; |
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/* per root hub port */ |
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unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; |
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/* bit vectors (one bit per port) */ |
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unsigned long bus_suspended; /* which ports were |
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already suspended at the start of a bus suspend */ |
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unsigned long companion_ports; /* which ports are |
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dedicated to the companion controller */ |
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unsigned long owned_ports; /* which ports are |
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owned by the companion during a bus suspend */ |
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unsigned long port_c_suspend; /* which ports have |
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the change-suspend feature turned on */ |
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unsigned long suspended_ports; /* which ports are |
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suspended */ |
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unsigned long resuming_ports; /* which ports have |
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started to resume */ |
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/* per-HC memory pools (could be per-bus, but ...) */ |
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struct dma_pool *qh_pool; /* qh per active urb */ |
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struct dma_pool *qtd_pool; /* one or more per qh */ |
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struct dma_pool *itd_pool; /* itd per iso urb */ |
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struct dma_pool *sitd_pool; /* sitd per split iso urb */ |
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unsigned random_frame; |
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unsigned long next_statechange; |
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ktime_t last_periodic_enable; |
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u32 command; |
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/* SILICON QUIRKS */ |
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unsigned no_selective_suspend:1; |
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unsigned has_fsl_port_bug:1; /* FreeScale */ |
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unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ |
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unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ |
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unsigned big_endian_mmio:1; |
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unsigned big_endian_desc:1; |
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unsigned big_endian_capbase:1; |
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unsigned has_amcc_usb23:1; |
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unsigned need_io_watchdog:1; |
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unsigned amd_pll_fix:1; |
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unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ |
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unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ |
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unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ |
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unsigned need_oc_pp_cycle:1; /* MPC834X port power */ |
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unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ |
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/* required for usb32 quirk */ |
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#define OHCI_CTRL_HCFS (3 << 6) |
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#define OHCI_USB_OPER (2 << 6) |
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#define OHCI_USB_SUSPEND (3 << 6) |
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#define OHCI_HCCTRL_OFFSET 0x4 |
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#define OHCI_HCCTRL_LEN 0x4 |
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__hc32 *ohci_hcctrl_reg; |
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unsigned has_hostpc:1; |
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unsigned has_tdi_phy_lpm:1; |
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unsigned has_ppcd:1; /* support per-port change bits */ |
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u8 sbrn; /* packed release number */ |
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/* irq statistics */ |
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#ifdef EHCI_STATS |
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struct ehci_stats stats; |
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# define INCR(x) ((x)++) |
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#else |
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# define INCR(x) do {} while (0) |
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#endif |
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/* debug files */ |
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#ifdef CONFIG_DYNAMIC_DEBUG |
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struct dentry *debug_dir; |
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#endif |
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/* bandwidth usage */ |
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#define EHCI_BANDWIDTH_SIZE 64 |
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#define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) |
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u8 bandwidth[EHCI_BANDWIDTH_SIZE]; |
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/* us allocated per uframe */ |
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u8 tt_budget[EHCI_BANDWIDTH_SIZE]; |
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/* us budgeted per uframe */ |
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struct list_head tt_list; |
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/* platform-specific data -- must come last */ |
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unsigned long priv[] __aligned(sizeof(s64)); |
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}; |
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/* convert between an HCD pointer and the corresponding EHCI_HCD */ |
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static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd) |
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{ |
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return (struct ehci_hcd *) (hcd->hcd_priv); |
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} |
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static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci) |
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{ |
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return container_of((void *) ehci, struct usb_hcd, hcd_priv); |
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} |
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/*-------------------------------------------------------------------------*/ |
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#include <linux/usb/ehci_def.h> |
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/*-------------------------------------------------------------------------*/ |
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#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
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/* |
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* EHCI Specification 0.95 Section 3.5 |
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* QTD: describe data transfer components (buffer, direction, ...) |
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* See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
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* |
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* These are associated only with "QH" (Queue Head) structures, |
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* used with control, bulk, and interrupt transfers. |
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*/ |
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struct ehci_qtd { |
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/* first part defined by EHCI spec */ |
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__hc32 hw_next; /* see EHCI 3.5.1 */ |
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__hc32 hw_alt_next; /* see EHCI 3.5.2 */ |
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__hc32 hw_token; /* see EHCI 3.5.3 */ |
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#define QTD_TOGGLE (1 << 31) /* data toggle */ |
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#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) |
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#define QTD_IOC (1 << 15) /* interrupt on complete */ |
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#define QTD_CERR(tok) (((tok)>>10) & 0x3) |
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#define QTD_PID(tok) (((tok)>>8) & 0x3) |
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#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ |
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#define QTD_STS_HALT (1 << 6) /* halted on error */ |
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#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ |
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#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ |
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#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ |
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#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ |
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#define QTD_STS_STS (1 << 1) /* split transaction state */ |
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#define QTD_STS_PING (1 << 0) /* issue PING? */ |
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#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) |
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#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) |
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#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) |
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__hc32 hw_buf[5]; /* see EHCI 3.5.4 */ |
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__hc32 hw_buf_hi[5]; /* Appendix B */ |
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/* the rest is HCD-private */ |
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dma_addr_t qtd_dma; /* qtd address */ |
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struct list_head qtd_list; /* sw qtd list */ |
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struct urb *urb; /* qtd's urb */ |
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size_t length; /* length of buffer */ |
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} __aligned(32); |
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/* mask NakCnt+T in qh->hw_alt_next */ |
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#define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f) |
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#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) |
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/*-------------------------------------------------------------------------*/ |
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/* type tag from {qh,itd,sitd,fstn}->hw_next */ |
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#define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
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/* |
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* Now the following defines are not converted using the |
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* cpu_to_le32() macro anymore, since we have to support |
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* "dynamic" switching between be and le support, so that the driver |
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* can be used on one system with SoC EHCI controller using big-endian |
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* descriptors as well as a normal little-endian PCI EHCI controller. |
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*/ |
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/* values for that type tag */ |
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#define Q_TYPE_ITD (0 << 1) |
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#define Q_TYPE_QH (1 << 1) |
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#define Q_TYPE_SITD (2 << 1) |
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#define Q_TYPE_FSTN (3 << 1) |
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/* next async queue entry, or pointer to interrupt/periodic QH */ |
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#define QH_NEXT(ehci, dma) \ |
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(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH)) |
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/* for periodic/async schedules and qtd lists, mark end of list */ |
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#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
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/* |
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* Entries in periodic shadow table are pointers to one of four kinds |
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* of data structure. That's dictated by the hardware; a type tag is |
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* encoded in the low bits of the hardware's periodic schedule. Use |
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* Q_NEXT_TYPE to get the tag. |
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* |
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* For entries in the async schedule, the type tag always says "qh". |
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*/ |
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union ehci_shadow { |
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struct ehci_qh *qh; /* Q_TYPE_QH */ |
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struct ehci_itd *itd; /* Q_TYPE_ITD */ |
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struct ehci_sitd *sitd; /* Q_TYPE_SITD */ |
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struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ |
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__hc32 *hw_next; /* (all types) */ |
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void *ptr; |
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}; |
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/*-------------------------------------------------------------------------*/ |
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/* |
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* EHCI Specification 0.95 Section 3.6 |
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* QH: describes control/bulk/interrupt endpoints |
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* See Fig 3-7 "Queue Head Structure Layout". |
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* |
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* These appear in both the async and (for interrupt) periodic schedules. |
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*/ |
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/* first part defined by EHCI spec */ |
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struct ehci_qh_hw { |
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__hc32 hw_next; /* see EHCI 3.6.1 */ |
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__hc32 hw_info1; /* see EHCI 3.6.2 */ |
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#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ |
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#define QH_HEAD (1 << 15) /* Head of async reclamation list */ |
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#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ |
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#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ |
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#define QH_LOW_SPEED (1 << 12) |
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#define QH_FULL_SPEED (0 << 12) |
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#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ |
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__hc32 hw_info2; /* see EHCI 3.6.2 */ |
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#define QH_SMASK 0x000000ff |
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#define QH_CMASK 0x0000ff00 |
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#define QH_HUBADDR 0x007f0000 |
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#define QH_HUBPORT 0x3f800000 |
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#define QH_MULT 0xc0000000 |
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__hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
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/* qtd overlay (hardware parts of a struct ehci_qtd) */ |
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__hc32 hw_qtd_next; |
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__hc32 hw_alt_next; |
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__hc32 hw_token; |
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__hc32 hw_buf[5]; |
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__hc32 hw_buf_hi[5]; |
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} __aligned(32); |
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struct ehci_qh { |
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struct ehci_qh_hw *hw; /* Must come first */ |
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/* the rest is HCD-private */ |
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dma_addr_t qh_dma; /* address of qh */ |
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union ehci_shadow qh_next; /* ptr to qh; or periodic */ |
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struct list_head qtd_list; /* sw qtd list */ |
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struct list_head intr_node; /* list of intr QHs */ |
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struct ehci_qtd *dummy; |
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struct list_head unlink_node; |
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struct ehci_per_sched ps; /* scheduling info */ |
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unsigned unlink_cycle; |
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u8 qh_state; |
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#define QH_STATE_LINKED 1 /* HC sees this */ |
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#define QH_STATE_UNLINK 2 /* HC may still see this */ |
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#define QH_STATE_IDLE 3 /* HC doesn't see this */ |
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#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ |
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#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ |
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u8 xacterrs; /* XactErr retry counter */ |
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#define QH_XACTERR_MAX 32 /* XactErr retry limit */ |
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u8 unlink_reason; |
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#define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ |
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#define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ |
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#define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ |
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#define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ |
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#define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ |
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#define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */ |
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u8 gap_uf; /* uframes split/csplit gap */ |
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unsigned is_out:1; /* bulk or intr OUT */ |
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unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
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unsigned dequeue_during_giveback:1; |
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unsigned should_be_inactive:1; |
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}; |
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/*-------------------------------------------------------------------------*/ |
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|
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/* description of one iso transaction (up to 3 KB data if highspeed) */ |
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struct ehci_iso_packet { |
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/* These will be copied to iTD when scheduling */ |
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u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ |
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__hc32 transaction; /* itd->hw_transaction[i] |= */ |
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u8 cross; /* buf crosses pages */ |
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/* for full speed OUT splits */ |
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u32 buf1; |
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}; |
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/* temporary schedule data for packets from iso urbs (both speeds) |
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* each packet is one logical usb transaction to the device (not TT), |
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* beginning at stream->next_uframe |
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*/ |
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struct ehci_iso_sched { |
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struct list_head td_list; |
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unsigned span; |
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unsigned first_packet; |
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struct ehci_iso_packet packet[]; |
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}; |
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/* |
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* ehci_iso_stream - groups all (s)itds for this endpoint. |
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* acts like a qh would, if EHCI had them for ISO. |
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*/ |
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struct ehci_iso_stream { |
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/* first field matches ehci_hq, but is NULL */ |
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struct ehci_qh_hw *hw; |
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u8 bEndpointAddress; |
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u8 highspeed; |
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struct list_head td_list; /* queued itds/sitds */ |
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struct list_head free_list; /* list of unused itds/sitds */ |
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|
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/* output of (re)scheduling */ |
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struct ehci_per_sched ps; /* scheduling info */ |
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unsigned next_uframe; |
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__hc32 splits; |
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|
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/* the rest is derived from the endpoint descriptor, |
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* including the extra info for hw_bufp[0..2] |
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*/ |
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u16 uperiod; /* period in uframes */ |
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u16 maxp; |
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unsigned bandwidth; |
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|
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/* This is used to initialize iTD's hw_bufp fields */ |
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__hc32 buf0; |
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__hc32 buf1; |
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__hc32 buf2; |
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|
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/* this is used to initialize sITD's tt info */ |
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__hc32 address; |
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}; |
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/*-------------------------------------------------------------------------*/ |
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/* |
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* EHCI Specification 0.95 Section 3.3 |
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* Fig 3-4 "Isochronous Transaction Descriptor (iTD)" |
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* |
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* Schedule records for high speed iso xfers |
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*/ |
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struct ehci_itd { |
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/* first part defined by EHCI spec */ |
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__hc32 hw_next; /* see EHCI 3.3.1 */ |
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__hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ |
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#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
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#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ |
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#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ |
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#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ |
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#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) |
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#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ |
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#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
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__hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ |
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__hc32 hw_bufp_hi[7]; /* Appendix B */ |
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/* the rest is HCD-private */ |
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dma_addr_t itd_dma; /* for this itd */ |
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union ehci_shadow itd_next; /* ptr to periodic q entry */ |
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struct urb *urb; |
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struct ehci_iso_stream *stream; /* endpoint's queue */ |
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struct list_head itd_list; /* list of stream's itds */ |
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/* any/all hw_transactions here may be used by that urb */ |
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unsigned frame; /* where scheduled */ |
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unsigned pg; |
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unsigned index[8]; /* in urb->iso_frame_desc */ |
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} __aligned(32); |
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/*-------------------------------------------------------------------------*/ |
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/* |
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* EHCI Specification 0.95 Section 3.4 |
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* siTD, aka split-transaction isochronous Transfer Descriptor |
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* ... describe full speed iso xfers through TT in hubs |
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* see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) |
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*/ |
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struct ehci_sitd { |
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/* first part defined by EHCI spec */ |
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__hc32 hw_next; |
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/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
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__hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
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__hc32 hw_uframe; /* EHCI table 3-10 */ |
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__hc32 hw_results; /* EHCI table 3-11 */ |
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#define SITD_IOC (1 << 31) /* interrupt on completion */ |
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#define SITD_PAGE (1 << 30) /* buffer 0/1 */ |
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#define SITD_LENGTH(x) (((x) >> 16) & 0x3ff) |
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#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ |
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#define SITD_STS_ERR (1 << 6) /* error from TT */ |
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#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ |
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#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ |
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#define SITD_STS_XACT (1 << 3) /* illegal IN response */ |
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#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ |
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#define SITD_STS_STS (1 << 1) /* split transaction state */ |
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#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
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__hc32 hw_buf[2]; /* EHCI table 3-12 */ |
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__hc32 hw_backpointer; /* EHCI table 3-13 */ |
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__hc32 hw_buf_hi[2]; /* Appendix B */ |
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|
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/* the rest is HCD-private */ |
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dma_addr_t sitd_dma; |
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union ehci_shadow sitd_next; /* ptr to periodic q entry */ |
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struct urb *urb; |
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struct ehci_iso_stream *stream; /* endpoint's queue */ |
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struct list_head sitd_list; /* list of stream's sitds */ |
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unsigned frame; |
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unsigned index; |
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} __aligned(32); |
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/*-------------------------------------------------------------------------*/ |
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/* |
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* EHCI Specification 0.96 Section 3.7 |
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* Periodic Frame Span Traversal Node (FSTN) |
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* |
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* Manages split interrupt transactions (using TT) that span frame boundaries |
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* into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN |
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* makes the HC jump (back) to a QH to scan for fs/ls QH completions until |
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* it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. |
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*/ |
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struct ehci_fstn { |
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__hc32 hw_next; /* any periodic q entry */ |
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__hc32 hw_prev; /* qh or EHCI_LIST_END */ |
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|
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/* the rest is HCD-private */ |
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dma_addr_t fstn_dma; |
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union ehci_shadow fstn_next; /* ptr to periodic q entry */ |
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} __aligned(32); |
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/*-------------------------------------------------------------------------*/ |
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/* |
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* USB-2.0 Specification Sections 11.14 and 11.18 |
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* Scheduling and budgeting split transactions using TTs |
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* |
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* A hub can have a single TT for all its ports, or multiple TTs (one for each |
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* port). The bandwidth and budgeting information for the full/low-speed bus |
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* below each TT is self-contained and independent of the other TTs or the |
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* high-speed bus. |
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* |
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* "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated |
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* to an interrupt or isochronous endpoint for each frame. "Budget" refers to |
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* the best-case estimate of the number of full-speed bytes allocated to an |
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* endpoint for each microframe within an allocated frame. |
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* |
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* Removal of an endpoint invalidates a TT's budget. Instead of trying to |
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* keep an up-to-date record, we recompute the budget when it is needed. |
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*/ |
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struct ehci_tt { |
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u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; |
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struct list_head tt_list; /* List of all ehci_tt's */ |
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struct list_head ps_list; /* Items using this TT */ |
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struct usb_tt *usb_tt; |
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int tt_port; /* TT port number */ |
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}; |
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/*-------------------------------------------------------------------------*/ |
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/* Prepare the PORTSC wakeup flags during controller suspend/resume */ |
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#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ |
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ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup) |
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#define ehci_prepare_ports_for_controller_resume(ehci) \ |
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ehci_adjust_port_wakeup_flags(ehci, false, false) |
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/*-------------------------------------------------------------------------*/ |
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#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT |
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/* |
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* Some EHCI controllers have a Transaction Translator built into the |
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* root hub. This is a non-standard feature. Each controller will need |
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* to add code to the following inline functions, and call them as |
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* needed (mostly in root hub code). |
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*/ |
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#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
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/* Returns the speed of a device attached to a port on the root hub. */ |
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static inline unsigned int |
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ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) |
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{ |
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if (ehci_is_TDI(ehci)) { |
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switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { |
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case 0: |
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return 0; |
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case 1: |
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return USB_PORT_STAT_LOW_SPEED; |
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case 2: |
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default: |
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return USB_PORT_STAT_HIGH_SPEED; |
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} |
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} |
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return USB_PORT_STAT_HIGH_SPEED; |
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} |
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#else |
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#define ehci_is_TDI(e) (0) |
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#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED |
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#endif |
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/*-------------------------------------------------------------------------*/ |
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#ifdef CONFIG_PPC_83xx |
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/* Some Freescale processors have an erratum in which the TT |
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* port number in the queue head was 0..N-1 instead of 1..N. |
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*/ |
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#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) |
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#else |
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#define ehci_has_fsl_portno_bug(e) (0) |
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#endif |
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#define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */ |
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#if defined(CONFIG_PPC_85xx) |
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/* Some Freescale processors have an erratum (USB A-005275) in which |
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* incoming packets get corrupted in HS mode |
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*/ |
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#define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata) |
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#else |
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#define ehci_has_fsl_hs_errata(e) (0) |
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#endif |
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/* |
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* Some Freescale/NXP processors have an erratum (USB A-005697) |
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* in which we need to wait for 10ms for bus to enter suspend mode |
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* after setting SUSP bit. |
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*/ |
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#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata) |
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/* |
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* While most USB host controllers implement their registers in |
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* little-endian format, a minority (celleb companion chip) implement |
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* them in big endian format. |
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* |
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* This attempts to support either format at compile time without a |
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* runtime penalty, or both formats with the additional overhead |
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* of checking a flag bit. |
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* |
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* ehci_big_endian_capbase is a special quirk for controllers that |
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* implement the HC capability registers as separate registers and not |
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* as fields of a 32-bit register. |
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*/ |
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
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#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) |
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#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) |
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#else |
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#define ehci_big_endian_mmio(e) 0 |
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#define ehci_big_endian_capbase(e) 0 |
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#endif |
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/* |
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* Big-endian read/write functions are arch-specific. |
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* Other arches can be added if/when they're needed. |
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*/ |
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#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
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#define readl_be(addr) __raw_readl((__force unsigned *)addr) |
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#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) |
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#endif |
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static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
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__u32 __iomem *regs) |
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{ |
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
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return ehci_big_endian_mmio(ehci) ? |
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readl_be(regs) : |
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readl(regs); |
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#else |
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return readl(regs); |
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#endif |
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} |
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#ifdef CONFIG_SOC_IMX28 |
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static inline void imx28_ehci_writel(const unsigned int val, |
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volatile __u32 __iomem *addr) |
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{ |
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__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); |
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} |
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#else |
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static inline void imx28_ehci_writel(const unsigned int val, |
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volatile __u32 __iomem *addr) |
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{ |
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} |
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#endif |
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static inline void ehci_writel(const struct ehci_hcd *ehci, |
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const unsigned int val, __u32 __iomem *regs) |
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{ |
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
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ehci_big_endian_mmio(ehci) ? |
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writel_be(val, regs) : |
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writel(val, regs); |
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#else |
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if (ehci->imx28_write_fix) |
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imx28_ehci_writel(val, regs); |
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else |
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writel(val, regs); |
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#endif |
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} |
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/* |
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* On certain ppc-44x SoC there is a HW issue, that could only worked around with |
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* explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. |
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* Other common bits are dependent on has_amcc_usb23 quirk flag. |
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*/ |
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#ifdef CONFIG_44x |
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static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) |
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{ |
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u32 hc_control; |
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hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); |
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if (operational) |
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hc_control |= OHCI_USB_OPER; |
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else |
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hc_control |= OHCI_USB_SUSPEND; |
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writel_be(hc_control, ehci->ohci_hcctrl_reg); |
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(void) readl_be(ehci->ohci_hcctrl_reg); |
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} |
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#else |
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static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) |
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{ } |
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#endif |
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/*-------------------------------------------------------------------------*/ |
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|
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/* |
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* The AMCC 440EPx not only implements its EHCI registers in big-endian |
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* format, but also its DMA data structures (descriptors). |
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* |
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* EHCI controllers accessed through PCI work normally (little-endian |
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* everywhere), so we won't bother supporting a BE-only mode for now. |
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*/ |
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC |
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#define ehci_big_endian_desc(e) ((e)->big_endian_desc) |
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/* cpu to ehci */ |
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static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) |
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{ |
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return ehci_big_endian_desc(ehci) |
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? (__force __hc32)cpu_to_be32(x) |
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: (__force __hc32)cpu_to_le32(x); |
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} |
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/* ehci to cpu */ |
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static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) |
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{ |
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return ehci_big_endian_desc(ehci) |
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? be32_to_cpu((__force __be32)x) |
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: le32_to_cpu((__force __le32)x); |
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} |
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static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) |
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{ |
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return ehci_big_endian_desc(ehci) |
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? be32_to_cpup((__force __be32 *)x) |
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: le32_to_cpup((__force __le32 *)x); |
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} |
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#else |
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/* cpu to ehci */ |
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static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) |
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{ |
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return cpu_to_le32(x); |
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} |
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/* ehci to cpu */ |
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static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) |
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{ |
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return le32_to_cpu(x); |
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} |
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static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) |
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{ |
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return le32_to_cpup(x); |
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} |
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#endif |
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/*-------------------------------------------------------------------------*/ |
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#define ehci_dbg(ehci, fmt, args...) \ |
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dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
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#define ehci_err(ehci, fmt, args...) \ |
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dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
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#define ehci_info(ehci, fmt, args...) \ |
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dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
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#define ehci_warn(ehci, fmt, args...) \ |
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dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
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/*-------------------------------------------------------------------------*/ |
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/* Declarations of things exported for use by ehci platform drivers */ |
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|
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struct ehci_driver_overrides { |
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size_t extra_priv_size; |
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int (*reset)(struct usb_hcd *hcd); |
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int (*port_power)(struct usb_hcd *hcd, |
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int portnum, bool enable); |
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}; |
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extern void ehci_init_driver(struct hc_driver *drv, |
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const struct ehci_driver_overrides *over); |
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extern int ehci_setup(struct usb_hcd *hcd); |
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extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, |
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u32 mask, u32 done, int usec); |
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extern int ehci_reset(struct ehci_hcd *ehci); |
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extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); |
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extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); |
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extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, |
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bool suspending, bool do_wakeup); |
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extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
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u16 wIndex, char *buf, u16 wLength); |
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#endif /* __LINUX_EHCI_HCD_H */
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