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751 lines
20 KiB
751 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2005-2009 MontaVista Software, Inc. |
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* Copyright 2008,2012,2015 Freescale Semiconductor, Inc. |
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* |
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* Ported to 834x by Randy Vinson <[email protected]> using code provided |
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* by Hunter Wu. |
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* Power Management support by Dave Liu <[email protected]>, |
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* Jerry Huang <[email protected]> and |
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* Anton Vorontsov <[email protected]>. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/delay.h> |
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#include <linux/pm.h> |
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#include <linux/err.h> |
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#include <linux/usb.h> |
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#include <linux/usb/ehci_def.h> |
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#include <linux/usb/hcd.h> |
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#include <linux/usb/otg.h> |
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#include <linux/platform_device.h> |
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#include <linux/fsl_devices.h> |
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#include <linux/of_platform.h> |
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#include <linux/io.h> |
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#include "ehci.h" |
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#include "ehci-fsl.h" |
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#define DRIVER_DESC "Freescale EHCI Host controller driver" |
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#define DRV_NAME "ehci-fsl" |
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static struct hc_driver __read_mostly fsl_ehci_hc_driver; |
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|
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/* configure so an HC device and id are always provided */ |
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/* always called with process context; sleeping is OK */ |
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|
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/* |
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* fsl_ehci_drv_probe - initialize FSL-based HCDs |
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* @pdev: USB Host Controller being probed |
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* |
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* Context: task context, might sleep |
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* |
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* Allocates basic resources for this USB host controller. |
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*/ |
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static int fsl_ehci_drv_probe(struct platform_device *pdev) |
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{ |
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struct fsl_usb2_platform_data *pdata; |
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struct usb_hcd *hcd; |
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struct resource *res; |
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int irq; |
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int retval; |
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u32 tmp; |
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|
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pr_debug("initializing FSL-SOC USB Controller\n"); |
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/* Need platform data for setup */ |
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pdata = dev_get_platdata(&pdev->dev); |
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if (!pdata) { |
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dev_err(&pdev->dev, |
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"No platform data for %s.\n", dev_name(&pdev->dev)); |
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return -ENODEV; |
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} |
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|
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/* |
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* This is a host mode driver, verify that we're supposed to be |
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* in host mode. |
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*/ |
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if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || |
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(pdata->operating_mode == FSL_USB2_MPH_HOST) || |
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(pdata->operating_mode == FSL_USB2_DR_OTG))) { |
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dev_err(&pdev->dev, |
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"Non Host Mode configured for %s. Wrong driver linked.\n", |
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dev_name(&pdev->dev)); |
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return -ENODEV; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
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if (!res) { |
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dev_err(&pdev->dev, |
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"Found HC with no IRQ. Check %s setup!\n", |
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dev_name(&pdev->dev)); |
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return -ENODEV; |
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} |
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irq = res->start; |
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hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent, |
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&pdev->dev, dev_name(&pdev->dev), NULL); |
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if (!hcd) { |
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retval = -ENOMEM; |
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goto err1; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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hcd->regs = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(hcd->regs)) { |
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retval = PTR_ERR(hcd->regs); |
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goto err2; |
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} |
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hcd->rsrc_start = res->start; |
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hcd->rsrc_len = resource_size(res); |
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pdata->regs = hcd->regs; |
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if (pdata->power_budget) |
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hcd->power_budget = pdata->power_budget; |
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/* |
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* do platform specific init: check the clock, grab/config pins, etc. |
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*/ |
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if (pdata->init && pdata->init(pdev)) { |
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retval = -ENODEV; |
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goto err2; |
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} |
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/* Enable USB controller, 83xx or 8536 */ |
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if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) { |
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tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); |
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tmp &= ~CONTROL_REGISTER_W1C_MASK; |
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tmp |= 0x4; |
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iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); |
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} |
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/* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */ |
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if (pdata->controller_ver == FSL_USB_VER_2_5 && |
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pdata->phy_mode == FSL_USB2_PHY_ULPI) |
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iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL); |
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/* |
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* Enable UTMI phy and program PTS field in UTMI mode before asserting |
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* controller reset for USB Controller version 2.5 |
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*/ |
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if (pdata->has_fsl_erratum_a007792) { |
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tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); |
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tmp &= ~CONTROL_REGISTER_W1C_MASK; |
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tmp |= CTRL_UTMI_PHY_EN; |
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iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); |
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writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); |
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} |
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/* Don't need to set host mode here. It will be done by tdi_reset() */ |
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retval = usb_add_hcd(hcd, irq, IRQF_SHARED); |
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if (retval != 0) |
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goto err2; |
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device_wakeup_enable(hcd->self.controller); |
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#ifdef CONFIG_USB_OTG |
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if (pdata->operating_mode == FSL_USB2_DR_OTG) { |
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struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); |
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dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", |
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hcd, ehci, hcd->usb_phy); |
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if (!IS_ERR_OR_NULL(hcd->usb_phy)) { |
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retval = otg_set_host(hcd->usb_phy->otg, |
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&ehci_to_hcd(ehci)->self); |
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if (retval) { |
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usb_put_phy(hcd->usb_phy); |
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goto err2; |
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} |
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} else { |
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dev_err(&pdev->dev, "can't find phy\n"); |
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retval = -ENODEV; |
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goto err2; |
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} |
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hcd->skip_phy_initialization = 1; |
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} |
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#endif |
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return retval; |
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err2: |
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usb_put_hcd(hcd); |
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err1: |
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dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); |
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if (pdata->exit) |
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pdata->exit(pdev); |
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return retval; |
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} |
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static bool usb_phy_clk_valid(struct usb_hcd *hcd) |
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{ |
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void __iomem *non_ehci = hcd->regs; |
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bool ret = true; |
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if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) |
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ret = false; |
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return ret; |
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} |
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static int ehci_fsl_setup_phy(struct usb_hcd *hcd, |
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enum fsl_usb2_phy_modes phy_mode, |
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unsigned int port_offset) |
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{ |
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u32 portsc, tmp; |
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struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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void __iomem *non_ehci = hcd->regs; |
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struct device *dev = hcd->self.controller; |
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struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
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if (pdata->controller_ver < 0) { |
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dev_warn(hcd->self.controller, "Could not get controller version\n"); |
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return -ENODEV; |
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} |
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portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); |
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portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); |
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switch (phy_mode) { |
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case FSL_USB2_PHY_ULPI: |
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if (pdata->have_sysif_regs && pdata->controller_ver) { |
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/* controller version 1.6 or above */ |
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/* turn off UTMI PHY first */ |
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tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
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tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); |
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iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); |
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/* then turn on ULPI and enable USB controller */ |
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tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
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tmp &= ~CONTROL_REGISTER_W1C_MASK; |
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tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; |
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iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); |
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} |
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portsc |= PORT_PTS_ULPI; |
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break; |
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case FSL_USB2_PHY_SERIAL: |
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portsc |= PORT_PTS_SERIAL; |
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break; |
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case FSL_USB2_PHY_UTMI_WIDE: |
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portsc |= PORT_PTS_PTW; |
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fallthrough; |
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case FSL_USB2_PHY_UTMI: |
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/* Presence of this node "has_fsl_erratum_a006918" |
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* in device-tree is used to stop USB controller |
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* initialization in Linux |
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*/ |
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if (pdata->has_fsl_erratum_a006918) { |
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dev_warn(dev, "USB PHY clock invalid\n"); |
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return -EINVAL; |
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} |
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fallthrough; |
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case FSL_USB2_PHY_UTMI_DUAL: |
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/* PHY_CLK_VALID bit is de-featured from all controller |
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* versions below 2.4 and is to be checked only for |
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* internal UTMI phy |
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*/ |
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if (pdata->controller_ver > FSL_USB_VER_2_4 && |
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pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) { |
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dev_err(dev, "USB PHY clock invalid\n"); |
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return -EINVAL; |
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} |
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if (pdata->have_sysif_regs && pdata->controller_ver) { |
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/* controller version 1.6 or above */ |
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tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
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tmp &= ~CONTROL_REGISTER_W1C_MASK; |
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tmp |= UTMI_PHY_EN; |
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iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); |
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mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to |
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become stable - 10ms*/ |
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} |
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/* enable UTMI PHY */ |
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if (pdata->have_sysif_regs) { |
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tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
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tmp &= ~CONTROL_REGISTER_W1C_MASK; |
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tmp |= CTRL_UTMI_PHY_EN; |
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iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); |
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} |
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portsc |= PORT_PTS_UTMI; |
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break; |
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case FSL_USB2_PHY_NONE: |
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break; |
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} |
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if (pdata->have_sysif_regs && |
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pdata->controller_ver > FSL_USB_VER_1_6 && |
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!usb_phy_clk_valid(hcd)) { |
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dev_warn(hcd->self.controller, "USB PHY clock invalid\n"); |
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return -EINVAL; |
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} |
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ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); |
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if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { |
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tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
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tmp &= ~CONTROL_REGISTER_W1C_MASK; |
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tmp |= USB_CTRL_USB_EN; |
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iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); |
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} |
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return 0; |
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} |
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static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) |
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{ |
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struct usb_hcd *hcd = ehci_to_hcd(ehci); |
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struct fsl_usb2_platform_data *pdata; |
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void __iomem *non_ehci = hcd->regs; |
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pdata = dev_get_platdata(hcd->self.controller); |
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if (pdata->have_sysif_regs) { |
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/* |
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* Turn on cache snooping hardware, since some PowerPC platforms |
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* wholly rely on hardware to deal with cache coherent |
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*/ |
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/* Setup Snooping for all the 4GB space */ |
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/* SNOOP1 starts from 0x0, size 2G */ |
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iowrite32be(0x0 | SNOOP_SIZE_2GB, |
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non_ehci + FSL_SOC_USB_SNOOP1); |
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/* SNOOP2 starts from 0x80000000, size 2G */ |
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iowrite32be(0x80000000 | SNOOP_SIZE_2GB, |
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non_ehci + FSL_SOC_USB_SNOOP2); |
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} |
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/* Deal with USB erratum A-005275 */ |
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if (pdata->has_fsl_erratum_a005275 == 1) |
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ehci->has_fsl_hs_errata = 1; |
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if (pdata->has_fsl_erratum_a005697 == 1) |
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ehci->has_fsl_susp_errata = 1; |
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if ((pdata->operating_mode == FSL_USB2_DR_HOST) || |
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(pdata->operating_mode == FSL_USB2_DR_OTG)) |
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) |
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return -EINVAL; |
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if (pdata->operating_mode == FSL_USB2_MPH_HOST) { |
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/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ |
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if (pdata->has_fsl_erratum_14 == 1) |
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ehci->has_fsl_port_bug = 1; |
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if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) |
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) |
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return -EINVAL; |
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if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) |
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) |
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return -EINVAL; |
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} |
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if (pdata->have_sysif_regs) { |
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#ifdef CONFIG_FSL_SOC_BOOKE |
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iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL); |
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iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH); |
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#else |
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iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL); |
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iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH); |
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#endif |
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iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL); |
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} |
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return 0; |
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} |
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/* called after powerup, by probe or system-pm "wakeup" */ |
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static int ehci_fsl_reinit(struct ehci_hcd *ehci) |
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{ |
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if (ehci_fsl_usb_setup(ehci)) |
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return -EINVAL; |
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return 0; |
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} |
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/* called during probe() after chip reset completes */ |
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static int ehci_fsl_setup(struct usb_hcd *hcd) |
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{ |
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struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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int retval; |
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struct fsl_usb2_platform_data *pdata; |
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struct device *dev; |
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dev = hcd->self.controller; |
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pdata = dev_get_platdata(hcd->self.controller); |
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ehci->big_endian_desc = pdata->big_endian_desc; |
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ehci->big_endian_mmio = pdata->big_endian_mmio; |
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/* EHCI registers start at offset 0x100 */ |
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ehci->caps = hcd->regs + 0x100; |
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#ifdef CONFIG_PPC_83xx |
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/* |
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* Deal with MPC834X that need port power to be cycled after the power |
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* fault condition is removed. Otherwise the state machine does not |
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* reflect PORTSC[CSC] correctly. |
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*/ |
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ehci->need_oc_pp_cycle = 1; |
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#endif |
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hcd->has_tt = 1; |
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retval = ehci_setup(hcd); |
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if (retval) |
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return retval; |
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if (of_device_is_compatible(dev->parent->of_node, |
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"fsl,mpc5121-usb2-dr")) { |
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/* |
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* set SBUSCFG:AHBBRST so that control msgs don't |
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* fail when doing heavy PATA writes. |
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*/ |
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ehci_writel(ehci, SBUSCFG_INCR8, |
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hcd->regs + FSL_SOC_USB_SBUSCFG); |
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} |
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retval = ehci_fsl_reinit(ehci); |
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return retval; |
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} |
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struct ehci_fsl { |
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struct ehci_hcd ehci; |
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#ifdef CONFIG_PM |
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/* Saved USB PHY settings, need to restore after deep sleep. */ |
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u32 usb_ctrl; |
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#endif |
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}; |
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#ifdef CONFIG_PM |
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#ifdef CONFIG_PPC_MPC512x |
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static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) |
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{ |
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struct usb_hcd *hcd = dev_get_drvdata(dev); |
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struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
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u32 tmp; |
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#ifdef CONFIG_DYNAMIC_DEBUG |
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u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); |
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mode &= USBMODE_CM_MASK; |
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tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ |
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dev_dbg(dev, "suspend=%d already_suspended=%d " |
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"mode=%d usbcmd %08x\n", pdata->suspended, |
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pdata->already_suspended, mode, tmp); |
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#endif |
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/* |
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* If the controller is already suspended, then this must be a |
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* PM suspend. Remember this fact, so that we will leave the |
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* controller suspended at PM resume time. |
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*/ |
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if (pdata->suspended) { |
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dev_dbg(dev, "already suspended, leaving early\n"); |
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pdata->already_suspended = 1; |
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return 0; |
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} |
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dev_dbg(dev, "suspending...\n"); |
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|
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ehci->rh_state = EHCI_RH_SUSPENDED; |
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dev->power.power_state = PMSG_SUSPEND; |
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|
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/* ignore non-host interrupts */ |
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
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|
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/* stop the controller */ |
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tmp = ehci_readl(ehci, &ehci->regs->command); |
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tmp &= ~CMD_RUN; |
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ehci_writel(ehci, tmp, &ehci->regs->command); |
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|
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/* save EHCI registers */ |
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pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); |
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pdata->pm_command &= ~CMD_RUN; |
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pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); |
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pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); |
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pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); |
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pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); |
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pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); |
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pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); |
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pdata->pm_configured_flag = |
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ehci_readl(ehci, &ehci->regs->configured_flag); |
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pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); |
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pdata->pm_usbgenctrl = ehci_readl(ehci, |
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hcd->regs + FSL_SOC_USB_USBGENCTRL); |
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|
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/* clear the W1C bits */ |
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pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); |
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|
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pdata->suspended = 1; |
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|
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/* clear PP to cut power to the port */ |
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tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); |
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tmp &= ~PORT_POWER; |
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ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); |
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|
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return 0; |
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} |
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|
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static int ehci_fsl_mpc512x_drv_resume(struct device *dev) |
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{ |
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struct usb_hcd *hcd = dev_get_drvdata(dev); |
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struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
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u32 tmp; |
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|
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dev_dbg(dev, "suspend=%d already_suspended=%d\n", |
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pdata->suspended, pdata->already_suspended); |
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|
|
/* |
|
* If the controller was already suspended at suspend time, |
|
* then don't resume it now. |
|
*/ |
|
if (pdata->already_suspended) { |
|
dev_dbg(dev, "already suspended, leaving early\n"); |
|
pdata->already_suspended = 0; |
|
return 0; |
|
} |
|
|
|
if (!pdata->suspended) { |
|
dev_dbg(dev, "not suspended, leaving early\n"); |
|
return 0; |
|
} |
|
|
|
pdata->suspended = 0; |
|
|
|
dev_dbg(dev, "resuming...\n"); |
|
|
|
/* set host mode */ |
|
tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); |
|
ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); |
|
|
|
ehci_writel(ehci, pdata->pm_usbgenctrl, |
|
hcd->regs + FSL_SOC_USB_USBGENCTRL); |
|
ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, |
|
hcd->regs + FSL_SOC_USB_ISIPHYCTRL); |
|
|
|
ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); |
|
|
|
/* restore EHCI registers */ |
|
ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); |
|
ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); |
|
ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); |
|
ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); |
|
ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); |
|
ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); |
|
ehci_writel(ehci, pdata->pm_configured_flag, |
|
&ehci->regs->configured_flag); |
|
ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); |
|
|
|
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
|
ehci->rh_state = EHCI_RH_RUNNING; |
|
dev->power.power_state = PMSG_ON; |
|
|
|
tmp = ehci_readl(ehci, &ehci->regs->command); |
|
tmp |= CMD_RUN; |
|
ehci_writel(ehci, tmp, &ehci->regs->command); |
|
|
|
usb_hcd_resume_root_hub(hcd); |
|
|
|
return 0; |
|
} |
|
#else |
|
static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
|
|
static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
#endif /* CONFIG_PPC_MPC512x */ |
|
|
|
static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) |
|
{ |
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
|
|
|
return container_of(ehci, struct ehci_fsl, ehci); |
|
} |
|
|
|
static int ehci_fsl_drv_suspend(struct device *dev) |
|
{ |
|
struct usb_hcd *hcd = dev_get_drvdata(dev); |
|
struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); |
|
void __iomem *non_ehci = hcd->regs; |
|
|
|
if (of_device_is_compatible(dev->parent->of_node, |
|
"fsl,mpc5121-usb2-dr")) { |
|
return ehci_fsl_mpc512x_drv_suspend(dev); |
|
} |
|
|
|
ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), |
|
device_may_wakeup(dev)); |
|
if (!fsl_deep_sleep()) |
|
return 0; |
|
|
|
ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
|
return 0; |
|
} |
|
|
|
static int ehci_fsl_drv_resume(struct device *dev) |
|
{ |
|
struct usb_hcd *hcd = dev_get_drvdata(dev); |
|
struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); |
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
|
void __iomem *non_ehci = hcd->regs; |
|
|
|
if (of_device_is_compatible(dev->parent->of_node, |
|
"fsl,mpc5121-usb2-dr")) { |
|
return ehci_fsl_mpc512x_drv_resume(dev); |
|
} |
|
|
|
ehci_prepare_ports_for_controller_resume(ehci); |
|
if (!fsl_deep_sleep()) |
|
return 0; |
|
|
|
usb_root_hub_lost_power(hcd->self.root_hub); |
|
|
|
/* Restore USB PHY settings and enable the controller. */ |
|
iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL); |
|
|
|
ehci_reset(ehci); |
|
ehci_fsl_reinit(ehci); |
|
|
|
return 0; |
|
} |
|
|
|
static int ehci_fsl_drv_restore(struct device *dev) |
|
{ |
|
struct usb_hcd *hcd = dev_get_drvdata(dev); |
|
|
|
usb_root_hub_lost_power(hcd->self.root_hub); |
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops ehci_fsl_pm_ops = { |
|
.suspend = ehci_fsl_drv_suspend, |
|
.resume = ehci_fsl_drv_resume, |
|
.restore = ehci_fsl_drv_restore, |
|
}; |
|
|
|
#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) |
|
#else |
|
#define EHCI_FSL_PM_OPS NULL |
|
#endif /* CONFIG_PM */ |
|
|
|
#ifdef CONFIG_USB_OTG |
|
static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) |
|
{ |
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
|
u32 status; |
|
|
|
if (!port) |
|
return -EINVAL; |
|
|
|
port--; |
|
|
|
/* start port reset before HNP protocol time out */ |
|
status = readl(&ehci->regs->port_status[port]); |
|
if (!(status & PORT_CONNECT)) |
|
return -ENODEV; |
|
|
|
/* hub_wq will finish the reset later */ |
|
if (ehci_is_TDI(ehci)) { |
|
writel(PORT_RESET | |
|
(status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), |
|
&ehci->regs->port_status[port]); |
|
} else { |
|
writel(PORT_RESET, &ehci->regs->port_status[port]); |
|
} |
|
|
|
return 0; |
|
} |
|
#else |
|
#define ehci_start_port_reset NULL |
|
#endif /* CONFIG_USB_OTG */ |
|
|
|
static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = { |
|
.extra_priv_size = sizeof(struct ehci_fsl), |
|
.reset = ehci_fsl_setup, |
|
}; |
|
|
|
/** |
|
* fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs |
|
* @pdev: USB Host Controller being removed |
|
* |
|
* Context: task context, might sleep |
|
* |
|
* Reverses the effect of usb_hcd_fsl_probe(). |
|
*/ |
|
static int fsl_ehci_drv_remove(struct platform_device *pdev) |
|
{ |
|
struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); |
|
struct usb_hcd *hcd = platform_get_drvdata(pdev); |
|
|
|
if (!IS_ERR_OR_NULL(hcd->usb_phy)) { |
|
otg_set_host(hcd->usb_phy->otg, NULL); |
|
usb_put_phy(hcd->usb_phy); |
|
} |
|
|
|
usb_remove_hcd(hcd); |
|
|
|
/* |
|
* do platform specific un-initialization: |
|
* release iomux pins, disable clock, etc. |
|
*/ |
|
if (pdata->exit) |
|
pdata->exit(pdev); |
|
usb_put_hcd(hcd); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver ehci_fsl_driver = { |
|
.probe = fsl_ehci_drv_probe, |
|
.remove = fsl_ehci_drv_remove, |
|
.shutdown = usb_hcd_platform_shutdown, |
|
.driver = { |
|
.name = "fsl-ehci", |
|
.pm = EHCI_FSL_PM_OPS, |
|
}, |
|
}; |
|
|
|
static int __init ehci_fsl_init(void) |
|
{ |
|
if (usb_disabled()) |
|
return -ENODEV; |
|
|
|
pr_info(DRV_NAME ": " DRIVER_DESC "\n"); |
|
|
|
ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); |
|
|
|
fsl_ehci_hc_driver.product_desc = |
|
"Freescale On-Chip EHCI Host Controller"; |
|
fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; |
|
|
|
|
|
return platform_driver_register(&ehci_fsl_driver); |
|
} |
|
module_init(ehci_fsl_init); |
|
|
|
static void __exit ehci_fsl_cleanup(void) |
|
{ |
|
platform_driver_unregister(&ehci_fsl_driver); |
|
} |
|
module_exit(ehci_fsl_cleanup); |
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
|