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854 lines
24 KiB
854 lines
24 KiB
/* ========================================================================== |
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* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $ |
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* $Revision: #12 $ |
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* $Date: 2011/10/26 $ |
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* $Change: 1873028 $ |
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* |
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* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
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* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
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* otherwise expressly agreed to in writing between Synopsys and you. |
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* |
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* The Software IS NOT an item of Licensed Software or Licensed Product under |
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* any End User Software License Agreement or Agreement for Licensed Product |
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* with Synopsys or any supplement thereto. You are permitted to use and |
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* redistribute this Software in source and binary forms, with or without |
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* modification, provided that redistributions of source code must retain this |
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* notice. You may not view, use, disclose, copy or distribute this file or |
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* any information contained herein except pursuant to this license grant from |
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* Synopsys. If you do not agree with this notice, including the disclaimer |
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* below, then you are not authorized to use the Software. |
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* |
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
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* DAMAGE. |
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* ========================================================================== */ |
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#include "dwc_os.h" |
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#include "dwc_otg_regs.h" |
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#include "dwc_otg_cil.h" |
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#include "dwc_otg_adp.h" |
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|
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/** @file |
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* |
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* This file contains the most of the Attach Detect Protocol implementation for |
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* the driver to support OTG Rev2.0. |
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* |
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*/ |
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void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value) |
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{ |
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adpctl_data_t adpctl; |
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adpctl.d32 = value; |
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adpctl.b.ar = 0x2; |
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DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); |
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while (adpctl.b.ar) { |
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adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); |
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} |
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} |
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/** |
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* Function is called to read ADP registers |
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*/ |
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uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if) |
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{ |
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adpctl_data_t adpctl; |
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adpctl.d32 = 0; |
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adpctl.b.ar = 0x1; |
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DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); |
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while (adpctl.b.ar) { |
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adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); |
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} |
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return adpctl.d32; |
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} |
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/** |
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* Function is called to read ADPCTL register and filter Write-clear bits |
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*/ |
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uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if) |
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{ |
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adpctl_data_t adpctl; |
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adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
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adpctl.b.adp_tmout_int = 0; |
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adpctl.b.adp_prb_int = 0; |
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adpctl.b.adp_tmout_int = 0; |
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return adpctl.d32; |
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} |
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/** |
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* Function is called to write ADP registers |
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*/ |
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void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr, |
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uint32_t set) |
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{ |
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dwc_otg_adp_write_reg(core_if, |
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(dwc_otg_adp_read_reg(core_if) & (~clr)) | set); |
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} |
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static void adp_sense_timeout(void *ptr) |
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{ |
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dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; |
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core_if->adp.sense_timer_started = 0; |
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DWC_PRINTF("ADP SENSE TIMEOUT\n"); |
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if (core_if->adp_enable) { |
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dwc_otg_adp_sense_stop(core_if); |
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dwc_otg_adp_probe_start(core_if); |
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} |
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} |
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/** |
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* This function is called when the ADP vbus timer expires. Timeout is 1.1s. |
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*/ |
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static void adp_vbuson_timeout(void *ptr) |
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{ |
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gpwrdn_data_t gpwrdn; |
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dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; |
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hprt0_data_t hprt0 = {.d32 = 0 }; |
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pcgcctl_data_t pcgcctl = {.d32 = 0 }; |
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DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__); |
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if (core_if) { |
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core_if->adp.vbuson_timer_started = 0; |
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/* Turn off vbus */ |
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hprt0.b.prtpwr = 1; |
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DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0); |
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gpwrdn.d32 = 0; |
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/* Power off the core */ |
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if (core_if->power_down == 2) { |
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/* Enable Wakeup Logic */ |
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// gpwrdn.b.wkupactiv = 1; |
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gpwrdn.b.pmuactv = 0; |
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gpwrdn.b.pwrdnrstn = 1; |
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gpwrdn.b.pwrdnclmp = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, |
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gpwrdn.d32); |
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/* Suspend the Phy Clock */ |
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pcgcctl.b.stoppclk = 1; |
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DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); |
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/* Switch on VDD */ |
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// gpwrdn.b.wkupactiv = 1; |
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gpwrdn.b.pmuactv = 1; |
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gpwrdn.b.pwrdnrstn = 1; |
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gpwrdn.b.pwrdnclmp = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, |
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gpwrdn.d32); |
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} else { |
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/* Enable Power Down Logic */ |
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gpwrdn.b.pmuintsel = 1; |
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gpwrdn.b.pmuactv = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); |
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} |
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/* Power off the core */ |
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if (core_if->power_down == 2) { |
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gpwrdn.d32 = 0; |
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gpwrdn.b.pwrdnswtch = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, |
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gpwrdn.d32, 0); |
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} |
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/* Unmask SRP detected interrupt from Power Down Logic */ |
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gpwrdn.d32 = 0; |
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gpwrdn.b.srp_det_msk = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); |
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dwc_otg_adp_probe_start(core_if); |
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dwc_otg_dump_global_registers(core_if); |
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dwc_otg_dump_host_registers(core_if); |
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} |
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} |
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/** |
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* Start the ADP Initial Probe timer to detect if Port Connected interrupt is |
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* not asserted within 1.1 seconds. |
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* |
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* @param core_if the pointer to core_if strucure. |
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*/ |
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void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if) |
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{ |
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core_if->adp.vbuson_timer_started = 1; |
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if (core_if->adp.vbuson_timer) |
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{ |
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DWC_PRINTF("SCHEDULING VBUSON TIMER\n"); |
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/* 1.1 secs + 60ms necessary for cil_hcd_start*/ |
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DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160); |
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} else { |
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DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer); |
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} |
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} |
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#if 0 |
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/** |
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* Masks all DWC OTG core interrupts |
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* |
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*/ |
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static void mask_all_interrupts(dwc_otg_core_if_t * core_if) |
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{ |
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int i; |
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gahbcfg_data_t ahbcfg = {.d32 = 0 }; |
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/* Mask Host Interrupts */ |
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/* Clear and disable HCINTs */ |
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for (i = 0; i < core_if->core_params->host_channels; i++) { |
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DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0); |
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DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF); |
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} |
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/* Clear and disable HAINT */ |
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DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000); |
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DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF); |
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/* Mask Device Interrupts */ |
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if (!core_if->multiproc_int_enable) { |
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/* Clear and disable IN Endpoint interrupts */ |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0); |
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for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { |
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DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> |
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diepint, 0xFFFFFFFF); |
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} |
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/* Clear and disable OUT Endpoint interrupts */ |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0); |
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for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { |
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DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> |
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doepint, 0xFFFFFFFF); |
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} |
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/* Clear and disable DAINT */ |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint, |
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0xFFFFFFFF); |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0); |
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} else { |
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for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> |
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diepeachintmsk[i], 0); |
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DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> |
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diepint, 0xFFFFFFFF); |
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} |
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for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> |
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doepeachintmsk[i], 0); |
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DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> |
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doepint, 0xFFFFFFFF); |
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} |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, |
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0); |
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DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint, |
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0xFFFFFFFF); |
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} |
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/* Disable interrupts */ |
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ahbcfg.b.glblintrmsk = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); |
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/* Disable all interrupts. */ |
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DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); |
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/* Clear any pending interrupts */ |
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DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); |
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/* Clear any pending OTG Interrupts */ |
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DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF); |
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} |
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/** |
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* Unmask Port Connection Detected interrupt |
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* |
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*/ |
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static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if) |
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{ |
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gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 }; |
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DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); |
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} |
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#endif |
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/** |
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* Starts the ADP Probing |
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* |
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* @param core_if the pointer to core_if structure. |
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*/ |
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uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if) |
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{ |
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adpctl_data_t adpctl = {.d32 = 0}; |
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gpwrdn_data_t gpwrdn; |
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#if 0 |
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adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1, |
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.b.adp_sns_int = 1, b.adp_tmout_int}; |
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#endif |
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dwc_otg_disable_global_interrupts(core_if); |
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DWC_PRINTF("ADP Probe Start\n"); |
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core_if->adp.probe_enabled = 1; |
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adpctl.b.adpres = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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while (adpctl.b.adpres) { |
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adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
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} |
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adpctl.d32 = 0; |
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gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); |
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/* In Host mode unmask SRP detected interrupt */ |
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gpwrdn.d32 = 0; |
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gpwrdn.b.sts_chngint_msk = 1; |
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if (!gpwrdn.b.idsts) { |
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gpwrdn.b.srp_det_msk = 1; |
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} |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); |
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adpctl.b.adp_tmout_int_msk = 1; |
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adpctl.b.adp_prb_int_msk = 1; |
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adpctl.b.prb_dschg = 1; |
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adpctl.b.prb_delta = 1; |
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adpctl.b.prb_per = 1; |
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adpctl.b.adpen = 1; |
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adpctl.b.enaprb = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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DWC_PRINTF("ADP Probe Finish\n"); |
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return 0; |
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} |
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/** |
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* Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted |
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* within 3 seconds. |
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* |
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* @param core_if the pointer to core_if strucure. |
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*/ |
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void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if) |
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{ |
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core_if->adp.sense_timer_started = 1; |
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DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ ); |
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} |
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/** |
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* Starts the ADP Sense |
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* |
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* @param core_if the pointer to core_if strucure. |
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*/ |
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uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if) |
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{ |
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adpctl_data_t adpctl; |
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DWC_PRINTF("ADP Sense Start\n"); |
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/* Unmask ADP sense interrupt and mask all other from the core */ |
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adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); |
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adpctl.b.adp_sns_int_msk = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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dwc_otg_disable_global_interrupts(core_if); // vahrama |
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/* Set ADP reset bit*/ |
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adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); |
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adpctl.b.adpres = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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while (adpctl.b.adpres) { |
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adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
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} |
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adpctl.b.adpres = 0; |
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adpctl.b.adpen = 1; |
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adpctl.b.enasns = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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dwc_otg_adp_sense_timer_start(core_if); |
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return 0; |
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} |
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/** |
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* Stops the ADP Probing |
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* |
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* @param core_if the pointer to core_if strucure. |
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*/ |
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uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if) |
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{ |
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adpctl_data_t adpctl; |
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DWC_PRINTF("Stop ADP probe\n"); |
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core_if->adp.probe_enabled = 0; |
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core_if->adp.probe_counter = 0; |
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adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
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adpctl.b.adpen = 0; |
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adpctl.b.adp_prb_int = 1; |
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adpctl.b.adp_tmout_int = 1; |
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adpctl.b.adp_sns_int = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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return 0; |
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} |
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/** |
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* Stops the ADP Sensing |
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* |
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* @param core_if the pointer to core_if strucure. |
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*/ |
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uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if) |
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{ |
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adpctl_data_t adpctl; |
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core_if->adp.sense_enabled = 0; |
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adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); |
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adpctl.b.enasns = 0; |
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adpctl.b.adp_sns_int = 1; |
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dwc_otg_adp_write_reg(core_if, adpctl.d32); |
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return 0; |
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} |
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/** |
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* Called to turn on the VBUS after initial ADP probe in host mode. |
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* If port power was already enabled in cil_hcd_start function then |
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* only schedule a timer. |
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* |
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* @param core_if the pointer to core_if structure. |
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*/ |
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void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if) |
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{ |
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hprt0_data_t hprt0 = {.d32 = 0 }; |
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hprt0.d32 = dwc_otg_read_hprt0(core_if); |
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DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr); |
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|
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if (hprt0.b.prtpwr == 0) { |
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hprt0.b.prtpwr = 1; |
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//DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); |
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} |
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dwc_otg_adp_vbuson_timer_start(core_if); |
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} |
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/** |
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* Called right after driver is loaded |
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* to perform initial actions for ADP |
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* |
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* @param core_if the pointer to core_if structure. |
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* @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN |
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*/ |
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void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host) |
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{ |
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gpwrdn_data_t gpwrdn; |
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|
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DWC_PRINTF("ADP Initial Start\n"); |
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core_if->adp.adp_started = 1; |
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|
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DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); |
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dwc_otg_disable_global_interrupts(core_if); |
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if (is_host) { |
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DWC_PRINTF("HOST MODE\n"); |
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/* Enable Power Down Logic Interrupt*/ |
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gpwrdn.d32 = 0; |
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gpwrdn.b.pmuintsel = 1; |
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gpwrdn.b.pmuactv = 1; |
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DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); |
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/* Initialize first ADP probe to obtain Ramp Time value */ |
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core_if->adp.initial_probe = 1; |
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dwc_otg_adp_probe_start(core_if); |
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} else { |
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gotgctl_data_t gotgctl; |
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gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); |
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DWC_PRINTF("DEVICE MODE\n"); |
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if (gotgctl.b.bsesvld == 0) { |
|
/* Enable Power Down Logic Interrupt*/ |
|
gpwrdn.d32 = 0; |
|
DWC_PRINTF("VBUS is not valid - start ADP probe\n"); |
|
gpwrdn.b.pmuintsel = 1; |
|
gpwrdn.b.pmuactv = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); |
|
core_if->adp.initial_probe = 1; |
|
dwc_otg_adp_probe_start(core_if); |
|
} else { |
|
DWC_PRINTF("VBUS is valid - initialize core as a Device\n"); |
|
core_if->op_state = B_PERIPHERAL; |
|
dwc_otg_core_init(core_if); |
|
dwc_otg_enable_global_interrupts(core_if); |
|
cil_pcd_start(core_if); |
|
dwc_otg_dump_global_registers(core_if); |
|
dwc_otg_dump_dev_registers(core_if); |
|
} |
|
} |
|
} |
|
|
|
void dwc_otg_adp_init(dwc_otg_core_if_t * core_if) |
|
{ |
|
core_if->adp.adp_started = 0; |
|
core_if->adp.initial_probe = 0; |
|
core_if->adp.probe_timer_values[0] = -1; |
|
core_if->adp.probe_timer_values[1] = -1; |
|
core_if->adp.probe_enabled = 0; |
|
core_if->adp.sense_enabled = 0; |
|
core_if->adp.sense_timer_started = 0; |
|
core_if->adp.vbuson_timer_started = 0; |
|
core_if->adp.probe_counter = 0; |
|
core_if->adp.gpwrdn = 0; |
|
core_if->adp.attached = DWC_OTG_ADP_UNKOWN; |
|
/* Initialize timers */ |
|
core_if->adp.sense_timer = |
|
DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if); |
|
core_if->adp.vbuson_timer = |
|
DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if); |
|
if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer) |
|
{ |
|
DWC_ERROR("Could not allocate memory for ADP timers\n"); |
|
} |
|
} |
|
|
|
void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if) |
|
{ |
|
gpwrdn_data_t gpwrdn = { .d32 = 0 }; |
|
gpwrdn.b.pmuintsel = 1; |
|
gpwrdn.b.pmuactv = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); |
|
|
|
if (core_if->adp.probe_enabled) |
|
dwc_otg_adp_probe_stop(core_if); |
|
if (core_if->adp.sense_enabled) |
|
dwc_otg_adp_sense_stop(core_if); |
|
if (core_if->adp.sense_timer_started) |
|
DWC_TIMER_CANCEL(core_if->adp.sense_timer); |
|
if (core_if->adp.vbuson_timer_started) |
|
DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); |
|
DWC_TIMER_FREE(core_if->adp.sense_timer); |
|
DWC_TIMER_FREE(core_if->adp.vbuson_timer); |
|
} |
|
|
|
///////////////////////////////////////////////////////////////////// |
|
////////////// ADP Interrupt Handlers /////////////////////////////// |
|
///////////////////////////////////////////////////////////////////// |
|
/** |
|
* This function sets Ramp Timer values |
|
*/ |
|
static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val) |
|
{ |
|
if (core_if->adp.probe_timer_values[0] == -1) { |
|
core_if->adp.probe_timer_values[0] = val; |
|
core_if->adp.probe_timer_values[1] = -1; |
|
return 1; |
|
} else { |
|
core_if->adp.probe_timer_values[1] = |
|
core_if->adp.probe_timer_values[0]; |
|
core_if->adp.probe_timer_values[0] = val; |
|
return 0; |
|
} |
|
} |
|
|
|
/** |
|
* This function compares Ramp Timer values |
|
*/ |
|
static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if) |
|
{ |
|
uint32_t diff; |
|
if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1]) |
|
diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1]; |
|
else |
|
diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0]; |
|
if(diff < 2) { |
|
return 0; |
|
} else { |
|
return 1; |
|
} |
|
} |
|
|
|
/** |
|
* This function handles ADP Probe Interrupts |
|
*/ |
|
static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if, |
|
uint32_t val) |
|
{ |
|
adpctl_data_t adpctl = {.d32 = 0 }; |
|
gpwrdn_data_t gpwrdn, temp; |
|
adpctl.d32 = val; |
|
|
|
temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); |
|
core_if->adp.probe_counter++; |
|
core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); |
|
if (adpctl.b.rtim == 0 && !temp.b.idsts){ |
|
DWC_PRINTF("RTIM value is 0\n"); |
|
goto exit; |
|
} |
|
if (set_timer_value(core_if, adpctl.b.rtim) && |
|
core_if->adp.initial_probe) { |
|
core_if->adp.initial_probe = 0; |
|
dwc_otg_adp_probe_stop(core_if); |
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.pmuactv = 1; |
|
gpwrdn.b.pmuintsel = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); |
|
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); |
|
|
|
/* check which value is for device mode and which for Host mode */ |
|
if (!temp.b.idsts) { /* considered host mode value is 0 */ |
|
/* |
|
* Turn on VBUS after initial ADP probe. |
|
*/ |
|
core_if->op_state = A_HOST; |
|
dwc_otg_enable_global_interrupts(core_if); |
|
DWC_SPINUNLOCK(core_if->lock); |
|
cil_hcd_start(core_if); |
|
dwc_otg_adp_turnon_vbus(core_if); |
|
DWC_SPINLOCK(core_if->lock); |
|
} else { |
|
/* |
|
* Initiate SRP after initial ADP probe. |
|
*/ |
|
dwc_otg_enable_global_interrupts(core_if); |
|
dwc_otg_initiate_srp(core_if); |
|
} |
|
} else if (core_if->adp.probe_counter > 2){ |
|
gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); |
|
if (compare_timer_values(core_if)) { |
|
DWC_PRINTF("Difference in timer values !!! \n"); |
|
// core_if->adp.attached = DWC_OTG_ADP_ATTACHED; |
|
dwc_otg_adp_probe_stop(core_if); |
|
|
|
/* Power on the core */ |
|
if (core_if->power_down == 2) { |
|
gpwrdn.b.pwrdnswtch = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs-> |
|
gpwrdn, 0, gpwrdn.d32); |
|
} |
|
|
|
/* check which value is for device mode and which for Host mode */ |
|
if (!temp.b.idsts) { /* considered host mode value is 0 */ |
|
/* Disable Interrupt from Power Down Logic */ |
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.pmuintsel = 1; |
|
gpwrdn.b.pmuactv = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs-> |
|
gpwrdn, gpwrdn.d32, 0); |
|
|
|
/* |
|
* Initialize the Core for Host mode. |
|
*/ |
|
core_if->op_state = A_HOST; |
|
dwc_otg_core_init(core_if); |
|
dwc_otg_enable_global_interrupts(core_if); |
|
cil_hcd_start(core_if); |
|
} else { |
|
gotgctl_data_t gotgctl; |
|
/* Mask SRP detected interrupt from Power Down Logic */ |
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.srp_det_msk = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs-> |
|
gpwrdn, gpwrdn.d32, 0); |
|
|
|
/* Disable Power Down Logic */ |
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.pmuintsel = 1; |
|
gpwrdn.b.pmuactv = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs-> |
|
gpwrdn, gpwrdn.d32, 0); |
|
|
|
/* |
|
* Initialize the Core for Device mode. |
|
*/ |
|
core_if->op_state = B_PERIPHERAL; |
|
dwc_otg_core_init(core_if); |
|
dwc_otg_enable_global_interrupts(core_if); |
|
cil_pcd_start(core_if); |
|
|
|
gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); |
|
if (!gotgctl.b.bsesvld) { |
|
dwc_otg_initiate_srp(core_if); |
|
} |
|
} |
|
} |
|
if (core_if->power_down == 2) { |
|
if (gpwrdn.b.bsessvld) { |
|
/* Mask SRP detected interrupt from Power Down Logic */ |
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.srp_det_msk = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); |
|
|
|
/* Disable Power Down Logic */ |
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.pmuactv = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); |
|
|
|
/* |
|
* Initialize the Core for Device mode. |
|
*/ |
|
core_if->op_state = B_PERIPHERAL; |
|
dwc_otg_core_init(core_if); |
|
dwc_otg_enable_global_interrupts(core_if); |
|
cil_pcd_start(core_if); |
|
} |
|
} |
|
} |
|
exit: |
|
/* Clear interrupt */ |
|
adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
|
adpctl.b.adp_prb_int = 1; |
|
dwc_otg_adp_write_reg(core_if, adpctl.d32); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* This function hadles ADP Sense Interrupt |
|
*/ |
|
static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if) |
|
{ |
|
adpctl_data_t adpctl; |
|
/* Stop ADP Sense timer */ |
|
DWC_TIMER_CANCEL(core_if->adp.sense_timer); |
|
|
|
/* Restart ADP Sense timer */ |
|
dwc_otg_adp_sense_timer_start(core_if); |
|
|
|
/* Clear interrupt */ |
|
adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
|
adpctl.b.adp_sns_int = 1; |
|
dwc_otg_adp_write_reg(core_if, adpctl.d32); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* This function handles ADP Probe Interrupts |
|
*/ |
|
static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if, |
|
uint32_t val) |
|
{ |
|
adpctl_data_t adpctl = {.d32 = 0 }; |
|
adpctl.d32 = val; |
|
set_timer_value(core_if, adpctl.b.rtim); |
|
|
|
/* Clear interrupt */ |
|
adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
|
adpctl.b.adp_tmout_int = 1; |
|
dwc_otg_adp_write_reg(core_if, adpctl.d32); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* ADP Interrupt handler. |
|
* |
|
*/ |
|
int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if) |
|
{ |
|
int retval = 0; |
|
adpctl_data_t adpctl = {.d32 = 0}; |
|
|
|
adpctl.d32 = dwc_otg_adp_read_reg(core_if); |
|
DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32); |
|
|
|
if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) { |
|
DWC_PRINTF("ADP Sense interrupt\n"); |
|
retval |= dwc_otg_adp_handle_sns_intr(core_if); |
|
} |
|
if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) { |
|
DWC_PRINTF("ADP timeout interrupt\n"); |
|
retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32); |
|
} |
|
if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) { |
|
DWC_PRINTF("ADP Probe interrupt\n"); |
|
adpctl.b.adp_prb_int = 1; |
|
retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32); |
|
} |
|
|
|
// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0); |
|
//dwc_otg_adp_write_reg(core_if, adpctl.d32); |
|
DWC_PRINTF("RETURN FROM ADP ISR\n"); |
|
|
|
return retval; |
|
} |
|
|
|
/** |
|
* |
|
* @param core_if Programming view of DWC_otg controller. |
|
*/ |
|
int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if) |
|
{ |
|
|
|
#ifndef DWC_HOST_ONLY |
|
hprt0_data_t hprt0; |
|
gpwrdn_data_t gpwrdn; |
|
DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n"); |
|
|
|
gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); |
|
/* check which value is for device mode and which for Host mode */ |
|
if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */ |
|
DWC_PRINTF("SRP: Host mode\n"); |
|
|
|
if (core_if->adp_enable) { |
|
dwc_otg_adp_probe_stop(core_if); |
|
|
|
/* Power on the core */ |
|
if (core_if->power_down == 2) { |
|
gpwrdn.b.pwrdnswtch = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs-> |
|
gpwrdn, 0, gpwrdn.d32); |
|
} |
|
|
|
core_if->op_state = A_HOST; |
|
dwc_otg_core_init(core_if); |
|
dwc_otg_enable_global_interrupts(core_if); |
|
cil_hcd_start(core_if); |
|
} |
|
|
|
/* Turn on the port power bit. */ |
|
hprt0.d32 = dwc_otg_read_hprt0(core_if); |
|
hprt0.b.prtpwr = 1; |
|
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); |
|
|
|
/* Start the Connection timer. So a message can be displayed |
|
* if connect does not occur within 10 seconds. */ |
|
cil_hcd_session_start(core_if); |
|
} else { |
|
DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__); |
|
if (core_if->adp_enable) { |
|
dwc_otg_adp_probe_stop(core_if); |
|
|
|
/* Power on the core */ |
|
if (core_if->power_down == 2) { |
|
gpwrdn.b.pwrdnswtch = 1; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs-> |
|
gpwrdn, 0, gpwrdn.d32); |
|
} |
|
|
|
gpwrdn.d32 = 0; |
|
gpwrdn.b.pmuactv = 0; |
|
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, |
|
gpwrdn.d32); |
|
|
|
core_if->op_state = B_PERIPHERAL; |
|
dwc_otg_core_init(core_if); |
|
dwc_otg_enable_global_interrupts(core_if); |
|
cil_pcd_start(core_if); |
|
} |
|
} |
|
#endif |
|
return 1; |
|
}
|
|
|