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379 lines
9.8 KiB
379 lines
9.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/** |
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* dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms |
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* |
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* This is a small driver for the dwc3 to provide the glue logic |
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* to configure the controller. Tested on STi platforms. |
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* |
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* Copyright (C) 2014 Stmicroelectronics |
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* |
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* Author: Giuseppe Cavallaro <[email protected]> |
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* Contributors: Aymen Bouattay <[email protected]> |
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* Peter Griffin <[email protected]> |
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* |
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* Inspired by dwc3-omap.c and dwc3-exynos.c. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/usb/of.h> |
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#include "core.h" |
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#include "io.h" |
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/* glue registers */ |
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#define CLKRST_CTRL 0x00 |
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#define AUX_CLK_EN BIT(0) |
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#define SW_PIPEW_RESET_N BIT(4) |
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#define EXT_CFG_RESET_N BIT(8) |
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/* |
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* 1'b0 : The host controller complies with the xHCI revision 0.96 |
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* 1'b1 : The host controller complies with the xHCI revision 1.0 |
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*/ |
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#define XHCI_REVISION BIT(12) |
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#define USB2_VBUS_MNGMNT_SEL1 0x2C |
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/* |
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* For all fields in USB2_VBUS_MNGMNT_SEL1 |
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* 2’b00 : Override value from Reg 0x30 is selected |
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* 2’b01 : utmiotg_<signal_name> from usb3_top is selected |
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* 2’b10 : pipew_<signal_name> from PIPEW instance is selected |
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* 2’b11 : value is 1'b0 |
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*/ |
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#define USB2_VBUS_REG30 0x0 |
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#define USB2_VBUS_UTMIOTG 0x1 |
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#define USB2_VBUS_PIPEW 0x2 |
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#define USB2_VBUS_ZERO 0x3 |
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#define SEL_OVERRIDE_VBUSVALID(n) (n << 0) |
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#define SEL_OVERRIDE_POWERPRESENT(n) (n << 4) |
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#define SEL_OVERRIDE_BVALID(n) (n << 8) |
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/* Static DRD configuration */ |
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#define USB3_CONTROL_MASK 0xf77 |
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#define USB3_DEVICE_NOT_HOST BIT(0) |
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#define USB3_FORCE_VBUSVALID BIT(1) |
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#define USB3_DELAY_VBUSVALID BIT(2) |
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#define USB3_SEL_FORCE_OPMODE BIT(4) |
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#define USB3_FORCE_OPMODE(n) (n << 5) |
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#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) |
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#define USB3_FORCE_DPPULLDOWN2 BIT(9) |
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#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) |
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#define USB3_FORCE_DMPULLDOWN2 BIT(11) |
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/** |
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* struct st_dwc3 - dwc3-st driver private structure |
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* @dev: device pointer |
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* @glue_base: ioaddr for the glue registers |
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* @regmap: regmap pointer for getting syscfg |
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* @syscfg_reg_off: usb syscfg control offset |
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* @dr_mode: drd static host/device config |
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* @rstc_pwrdn: rest controller for powerdown signal |
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* @rstc_rst: reset controller for softreset signal |
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*/ |
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struct st_dwc3 { |
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struct device *dev; |
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void __iomem *glue_base; |
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struct regmap *regmap; |
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int syscfg_reg_off; |
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enum usb_dr_mode dr_mode; |
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struct reset_control *rstc_pwrdn; |
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struct reset_control *rstc_rst; |
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}; |
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static inline u32 st_dwc3_readl(void __iomem *base, u32 offset) |
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{ |
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return readl_relaxed(base + offset); |
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} |
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static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value) |
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{ |
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writel_relaxed(value, base + offset); |
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} |
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/** |
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* st_dwc3_drd_init: program the port |
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* @dwc3_data: driver private structure |
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* Description: this function is to program the port as either host or device |
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* according to the static configuration passed from devicetree. |
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* OTG and dual role are not yet supported! |
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*/ |
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static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data) |
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{ |
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u32 val; |
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int err; |
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err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val); |
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if (err) |
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return err; |
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val &= USB3_CONTROL_MASK; |
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switch (dwc3_data->dr_mode) { |
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case USB_DR_MODE_PERIPHERAL: |
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val &= ~(USB3_DELAY_VBUSVALID |
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| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) |
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| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 |
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| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); |
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/* |
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* USB3_PORT2_FORCE_VBUSVALID When '1' and when |
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* USB3_PORT2_DEVICE_NOT_HOST = 1, forces VBUSVLDEXT2 input |
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* of the pico PHY to 1. |
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*/ |
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val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; |
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break; |
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case USB_DR_MODE_HOST: |
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val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID |
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| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) |
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| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 |
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| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); |
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/* |
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* USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus, |
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* when set to ‘0‘, it can delay the arrival of VBUSVALID |
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* information to VBUSVLDEXT2 input of the pico PHY. |
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* We don't want to do that so we set the bit to '1'. |
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*/ |
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val |= USB3_DELAY_VBUSVALID; |
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break; |
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default: |
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dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n", |
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dwc3_data->dr_mode); |
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return -EINVAL; |
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} |
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return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val); |
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} |
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/** |
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* st_dwc3_init: init the controller via glue logic |
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* @dwc3_data: driver private structure |
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*/ |
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static void st_dwc3_init(struct st_dwc3 *dwc3_data) |
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{ |
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u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); |
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reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; |
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reg &= ~SW_PIPEW_RESET_N; |
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st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); |
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/* configure mux for vbus, powerpresent and bvalid signals */ |
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reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1); |
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reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | |
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SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | |
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SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); |
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st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg); |
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reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); |
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reg |= SW_PIPEW_RESET_N; |
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st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); |
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} |
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static int st_dwc3_probe(struct platform_device *pdev) |
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{ |
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struct st_dwc3 *dwc3_data; |
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struct resource *res; |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->of_node, *child; |
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struct platform_device *child_pdev; |
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struct regmap *regmap; |
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int ret; |
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dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL); |
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if (!dwc3_data) |
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return -ENOMEM; |
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dwc3_data->glue_base = |
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devm_platform_ioremap_resource_byname(pdev, "reg-glue"); |
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if (IS_ERR(dwc3_data->glue_base)) |
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return PTR_ERR(dwc3_data->glue_base); |
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regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg"); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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dwc3_data->dev = dev; |
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dwc3_data->regmap = regmap; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg"); |
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if (!res) { |
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ret = -ENXIO; |
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goto undo_platform_dev_alloc; |
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} |
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dwc3_data->syscfg_reg_off = res->start; |
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dev_vdbg(&pdev->dev, "glue-logic addr 0x%pK, syscfg-reg offset 0x%x\n", |
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dwc3_data->glue_base, dwc3_data->syscfg_reg_off); |
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dwc3_data->rstc_pwrdn = |
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devm_reset_control_get_exclusive(dev, "powerdown"); |
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if (IS_ERR(dwc3_data->rstc_pwrdn)) { |
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dev_err(&pdev->dev, "could not get power controller\n"); |
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ret = PTR_ERR(dwc3_data->rstc_pwrdn); |
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goto undo_platform_dev_alloc; |
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} |
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/* Manage PowerDown */ |
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reset_control_deassert(dwc3_data->rstc_pwrdn); |
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dwc3_data->rstc_rst = |
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devm_reset_control_get_shared(dev, "softreset"); |
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if (IS_ERR(dwc3_data->rstc_rst)) { |
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dev_err(&pdev->dev, "could not get reset controller\n"); |
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ret = PTR_ERR(dwc3_data->rstc_rst); |
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goto undo_powerdown; |
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} |
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/* Manage SoftReset */ |
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reset_control_deassert(dwc3_data->rstc_rst); |
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child = of_get_child_by_name(node, "dwc3"); |
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if (!child) { |
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dev_err(&pdev->dev, "failed to find dwc3 core node\n"); |
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ret = -ENODEV; |
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goto err_node_put; |
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} |
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/* Allocate and initialize the core */ |
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ret = of_platform_populate(node, NULL, NULL, dev); |
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if (ret) { |
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dev_err(dev, "failed to add dwc3 core\n"); |
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goto err_node_put; |
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} |
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child_pdev = of_find_device_by_node(child); |
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if (!child_pdev) { |
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dev_err(dev, "failed to find dwc3 core device\n"); |
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ret = -ENODEV; |
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goto err_node_put; |
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} |
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dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev); |
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of_node_put(child); |
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platform_device_put(child_pdev); |
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/* |
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* Configure the USB port as device or host according to the static |
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* configuration passed from DT. |
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* DRD is the only mode currently supported so this will be enhanced |
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* as soon as OTG is available. |
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*/ |
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ret = st_dwc3_drd_init(dwc3_data); |
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if (ret) { |
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dev_err(dev, "drd initialisation failed\n"); |
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goto undo_softreset; |
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} |
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/* ST glue logic init */ |
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st_dwc3_init(dwc3_data); |
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platform_set_drvdata(pdev, dwc3_data); |
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return 0; |
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err_node_put: |
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of_node_put(child); |
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undo_softreset: |
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reset_control_assert(dwc3_data->rstc_rst); |
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undo_powerdown: |
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reset_control_assert(dwc3_data->rstc_pwrdn); |
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undo_platform_dev_alloc: |
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platform_device_put(pdev); |
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return ret; |
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} |
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static int st_dwc3_remove(struct platform_device *pdev) |
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{ |
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struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev); |
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of_platform_depopulate(&pdev->dev); |
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reset_control_assert(dwc3_data->rstc_pwrdn); |
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reset_control_assert(dwc3_data->rstc_rst); |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int st_dwc3_suspend(struct device *dev) |
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{ |
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struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); |
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reset_control_assert(dwc3_data->rstc_pwrdn); |
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reset_control_assert(dwc3_data->rstc_rst); |
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pinctrl_pm_select_sleep_state(dev); |
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return 0; |
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} |
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static int st_dwc3_resume(struct device *dev) |
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{ |
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struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); |
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int ret; |
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pinctrl_pm_select_default_state(dev); |
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reset_control_deassert(dwc3_data->rstc_pwrdn); |
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reset_control_deassert(dwc3_data->rstc_rst); |
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ret = st_dwc3_drd_init(dwc3_data); |
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if (ret) { |
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dev_err(dev, "drd initialisation failed\n"); |
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return ret; |
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} |
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/* ST glue logic init */ |
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st_dwc3_init(dwc3_data); |
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return 0; |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume); |
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static const struct of_device_id st_dwc3_match[] = { |
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{ .compatible = "st,stih407-dwc3" }, |
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{ /* sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, st_dwc3_match); |
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static struct platform_driver st_dwc3_driver = { |
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.probe = st_dwc3_probe, |
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.remove = st_dwc3_remove, |
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.driver = { |
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.name = "usb-st-dwc3", |
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.of_match_table = st_dwc3_match, |
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.pm = &st_dwc3_dev_pm_ops, |
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}, |
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}; |
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module_platform_driver(st_dwc3_driver); |
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MODULE_AUTHOR("Giuseppe Cavallaro <[email protected]>"); |
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MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer"); |
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MODULE_LICENSE("GPL v2");
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