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382 lines
9.4 KiB
382 lines
9.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2016, NVIDIA Corporation |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/reset.h> |
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#include <linux/usb.h> |
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#include <linux/usb/chipidea.h> |
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#include <linux/usb/hcd.h> |
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#include <linux/usb/of.h> |
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#include <linux/usb/phy.h> |
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#include "../host/ehci.h" |
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#include "ci.h" |
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struct tegra_usb { |
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struct ci_hdrc_platform_data data; |
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struct platform_device *dev; |
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const struct tegra_usb_soc_info *soc; |
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struct usb_phy *phy; |
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struct clk *clk; |
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bool needs_double_reset; |
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}; |
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struct tegra_usb_soc_info { |
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unsigned long flags; |
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unsigned int txfifothresh; |
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enum usb_dr_mode dr_mode; |
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}; |
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static const struct tegra_usb_soc_info tegra20_ehci_soc_info = { |
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.flags = CI_HDRC_REQUIRES_ALIGNED_DMA | |
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CI_HDRC_OVERRIDE_PHY_CONTROL | |
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CI_HDRC_SUPPORTS_RUNTIME_PM, |
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.dr_mode = USB_DR_MODE_HOST, |
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.txfifothresh = 10, |
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}; |
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static const struct tegra_usb_soc_info tegra30_ehci_soc_info = { |
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.flags = CI_HDRC_REQUIRES_ALIGNED_DMA | |
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CI_HDRC_OVERRIDE_PHY_CONTROL | |
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CI_HDRC_SUPPORTS_RUNTIME_PM, |
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.dr_mode = USB_DR_MODE_HOST, |
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.txfifothresh = 16, |
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}; |
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static const struct tegra_usb_soc_info tegra20_udc_soc_info = { |
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.flags = CI_HDRC_REQUIRES_ALIGNED_DMA | |
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CI_HDRC_OVERRIDE_PHY_CONTROL | |
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CI_HDRC_SUPPORTS_RUNTIME_PM, |
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.dr_mode = USB_DR_MODE_UNKNOWN, |
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.txfifothresh = 10, |
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}; |
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static const struct tegra_usb_soc_info tegra30_udc_soc_info = { |
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.flags = CI_HDRC_REQUIRES_ALIGNED_DMA | |
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CI_HDRC_OVERRIDE_PHY_CONTROL | |
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CI_HDRC_SUPPORTS_RUNTIME_PM, |
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.dr_mode = USB_DR_MODE_UNKNOWN, |
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.txfifothresh = 16, |
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}; |
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static const struct of_device_id tegra_usb_of_match[] = { |
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{ |
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.compatible = "nvidia,tegra20-ehci", |
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.data = &tegra20_ehci_soc_info, |
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}, { |
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.compatible = "nvidia,tegra30-ehci", |
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.data = &tegra30_ehci_soc_info, |
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}, { |
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.compatible = "nvidia,tegra20-udc", |
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.data = &tegra20_udc_soc_info, |
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}, { |
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.compatible = "nvidia,tegra30-udc", |
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.data = &tegra30_udc_soc_info, |
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}, { |
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.compatible = "nvidia,tegra114-udc", |
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.data = &tegra30_udc_soc_info, |
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}, { |
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.compatible = "nvidia,tegra124-udc", |
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.data = &tegra30_udc_soc_info, |
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}, { |
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/* sentinel */ |
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} |
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}; |
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MODULE_DEVICE_TABLE(of, tegra_usb_of_match); |
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static int tegra_usb_reset_controller(struct device *dev) |
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{ |
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struct reset_control *rst, *rst_utmi; |
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struct device_node *phy_np; |
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int err; |
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rst = devm_reset_control_get_shared(dev, "usb"); |
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if (IS_ERR(rst)) { |
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dev_err(dev, "can't get ehci reset: %pe\n", rst); |
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return PTR_ERR(rst); |
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} |
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phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0); |
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if (!phy_np) |
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return -ENOENT; |
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/* |
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* The 1st USB controller contains some UTMI pad registers that are |
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* global for all the controllers on the chip. Those registers are |
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* also cleared when reset is asserted to the 1st controller. |
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*/ |
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rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads"); |
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if (IS_ERR(rst_utmi)) { |
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dev_warn(dev, "can't get utmi-pads reset from the PHY\n"); |
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dev_warn(dev, "continuing, but please update your DT\n"); |
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} else { |
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/* |
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* PHY driver performs UTMI-pads reset in a case of a |
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* non-legacy DT. |
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*/ |
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reset_control_put(rst_utmi); |
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} |
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of_node_put(phy_np); |
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/* reset control is shared, hence initialize it first */ |
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err = reset_control_deassert(rst); |
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if (err) |
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return err; |
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err = reset_control_assert(rst); |
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if (err) |
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return err; |
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udelay(1); |
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err = reset_control_deassert(rst); |
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if (err) |
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return err; |
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return 0; |
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} |
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static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event) |
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{ |
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struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent); |
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struct ehci_hcd *ehci; |
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switch (event) { |
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case CI_HDRC_CONTROLLER_RESET_EVENT: |
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if (ci->hcd) { |
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ehci = hcd_to_ehci(ci->hcd); |
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ehci->has_tdi_phy_lpm = false; |
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ehci_writel(ehci, usb->soc->txfifothresh << 16, |
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&ehci->regs->txfill_tuning); |
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} |
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break; |
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} |
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return 0; |
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} |
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static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci, |
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u32 __iomem *portsc_reg, |
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unsigned long *flags) |
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{ |
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u32 saved_usbintr, temp; |
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unsigned int i, tries; |
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int retval = 0; |
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saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); |
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/* disable USB interrupt */ |
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ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
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spin_unlock_irqrestore(&ehci->lock, *flags); |
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/* |
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* Here we have to do Port Reset at most twice for |
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* Port Enable bit to be set. |
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*/ |
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for (i = 0; i < 2; i++) { |
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temp = ehci_readl(ehci, portsc_reg); |
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temp |= PORT_RESET; |
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ehci_writel(ehci, temp, portsc_reg); |
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fsleep(10000); |
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temp &= ~PORT_RESET; |
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ehci_writel(ehci, temp, portsc_reg); |
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fsleep(1000); |
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tries = 100; |
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do { |
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fsleep(1000); |
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/* |
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* Up to this point, Port Enable bit is |
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* expected to be set after 2 ms waiting. |
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* USB1 usually takes extra 45 ms, for safety, |
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* we take 100 ms as timeout. |
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*/ |
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temp = ehci_readl(ehci, portsc_reg); |
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} while (!(temp & PORT_PE) && tries--); |
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if (temp & PORT_PE) |
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break; |
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} |
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if (i == 2) |
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retval = -ETIMEDOUT; |
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/* |
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* Clear Connect Status Change bit if it's set. |
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* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. |
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*/ |
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if (temp & PORT_CSC) |
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ehci_writel(ehci, PORT_CSC, portsc_reg); |
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/* |
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* Write to clear any interrupt status bits that might be set |
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* during port reset. |
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*/ |
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temp = ehci_readl(ehci, &ehci->regs->status); |
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ehci_writel(ehci, temp, &ehci->regs->status); |
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/* restore original interrupt-enable bits */ |
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spin_lock_irqsave(&ehci->lock, *flags); |
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ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); |
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return retval; |
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} |
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static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue, |
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u16 wIndex, char *buf, u16 wLength, |
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bool *done, unsigned long *flags) |
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{ |
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struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent); |
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struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd); |
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u32 __iomem *status_reg; |
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int retval = 0; |
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status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; |
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switch (typeReq) { |
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case SetPortFeature: |
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if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset) |
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break; |
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/* for USB1 port we need to issue Port Reset twice internally */ |
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retval = tegra_usb_internal_port_reset(ehci, status_reg, flags); |
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*done = true; |
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break; |
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} |
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return retval; |
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} |
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static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable) |
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{ |
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/* |
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* Touching any register which belongs to AHB clock domain will |
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* hang CPU if USB controller is put into low power mode because |
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* AHB USB clock is gated on Tegra in the LPM. |
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* |
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* Tegra PHY has a separate register for checking the clock status |
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* and usb_phy_set_suspend() takes care of gating/ungating the clocks |
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* and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers |
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* shouldn't be touched directly by the CI driver. |
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*/ |
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usb_phy_set_suspend(ci->usb_phy, enable); |
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} |
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static int tegra_usb_probe(struct platform_device *pdev) |
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{ |
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const struct tegra_usb_soc_info *soc; |
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struct tegra_usb *usb; |
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int err; |
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usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL); |
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if (!usb) |
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return -ENOMEM; |
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soc = of_device_get_match_data(&pdev->dev); |
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if (!soc) { |
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dev_err(&pdev->dev, "failed to match OF data\n"); |
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return -EINVAL; |
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} |
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usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); |
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if (IS_ERR(usb->phy)) { |
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err = PTR_ERR(usb->phy); |
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dev_err(&pdev->dev, "failed to get PHY: %d\n", err); |
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return err; |
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} |
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usb->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(usb->clk)) { |
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err = PTR_ERR(usb->clk); |
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dev_err(&pdev->dev, "failed to get clock: %d\n", err); |
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return err; |
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} |
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err = clk_prepare_enable(usb->clk); |
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if (err < 0) { |
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dev_err(&pdev->dev, "failed to enable clock: %d\n", err); |
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return err; |
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} |
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if (device_property_present(&pdev->dev, "nvidia,needs-double-reset")) |
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usb->needs_double_reset = true; |
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err = tegra_usb_reset_controller(&pdev->dev); |
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if (err) { |
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dev_err(&pdev->dev, "failed to reset controller: %d\n", err); |
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goto fail_power_off; |
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} |
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/* |
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* USB controller registers shouldn't be touched before PHY is |
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* initialized, otherwise CPU will hang because clocks are gated. |
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* PHY driver controls gating of internal USB clocks on Tegra. |
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*/ |
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err = usb_phy_init(usb->phy); |
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if (err) |
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goto fail_power_off; |
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platform_set_drvdata(pdev, usb); |
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/* setup and register ChipIdea HDRC device */ |
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usb->soc = soc; |
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usb->data.name = "tegra-usb"; |
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usb->data.flags = soc->flags; |
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usb->data.usb_phy = usb->phy; |
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usb->data.dr_mode = soc->dr_mode; |
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usb->data.capoffset = DEF_CAPOFFSET; |
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usb->data.enter_lpm = tegra_usb_enter_lpm; |
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usb->data.hub_control = tegra_ehci_hub_control; |
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usb->data.notify_event = tegra_usb_notify_event; |
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/* Tegra PHY driver currently doesn't support LPM for ULPI */ |
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if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI) |
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usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM; |
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usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource, |
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pdev->num_resources, &usb->data); |
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if (IS_ERR(usb->dev)) { |
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err = PTR_ERR(usb->dev); |
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dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err); |
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goto phy_shutdown; |
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} |
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return 0; |
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phy_shutdown: |
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usb_phy_shutdown(usb->phy); |
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fail_power_off: |
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clk_disable_unprepare(usb->clk); |
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return err; |
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} |
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static int tegra_usb_remove(struct platform_device *pdev) |
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{ |
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struct tegra_usb *usb = platform_get_drvdata(pdev); |
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ci_hdrc_remove_device(usb->dev); |
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usb_phy_shutdown(usb->phy); |
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clk_disable_unprepare(usb->clk); |
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return 0; |
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} |
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static struct platform_driver tegra_usb_driver = { |
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.driver = { |
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.name = "tegra-usb", |
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.of_match_table = tegra_usb_of_match, |
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}, |
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.probe = tegra_usb_probe, |
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.remove = tegra_usb_remove, |
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}; |
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module_platform_driver(tegra_usb_driver); |
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MODULE_DESCRIPTION("NVIDIA Tegra USB driver"); |
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MODULE_AUTHOR("Thierry Reding <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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