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776 lines
23 KiB
776 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2019 Xilinx, Inc. |
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* |
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* Author: Naga Sureshkumar Relli <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/spi/spi.h> |
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#include <linux/workqueue.h> |
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#include <linux/spi/spi-mem.h> |
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/* Register offset definitions */ |
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#define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */ |
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#define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */ |
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#define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */ |
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#define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */ |
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#define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */ |
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#define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */ |
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#define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */ |
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#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */ |
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#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */ |
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#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */ |
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#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */ |
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#define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */ |
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#define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */ |
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#define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */ |
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#define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */ |
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#define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */ |
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#define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */ |
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#define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */ |
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/* |
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* QSPI Configuration Register bit Masks |
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* |
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* This register contains various control bits that effect the operation |
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* of the QSPI controller |
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*/ |
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#define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */ |
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#define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */ |
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#define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */ |
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#define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */ |
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#define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */ |
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#define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */ |
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#define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */ |
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#define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */ |
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#define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */ |
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/* |
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* QSPI Configuration Register - Baud rate and slave select |
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* |
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* These are the values used in the calculation of baud rate divisor and |
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* setting the slave select. |
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*/ |
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#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */ |
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#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */ |
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#define ZYNQ_QSPI_CONFIG_PCS BIT(10) /* Peripheral Chip Select */ |
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/* |
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* QSPI Interrupt Registers bit Masks |
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* |
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* All the four interrupt registers (Status/Mask/Enable/Disable) have the same |
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* bit definitions. |
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*/ |
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#define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */ |
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#define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */ |
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#define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */ |
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#define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */ |
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#define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */ |
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#define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */ |
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#define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \ |
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ZYNQ_QSPI_IXR_TXNFULL_MASK | \ |
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ZYNQ_QSPI_IXR_TXFULL_MASK | \ |
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ZYNQ_QSPI_IXR_RXNEMTY_MASK | \ |
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ZYNQ_QSPI_IXR_RXF_FULL_MASK | \ |
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ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK) |
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#define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \ |
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ZYNQ_QSPI_IXR_RXNEMTY_MASK) |
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/* |
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* QSPI Enable Register bit Masks |
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* |
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* This register is used to enable or disable the QSPI controller |
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*/ |
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#define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */ |
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/* |
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* QSPI Linear Configuration Register |
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* |
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* It is named Linear Configuration but it controls other modes when not in |
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* linear mode also. |
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*/ |
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#define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */ |
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#define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */ |
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#define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */ |
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#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 |
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#define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */ |
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#define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */ |
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#define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */ |
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#define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */ |
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/* |
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* The modebits configurable by the driver to make the SPI support different |
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* data formats |
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*/ |
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#define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA) |
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/* Maximum number of chip selects */ |
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#define ZYNQ_QSPI_MAX_NUM_CS 2 |
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/** |
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* struct zynq_qspi - Defines qspi driver instance |
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* @dev: Pointer to the this device's information |
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* @regs: Virtual address of the QSPI controller registers |
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* @refclk: Pointer to the peripheral clock |
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* @pclk: Pointer to the APB clock |
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* @irq: IRQ number |
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* @txbuf: Pointer to the TX buffer |
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* @rxbuf: Pointer to the RX buffer |
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* @tx_bytes: Number of bytes left to transfer |
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* @rx_bytes: Number of bytes left to receive |
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* @data_completion: completion structure |
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*/ |
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struct zynq_qspi { |
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struct device *dev; |
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void __iomem *regs; |
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struct clk *refclk; |
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struct clk *pclk; |
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int irq; |
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u8 *txbuf; |
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u8 *rxbuf; |
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int tx_bytes; |
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int rx_bytes; |
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struct completion data_completion; |
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}; |
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/* |
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* Inline functions for the QSPI controller read/write |
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*/ |
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static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset) |
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{ |
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return readl_relaxed(xqspi->regs + offset); |
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} |
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static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset, |
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u32 val) |
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{ |
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writel_relaxed(val, xqspi->regs + offset); |
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} |
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/** |
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* zynq_qspi_init_hw - Initialize the hardware |
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* @xqspi: Pointer to the zynq_qspi structure |
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* @num_cs: Number of connected CS (to enable dual memories if needed) |
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* |
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* The default settings of the QSPI controller's configurable parameters on |
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* reset are |
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* - Master mode |
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* - Baud rate divisor is set to 2 |
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* - Tx threshold set to 1l Rx threshold set to 32 |
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* - Flash memory interface mode enabled |
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* - Size of the word to be transferred as 8 bit |
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* This function performs the following actions |
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* - Disable and clear all the interrupts |
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* - Enable manual slave select |
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* - Enable manual start |
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* - Deselect all the chip select lines |
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* - Set the size of the word to be transferred as 32 bit |
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* - Set the little endian mode of TX FIFO and |
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* - Enable the QSPI controller |
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*/ |
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static void zynq_qspi_init_hw(struct zynq_qspi *xqspi, unsigned int num_cs) |
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{ |
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u32 config_reg; |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK); |
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/* Disable linear mode as the boot loader may have used it */ |
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config_reg = 0; |
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/* At the same time, enable dual mode if more than 1 CS is available */ |
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if (num_cs > 1) |
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config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM; |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg); |
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/* Clear the RX FIFO */ |
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while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) & |
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ZYNQ_QSPI_IXR_RXNEMTY_MASK) |
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zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK); |
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config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); |
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config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK | |
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ZYNQ_QSPI_CONFIG_CPOL_MASK | |
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ZYNQ_QSPI_CONFIG_CPHA_MASK | |
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ZYNQ_QSPI_CONFIG_BDRATE_MASK | |
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ZYNQ_QSPI_CONFIG_SSFORCE_MASK | |
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ZYNQ_QSPI_CONFIG_MANSRTEN_MASK | |
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ZYNQ_QSPI_CONFIG_MANSRT_MASK); |
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config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK | |
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ZYNQ_QSPI_CONFIG_SSFORCE_MASK | |
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ZYNQ_QSPI_CONFIG_FWIDTH_MASK | |
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ZYNQ_QSPI_CONFIG_IFMODE_MASK); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET, |
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ZYNQ_QSPI_RX_THRESHOLD); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET, |
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ZYNQ_QSPI_TX_THRESHOLD); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, |
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ZYNQ_QSPI_ENABLE_ENABLE_MASK); |
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} |
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static bool zynq_qspi_supports_op(struct spi_mem *mem, |
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const struct spi_mem_op *op) |
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{ |
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if (!spi_mem_default_supports_op(mem, op)) |
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return false; |
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/* |
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* The number of address bytes should be equal to or less than 3 bytes. |
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*/ |
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if (op->addr.nbytes > 3) |
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return false; |
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return true; |
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} |
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/** |
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* zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer |
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* @xqspi: Pointer to the zynq_qspi structure |
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* @size: Number of bytes to be read (1..4) |
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*/ |
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static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size) |
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{ |
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u32 data; |
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data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET); |
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if (xqspi->rxbuf) { |
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memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size); |
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xqspi->rxbuf += size; |
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} |
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xqspi->rx_bytes -= size; |
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if (xqspi->rx_bytes < 0) |
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xqspi->rx_bytes = 0; |
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} |
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/** |
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* zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO |
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* @xqspi: Pointer to the zynq_qspi structure |
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* @size: Number of bytes to be written (1..4) |
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*/ |
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static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size) |
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{ |
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static const unsigned int offset[4] = { |
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ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET, |
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ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET }; |
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u32 data; |
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if (xqspi->txbuf) { |
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data = 0xffffffff; |
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memcpy(&data, xqspi->txbuf, size); |
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xqspi->txbuf += size; |
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} else { |
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data = 0; |
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} |
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xqspi->tx_bytes -= size; |
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zynq_qspi_write(xqspi, offset[size - 1], data); |
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} |
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/** |
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* zynq_qspi_chipselect - Select or deselect the chip select line |
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* @spi: Pointer to the spi_device structure |
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* @assert: 1 for select or 0 for deselect the chip select line |
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*/ |
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static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) |
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{ |
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struct spi_controller *ctlr = spi->master; |
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struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr); |
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u32 config_reg; |
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/* Select the lower (CS0) or upper (CS1) memory */ |
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if (ctlr->num_chipselect > 1) { |
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config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET); |
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if (!spi->chip_select) |
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config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE; |
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else |
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config_reg |= ZYNQ_QSPI_LCFG_U_PAGE; |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg); |
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} |
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/* Ground the line to assert the CS */ |
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config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); |
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if (assert) |
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config_reg &= ~ZYNQ_QSPI_CONFIG_PCS; |
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else |
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config_reg |= ZYNQ_QSPI_CONFIG_PCS; |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); |
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} |
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/** |
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* zynq_qspi_config_op - Configure QSPI controller for specified transfer |
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* @xqspi: Pointer to the zynq_qspi structure |
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* @spi: Pointer to the spi_device structure |
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* |
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* Sets the operational mode of QSPI controller for the next QSPI transfer and |
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* sets the requested clock frequency. |
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* |
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* Return: 0 on success and -EINVAL on invalid input parameter |
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* |
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* Note: If the requested frequency is not an exact match with what can be |
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* obtained using the prescalar value, the driver sets the clock frequency which |
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* is lower than the requested frequency (maximum lower) for the transfer. If |
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* the requested frequency is higher or lower than that is supported by the QSPI |
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* controller the driver will set the highest or lowest frequency supported by |
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* controller. |
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*/ |
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static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) |
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{ |
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u32 config_reg, baud_rate_val = 0; |
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/* |
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* Set the clock frequency |
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* The baud rate divisor is not a direct mapping to the value written |
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* into the configuration register (config_reg[5:3]) |
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* i.e. 000 - divide by 2 |
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* 001 - divide by 4 |
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* ---------------- |
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* 111 - divide by 256 |
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*/ |
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while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) && |
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(clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > |
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spi->max_speed_hz) |
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baud_rate_val++; |
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config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); |
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/* Set the QSPI clock phase and clock polarity */ |
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config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) & |
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(~ZYNQ_QSPI_CONFIG_CPOL_MASK); |
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if (spi->mode & SPI_CPHA) |
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config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK; |
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if (spi->mode & SPI_CPOL) |
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config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; |
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config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK; |
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config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT); |
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zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); |
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return 0; |
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} |
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/** |
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* zynq_qspi_setup - Configure the QSPI controller |
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* @spi: Pointer to the spi_device structure |
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* |
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* Sets the operational mode of QSPI controller for the next QSPI transfer, baud |
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* rate and divisor value to setup the requested qspi clock. |
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* |
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* Return: 0 on success and error value on failure |
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*/ |
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static int zynq_qspi_setup_op(struct spi_device *spi) |
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{ |
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struct spi_controller *ctlr = spi->master; |
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struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr); |
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if (ctlr->busy) |
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return -EBUSY; |
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clk_enable(qspi->refclk); |
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clk_enable(qspi->pclk); |
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zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET, |
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ZYNQ_QSPI_ENABLE_ENABLE_MASK); |
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return 0; |
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} |
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/** |
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* zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible |
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* @xqspi: Pointer to the zynq_qspi structure |
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* @txcount: Maximum number of words to write |
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* @txempty: Indicates that TxFIFO is empty |
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*/ |
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static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount, |
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bool txempty) |
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{ |
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int count, len, k; |
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len = xqspi->tx_bytes; |
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if (len && len < 4) { |
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/* |
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* We must empty the TxFIFO between accesses to TXD0, |
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* TXD1, TXD2, TXD3. |
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*/ |
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if (txempty) |
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zynq_qspi_txfifo_op(xqspi, len); |
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return; |
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} |
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count = len / 4; |
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if (count > txcount) |
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count = txcount; |
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if (xqspi->txbuf) { |
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iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET, |
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xqspi->txbuf, count); |
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xqspi->txbuf += count * 4; |
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} else { |
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for (k = 0; k < count; k++) |
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writel_relaxed(0, xqspi->regs + |
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ZYNQ_QSPI_TXD_00_00_OFFSET); |
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} |
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xqspi->tx_bytes -= count * 4; |
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} |
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/** |
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* zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible |
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* @xqspi: Pointer to the zynq_qspi structure |
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* @rxcount: Maximum number of words to read |
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*/ |
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static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount) |
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{ |
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int count, len, k; |
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len = xqspi->rx_bytes - xqspi->tx_bytes; |
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count = len / 4; |
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if (count > rxcount) |
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count = rxcount; |
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if (xqspi->rxbuf) { |
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ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET, |
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xqspi->rxbuf, count); |
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xqspi->rxbuf += count * 4; |
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} else { |
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for (k = 0; k < count; k++) |
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readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET); |
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} |
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xqspi->rx_bytes -= count * 4; |
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len -= count * 4; |
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if (len && len < 4 && count < rxcount) |
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zynq_qspi_rxfifo_op(xqspi, len); |
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} |
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/** |
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* zynq_qspi_irq - Interrupt service routine of the QSPI controller |
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* @irq: IRQ number |
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* @dev_id: Pointer to the xqspi structure |
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* |
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* This function handles TX empty only. |
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* On TX empty interrupt this function reads the received data from RX FIFO and |
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* fills the TX FIFO if there is any data remaining to be transferred. |
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* |
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* Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise. |
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*/ |
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static irqreturn_t zynq_qspi_irq(int irq, void *dev_id) |
|
{ |
|
u32 intr_status; |
|
bool txempty; |
|
struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id; |
|
|
|
intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET); |
|
zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status); |
|
|
|
if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) || |
|
(intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) { |
|
/* |
|
* This bit is set when Tx FIFO has < THRESHOLD entries. |
|
* We have the THRESHOLD value set to 1, |
|
* so this bit indicates Tx FIFO is empty. |
|
*/ |
|
txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK); |
|
/* Read out the data from the RX FIFO */ |
|
zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD); |
|
if (xqspi->tx_bytes) { |
|
/* There is more data to send */ |
|
zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD, |
|
txempty); |
|
} else { |
|
/* |
|
* If transfer and receive is completed then only send |
|
* complete signal. |
|
*/ |
|
if (!xqspi->rx_bytes) { |
|
zynq_qspi_write(xqspi, |
|
ZYNQ_QSPI_IDIS_OFFSET, |
|
ZYNQ_QSPI_IXR_RXTX_MASK); |
|
complete(&xqspi->data_completion); |
|
} |
|
} |
|
return IRQ_HANDLED; |
|
} |
|
|
|
return IRQ_NONE; |
|
} |
|
|
|
/** |
|
* zynq_qspi_exec_mem_op() - Initiates the QSPI transfer |
|
* @mem: the SPI memory |
|
* @op: the memory operation to execute |
|
* |
|
* Executes a memory operation. |
|
* |
|
* This function first selects the chip and starts the memory operation. |
|
* |
|
* Return: 0 in case of success, a negative error code otherwise. |
|
*/ |
|
static int zynq_qspi_exec_mem_op(struct spi_mem *mem, |
|
const struct spi_mem_op *op) |
|
{ |
|
struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master); |
|
int err = 0, i; |
|
u8 *tmpbuf; |
|
u8 opcode = op->cmd.opcode; |
|
|
|
dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", |
|
opcode, op->cmd.buswidth, op->addr.buswidth, |
|
op->dummy.buswidth, op->data.buswidth); |
|
|
|
zynq_qspi_chipselect(mem->spi, true); |
|
zynq_qspi_config_op(xqspi, mem->spi); |
|
|
|
if (op->cmd.nbytes) { |
|
reinit_completion(&xqspi->data_completion); |
|
xqspi->txbuf = &opcode; |
|
xqspi->rxbuf = NULL; |
|
xqspi->tx_bytes = op->cmd.nbytes; |
|
xqspi->rx_bytes = op->cmd.nbytes; |
|
zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); |
|
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, |
|
ZYNQ_QSPI_IXR_RXTX_MASK); |
|
if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, |
|
msecs_to_jiffies(1000))) |
|
err = -ETIMEDOUT; |
|
} |
|
|
|
if (op->addr.nbytes) { |
|
for (i = 0; i < op->addr.nbytes; i++) { |
|
xqspi->txbuf[i] = op->addr.val >> |
|
(8 * (op->addr.nbytes - i - 1)); |
|
} |
|
|
|
reinit_completion(&xqspi->data_completion); |
|
xqspi->rxbuf = NULL; |
|
xqspi->tx_bytes = op->addr.nbytes; |
|
xqspi->rx_bytes = op->addr.nbytes; |
|
zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); |
|
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, |
|
ZYNQ_QSPI_IXR_RXTX_MASK); |
|
if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, |
|
msecs_to_jiffies(1000))) |
|
err = -ETIMEDOUT; |
|
} |
|
|
|
if (op->dummy.nbytes) { |
|
tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL); |
|
memset(tmpbuf, 0xff, op->dummy.nbytes); |
|
reinit_completion(&xqspi->data_completion); |
|
xqspi->txbuf = tmpbuf; |
|
xqspi->rxbuf = NULL; |
|
xqspi->tx_bytes = op->dummy.nbytes; |
|
xqspi->rx_bytes = op->dummy.nbytes; |
|
zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); |
|
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, |
|
ZYNQ_QSPI_IXR_RXTX_MASK); |
|
if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, |
|
msecs_to_jiffies(1000))) |
|
err = -ETIMEDOUT; |
|
|
|
kfree(tmpbuf); |
|
} |
|
|
|
if (op->data.nbytes) { |
|
reinit_completion(&xqspi->data_completion); |
|
if (op->data.dir == SPI_MEM_DATA_OUT) { |
|
xqspi->txbuf = (u8 *)op->data.buf.out; |
|
xqspi->tx_bytes = op->data.nbytes; |
|
xqspi->rxbuf = NULL; |
|
xqspi->rx_bytes = op->data.nbytes; |
|
} else { |
|
xqspi->txbuf = NULL; |
|
xqspi->rxbuf = (u8 *)op->data.buf.in; |
|
xqspi->rx_bytes = op->data.nbytes; |
|
xqspi->tx_bytes = op->data.nbytes; |
|
} |
|
|
|
zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); |
|
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, |
|
ZYNQ_QSPI_IXR_RXTX_MASK); |
|
if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, |
|
msecs_to_jiffies(1000))) |
|
err = -ETIMEDOUT; |
|
} |
|
zynq_qspi_chipselect(mem->spi, false); |
|
|
|
return err; |
|
} |
|
|
|
static const struct spi_controller_mem_ops zynq_qspi_mem_ops = { |
|
.supports_op = zynq_qspi_supports_op, |
|
.exec_op = zynq_qspi_exec_mem_op, |
|
}; |
|
|
|
/** |
|
* zynq_qspi_probe - Probe method for the QSPI driver |
|
* @pdev: Pointer to the platform_device structure |
|
* |
|
* This function initializes the driver data structures and the hardware. |
|
* |
|
* Return: 0 on success and error value on failure |
|
*/ |
|
static int zynq_qspi_probe(struct platform_device *pdev) |
|
{ |
|
int ret = 0; |
|
struct spi_controller *ctlr; |
|
struct device *dev = &pdev->dev; |
|
struct device_node *np = dev->of_node; |
|
struct zynq_qspi *xqspi; |
|
u32 num_cs; |
|
|
|
ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); |
|
if (!ctlr) |
|
return -ENOMEM; |
|
|
|
xqspi = spi_controller_get_devdata(ctlr); |
|
xqspi->dev = dev; |
|
platform_set_drvdata(pdev, xqspi); |
|
xqspi->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(xqspi->regs)) { |
|
ret = PTR_ERR(xqspi->regs); |
|
goto remove_master; |
|
} |
|
|
|
xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); |
|
if (IS_ERR(xqspi->pclk)) { |
|
dev_err(&pdev->dev, "pclk clock not found.\n"); |
|
ret = PTR_ERR(xqspi->pclk); |
|
goto remove_master; |
|
} |
|
|
|
init_completion(&xqspi->data_completion); |
|
|
|
xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); |
|
if (IS_ERR(xqspi->refclk)) { |
|
dev_err(&pdev->dev, "ref_clk clock not found.\n"); |
|
ret = PTR_ERR(xqspi->refclk); |
|
goto remove_master; |
|
} |
|
|
|
ret = clk_prepare_enable(xqspi->pclk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Unable to enable APB clock.\n"); |
|
goto remove_master; |
|
} |
|
|
|
ret = clk_prepare_enable(xqspi->refclk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
|
goto clk_dis_pclk; |
|
} |
|
|
|
xqspi->irq = platform_get_irq(pdev, 0); |
|
if (xqspi->irq <= 0) { |
|
ret = -ENXIO; |
|
goto remove_master; |
|
} |
|
ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, |
|
0, pdev->name, xqspi); |
|
if (ret != 0) { |
|
ret = -ENXIO; |
|
dev_err(&pdev->dev, "request_irq failed\n"); |
|
goto remove_master; |
|
} |
|
|
|
ret = of_property_read_u32(np, "num-cs", |
|
&num_cs); |
|
if (ret < 0) { |
|
ctlr->num_chipselect = 1; |
|
} else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) { |
|
dev_err(&pdev->dev, "only 2 chip selects are available\n"); |
|
goto remove_master; |
|
} else { |
|
ctlr->num_chipselect = num_cs; |
|
} |
|
|
|
ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | |
|
SPI_TX_DUAL | SPI_TX_QUAD; |
|
ctlr->mem_ops = &zynq_qspi_mem_ops; |
|
ctlr->setup = zynq_qspi_setup_op; |
|
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; |
|
ctlr->dev.of_node = np; |
|
|
|
/* QSPI controller initializations */ |
|
zynq_qspi_init_hw(xqspi, ctlr->num_chipselect); |
|
|
|
ret = devm_spi_register_controller(&pdev->dev, ctlr); |
|
if (ret) { |
|
dev_err(&pdev->dev, "spi_register_master failed\n"); |
|
goto clk_dis_all; |
|
} |
|
|
|
return ret; |
|
|
|
clk_dis_all: |
|
clk_disable_unprepare(xqspi->refclk); |
|
clk_dis_pclk: |
|
clk_disable_unprepare(xqspi->pclk); |
|
remove_master: |
|
spi_controller_put(ctlr); |
|
|
|
return ret; |
|
} |
|
|
|
/** |
|
* zynq_qspi_remove - Remove method for the QSPI driver |
|
* @pdev: Pointer to the platform_device structure |
|
* |
|
* This function is called if a device is physically removed from the system or |
|
* if the driver module is being unloaded. It frees all resources allocated to |
|
* the device. |
|
* |
|
* Return: 0 on success and error value on failure |
|
*/ |
|
static int zynq_qspi_remove(struct platform_device *pdev) |
|
{ |
|
struct zynq_qspi *xqspi = platform_get_drvdata(pdev); |
|
|
|
zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0); |
|
|
|
clk_disable_unprepare(xqspi->refclk); |
|
clk_disable_unprepare(xqspi->pclk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id zynq_qspi_of_match[] = { |
|
{ .compatible = "xlnx,zynq-qspi-1.0", }, |
|
{ /* end of table */ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, zynq_qspi_of_match); |
|
|
|
/* |
|
* zynq_qspi_driver - This structure defines the QSPI platform driver |
|
*/ |
|
static struct platform_driver zynq_qspi_driver = { |
|
.probe = zynq_qspi_probe, |
|
.remove = zynq_qspi_remove, |
|
.driver = { |
|
.name = "zynq-qspi", |
|
.of_match_table = zynq_qspi_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(zynq_qspi_driver); |
|
|
|
MODULE_AUTHOR("Xilinx, Inc."); |
|
MODULE_DESCRIPTION("Xilinx Zynq QSPI driver"); |
|
MODULE_LICENSE("GPL");
|
|
|