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721 lines
18 KiB
721 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2012 - 2014 Allwinner Tech |
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* Pan Nan <[email protected]> |
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* |
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* Copyright (C) 2014 Maxime Ripard |
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* Maxime Ripard <[email protected]> |
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*/ |
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|
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> |
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#include <linux/dmaengine.h> |
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#include <linux/spi/spi.h> |
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#define SUN6I_AUTOSUSPEND_TIMEOUT 2000 |
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#define SUN6I_FIFO_DEPTH 128 |
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#define SUN8I_FIFO_DEPTH 64 |
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#define SUN6I_GBL_CTL_REG 0x04 |
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) |
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#define SUN6I_GBL_CTL_MASTER BIT(1) |
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#define SUN6I_GBL_CTL_TP BIT(7) |
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#define SUN6I_GBL_CTL_RST BIT(31) |
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#define SUN6I_TFR_CTL_REG 0x08 |
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#define SUN6I_TFR_CTL_CPHA BIT(0) |
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#define SUN6I_TFR_CTL_CPOL BIT(1) |
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#define SUN6I_TFR_CTL_SPOL BIT(2) |
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#define SUN6I_TFR_CTL_CS_MASK 0x30 |
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#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) |
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#define SUN6I_TFR_CTL_CS_MANUAL BIT(6) |
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#define SUN6I_TFR_CTL_CS_LEVEL BIT(7) |
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#define SUN6I_TFR_CTL_DHB BIT(8) |
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#define SUN6I_TFR_CTL_FBS BIT(12) |
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#define SUN6I_TFR_CTL_XCH BIT(31) |
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#define SUN6I_INT_CTL_REG 0x10 |
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#define SUN6I_INT_CTL_RF_RDY BIT(0) |
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#define SUN6I_INT_CTL_TF_ERQ BIT(4) |
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#define SUN6I_INT_CTL_RF_OVF BIT(8) |
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#define SUN6I_INT_CTL_TC BIT(12) |
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#define SUN6I_INT_STA_REG 0x14 |
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#define SUN6I_FIFO_CTL_REG 0x18 |
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#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff |
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#define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8) |
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#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 |
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#define SUN6I_FIFO_CTL_RF_RST BIT(15) |
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#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff |
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#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 |
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#define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24) |
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#define SUN6I_FIFO_CTL_TF_RST BIT(31) |
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#define SUN6I_FIFO_STA_REG 0x1c |
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#define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) |
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#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) |
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#define SUN6I_CLK_CTL_REG 0x24 |
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#define SUN6I_CLK_CTL_CDR2_MASK 0xff |
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#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) |
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#define SUN6I_CLK_CTL_CDR1_MASK 0xf |
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#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) |
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#define SUN6I_CLK_CTL_DRS BIT(12) |
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#define SUN6I_MAX_XFER_SIZE 0xffffff |
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#define SUN6I_BURST_CNT_REG 0x30 |
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#define SUN6I_XMIT_CNT_REG 0x34 |
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#define SUN6I_BURST_CTL_CNT_REG 0x38 |
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#define SUN6I_TXDATA_REG 0x200 |
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#define SUN6I_RXDATA_REG 0x300 |
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struct sun6i_spi { |
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struct spi_master *master; |
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void __iomem *base_addr; |
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dma_addr_t dma_addr_rx; |
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dma_addr_t dma_addr_tx; |
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struct clk *hclk; |
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struct clk *mclk; |
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struct reset_control *rstc; |
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struct completion done; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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int len; |
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unsigned long fifo_depth; |
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}; |
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static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) |
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{ |
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return readl(sspi->base_addr + reg); |
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} |
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static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) |
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{ |
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writel(value, sspi->base_addr + reg); |
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} |
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static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) |
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{ |
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u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); |
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return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); |
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} |
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static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) |
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{ |
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u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); |
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return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); |
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} |
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static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) |
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{ |
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u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); |
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reg &= ~mask; |
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); |
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} |
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static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi) |
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{ |
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u32 len; |
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u8 byte; |
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/* See how much data is available */ |
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len = sun6i_spi_get_rx_fifo_count(sspi); |
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while (len--) { |
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byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); |
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if (sspi->rx_buf) |
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*sspi->rx_buf++ = byte; |
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} |
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} |
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static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi) |
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{ |
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u32 cnt; |
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int len; |
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u8 byte; |
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/* See how much data we can fit */ |
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cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); |
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len = min((int)cnt, sspi->len); |
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while (len--) { |
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byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; |
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writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); |
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sspi->len--; |
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} |
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} |
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static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); |
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u32 reg; |
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); |
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reg &= ~SUN6I_TFR_CTL_CS_MASK; |
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reg |= SUN6I_TFR_CTL_CS(spi->chip_select); |
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if (enable) |
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reg |= SUN6I_TFR_CTL_CS_LEVEL; |
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else |
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reg &= ~SUN6I_TFR_CTL_CS_LEVEL; |
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); |
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} |
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static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) |
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{ |
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return SUN6I_MAX_XFER_SIZE - 1; |
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} |
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static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi, |
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struct spi_transfer *tfr) |
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{ |
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struct dma_async_tx_descriptor *rxdesc, *txdesc; |
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struct spi_master *master = sspi->master; |
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rxdesc = NULL; |
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if (tfr->rx_buf) { |
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struct dma_slave_config rxconf = { |
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.direction = DMA_DEV_TO_MEM, |
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.src_addr = sspi->dma_addr_rx, |
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
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.src_maxburst = 8, |
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}; |
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dmaengine_slave_config(master->dma_rx, &rxconf); |
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rxdesc = dmaengine_prep_slave_sg(master->dma_rx, |
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tfr->rx_sg.sgl, |
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tfr->rx_sg.nents, |
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DMA_DEV_TO_MEM, |
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DMA_PREP_INTERRUPT); |
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if (!rxdesc) |
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return -EINVAL; |
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} |
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txdesc = NULL; |
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if (tfr->tx_buf) { |
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struct dma_slave_config txconf = { |
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.direction = DMA_MEM_TO_DEV, |
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.dst_addr = sspi->dma_addr_tx, |
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
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.dst_maxburst = 8, |
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}; |
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dmaengine_slave_config(master->dma_tx, &txconf); |
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txdesc = dmaengine_prep_slave_sg(master->dma_tx, |
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tfr->tx_sg.sgl, |
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tfr->tx_sg.nents, |
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DMA_MEM_TO_DEV, |
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DMA_PREP_INTERRUPT); |
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if (!txdesc) { |
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if (rxdesc) |
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dmaengine_terminate_sync(master->dma_rx); |
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return -EINVAL; |
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} |
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} |
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if (tfr->rx_buf) { |
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dmaengine_submit(rxdesc); |
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dma_async_issue_pending(master->dma_rx); |
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} |
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if (tfr->tx_buf) { |
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dmaengine_submit(txdesc); |
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dma_async_issue_pending(master->dma_tx); |
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} |
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return 0; |
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} |
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static int sun6i_spi_transfer_one(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *tfr) |
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{ |
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struct sun6i_spi *sspi = spi_master_get_devdata(master); |
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unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; |
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unsigned int start, end, tx_time; |
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unsigned int trig_level; |
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unsigned int tx_len = 0, rx_len = 0; |
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bool use_dma; |
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int ret = 0; |
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u32 reg; |
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if (tfr->len > SUN6I_MAX_XFER_SIZE) |
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return -EINVAL; |
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reinit_completion(&sspi->done); |
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sspi->tx_buf = tfr->tx_buf; |
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sspi->rx_buf = tfr->rx_buf; |
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sspi->len = tfr->len; |
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use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; |
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/* Clear pending interrupts */ |
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); |
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/* Reset FIFO */ |
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sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, |
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SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); |
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reg = 0; |
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if (!use_dma) { |
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/* |
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* Setup FIFO interrupt trigger level |
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* Here we choose 3/4 of the full fifo depth, as it's |
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* the hardcoded value used in old generation of Allwinner |
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* SPI controller. (See spi-sun4i.c) |
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*/ |
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trig_level = sspi->fifo_depth / 4 * 3; |
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} else { |
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/* |
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* Setup FIFO DMA request trigger level |
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* We choose 1/2 of the full fifo depth, that value will |
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* be used as DMA burst length. |
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*/ |
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trig_level = sspi->fifo_depth / 2; |
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if (tfr->tx_buf) |
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reg |= SUN6I_FIFO_CTL_TF_DRQ_EN; |
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if (tfr->rx_buf) |
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reg |= SUN6I_FIFO_CTL_RF_DRQ_EN; |
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} |
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reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | |
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(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS); |
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sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); |
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/* |
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* Setup the transfer control register: Chip Select, |
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* polarities, etc. |
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*/ |
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); |
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if (spi->mode & SPI_CPOL) |
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reg |= SUN6I_TFR_CTL_CPOL; |
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else |
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reg &= ~SUN6I_TFR_CTL_CPOL; |
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if (spi->mode & SPI_CPHA) |
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reg |= SUN6I_TFR_CTL_CPHA; |
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else |
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reg &= ~SUN6I_TFR_CTL_CPHA; |
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|
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if (spi->mode & SPI_LSB_FIRST) |
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reg |= SUN6I_TFR_CTL_FBS; |
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else |
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reg &= ~SUN6I_TFR_CTL_FBS; |
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|
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/* |
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* If it's a TX only transfer, we don't want to fill the RX |
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* FIFO with bogus data |
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*/ |
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if (sspi->rx_buf) { |
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reg &= ~SUN6I_TFR_CTL_DHB; |
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rx_len = tfr->len; |
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} else { |
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reg |= SUN6I_TFR_CTL_DHB; |
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} |
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|
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/* We want to control the chip select manually */ |
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reg |= SUN6I_TFR_CTL_CS_MANUAL; |
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|
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); |
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|
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/* Ensure that we have a parent clock fast enough */ |
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mclk_rate = clk_get_rate(sspi->mclk); |
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if (mclk_rate < (2 * tfr->speed_hz)) { |
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clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); |
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mclk_rate = clk_get_rate(sspi->mclk); |
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} |
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|
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/* |
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* Setup clock divider. |
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* |
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* We have two choices there. Either we can use the clock |
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* divide rate 1, which is calculated thanks to this formula: |
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* SPI_CLK = MOD_CLK / (2 ^ cdr) |
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* Or we can use CDR2, which is calculated with the formula: |
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* SPI_CLK = MOD_CLK / (2 * (cdr + 1)) |
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* Wether we use the former or the latter is set through the |
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* DRS bit. |
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* |
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* First try CDR2, and if we can't reach the expected |
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* frequency, fall back to CDR1. |
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*/ |
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div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); |
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div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); |
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if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { |
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reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; |
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tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); |
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} else { |
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div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); |
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reg = SUN6I_CLK_CTL_CDR1(div); |
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tfr->effective_speed_hz = mclk_rate / (1 << div); |
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} |
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|
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sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); |
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|
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/* Setup the transfer now... */ |
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if (sspi->tx_buf) |
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tx_len = tfr->len; |
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|
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/* Setup the counters */ |
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sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); |
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sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); |
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sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); |
|
|
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if (!use_dma) { |
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/* Fill the TX FIFO */ |
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sun6i_spi_fill_fifo(sspi); |
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} else { |
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ret = sun6i_spi_prepare_dma(sspi, tfr); |
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if (ret) { |
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dev_warn(&master->dev, |
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"%s: prepare DMA failed, ret=%d", |
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dev_name(&spi->dev), ret); |
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return ret; |
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} |
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} |
|
|
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/* Enable the interrupts */ |
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reg = SUN6I_INT_CTL_TC; |
|
|
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if (!use_dma) { |
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if (rx_len > sspi->fifo_depth) |
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reg |= SUN6I_INT_CTL_RF_RDY; |
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if (tx_len > sspi->fifo_depth) |
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reg |= SUN6I_INT_CTL_TF_ERQ; |
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} |
|
|
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); |
|
|
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/* Start the transfer */ |
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reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); |
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); |
|
|
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tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); |
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start = jiffies; |
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timeout = wait_for_completion_timeout(&sspi->done, |
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msecs_to_jiffies(tx_time)); |
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end = jiffies; |
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if (!timeout) { |
|
dev_warn(&master->dev, |
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"%s: timeout transferring %u bytes@%iHz for %i(%i)ms", |
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dev_name(&spi->dev), tfr->len, tfr->speed_hz, |
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jiffies_to_msecs(end - start), tx_time); |
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ret = -ETIMEDOUT; |
|
} |
|
|
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); |
|
|
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if (ret && use_dma) { |
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dmaengine_terminate_sync(master->dma_rx); |
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dmaengine_terminate_sync(master->dma_tx); |
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} |
|
|
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return ret; |
|
} |
|
|
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static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) |
|
{ |
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struct sun6i_spi *sspi = dev_id; |
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u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); |
|
|
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/* Transfer complete */ |
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if (status & SUN6I_INT_CTL_TC) { |
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); |
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sun6i_spi_drain_fifo(sspi); |
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complete(&sspi->done); |
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return IRQ_HANDLED; |
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} |
|
|
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/* Receive FIFO 3/4 full */ |
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if (status & SUN6I_INT_CTL_RF_RDY) { |
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sun6i_spi_drain_fifo(sspi); |
|
/* Only clear the interrupt _after_ draining the FIFO */ |
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); |
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return IRQ_HANDLED; |
|
} |
|
|
|
/* Transmit FIFO 3/4 empty */ |
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if (status & SUN6I_INT_CTL_TF_ERQ) { |
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sun6i_spi_fill_fifo(sspi); |
|
|
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if (!sspi->len) |
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/* nothing left to transmit */ |
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sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); |
|
|
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/* Only clear the interrupt _after_ re-seeding the FIFO */ |
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sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); |
|
|
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return IRQ_HANDLED; |
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} |
|
|
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return IRQ_NONE; |
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} |
|
|
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static int sun6i_spi_runtime_resume(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct sun6i_spi *sspi = spi_master_get_devdata(master); |
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int ret; |
|
|
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ret = clk_prepare_enable(sspi->hclk); |
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if (ret) { |
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dev_err(dev, "Couldn't enable AHB clock\n"); |
|
goto out; |
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} |
|
|
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ret = clk_prepare_enable(sspi->mclk); |
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if (ret) { |
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dev_err(dev, "Couldn't enable module clock\n"); |
|
goto err; |
|
} |
|
|
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ret = reset_control_deassert(sspi->rstc); |
|
if (ret) { |
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dev_err(dev, "Couldn't deassert the device from reset\n"); |
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goto err2; |
|
} |
|
|
|
sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, |
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SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); |
|
|
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return 0; |
|
|
|
err2: |
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clk_disable_unprepare(sspi->mclk); |
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err: |
|
clk_disable_unprepare(sspi->hclk); |
|
out: |
|
return ret; |
|
} |
|
|
|
static int sun6i_spi_runtime_suspend(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct sun6i_spi *sspi = spi_master_get_devdata(master); |
|
|
|
reset_control_assert(sspi->rstc); |
|
clk_disable_unprepare(sspi->mclk); |
|
clk_disable_unprepare(sspi->hclk); |
|
|
|
return 0; |
|
} |
|
|
|
static bool sun6i_spi_can_dma(struct spi_master *master, |
|
struct spi_device *spi, |
|
struct spi_transfer *xfer) |
|
{ |
|
struct sun6i_spi *sspi = spi_master_get_devdata(master); |
|
|
|
/* |
|
* If the number of spi words to transfer is less or equal than |
|
* the fifo length we can just fill the fifo and wait for a single |
|
* irq, so don't bother setting up dma |
|
*/ |
|
return xfer->len > sspi->fifo_depth; |
|
} |
|
|
|
static int sun6i_spi_probe(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master; |
|
struct sun6i_spi *sspi; |
|
struct resource *mem; |
|
int ret = 0, irq; |
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); |
|
if (!master) { |
|
dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
platform_set_drvdata(pdev, master); |
|
sspi = spi_master_get_devdata(master); |
|
|
|
sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); |
|
if (IS_ERR(sspi->base_addr)) { |
|
ret = PTR_ERR(sspi->base_addr); |
|
goto err_free_master; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
ret = -ENXIO; |
|
goto err_free_master; |
|
} |
|
|
|
ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, |
|
0, "sun6i-spi", sspi); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Cannot request IRQ\n"); |
|
goto err_free_master; |
|
} |
|
|
|
sspi->master = master; |
|
sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); |
|
|
|
master->max_speed_hz = 100 * 1000 * 1000; |
|
master->min_speed_hz = 3 * 1000; |
|
master->use_gpio_descriptors = true; |
|
master->set_cs = sun6i_spi_set_cs; |
|
master->transfer_one = sun6i_spi_transfer_one; |
|
master->num_chipselect = 4; |
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
|
master->bits_per_word_mask = SPI_BPW_MASK(8); |
|
master->dev.of_node = pdev->dev.of_node; |
|
master->auto_runtime_pm = true; |
|
master->max_transfer_size = sun6i_spi_max_transfer_size; |
|
|
|
sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); |
|
if (IS_ERR(sspi->hclk)) { |
|
dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); |
|
ret = PTR_ERR(sspi->hclk); |
|
goto err_free_master; |
|
} |
|
|
|
sspi->mclk = devm_clk_get(&pdev->dev, "mod"); |
|
if (IS_ERR(sspi->mclk)) { |
|
dev_err(&pdev->dev, "Unable to acquire module clock\n"); |
|
ret = PTR_ERR(sspi->mclk); |
|
goto err_free_master; |
|
} |
|
|
|
init_completion(&sspi->done); |
|
|
|
sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
|
if (IS_ERR(sspi->rstc)) { |
|
dev_err(&pdev->dev, "Couldn't get reset controller\n"); |
|
ret = PTR_ERR(sspi->rstc); |
|
goto err_free_master; |
|
} |
|
|
|
master->dma_tx = dma_request_chan(&pdev->dev, "tx"); |
|
if (IS_ERR(master->dma_tx)) { |
|
/* Check tx to see if we need defer probing driver */ |
|
if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { |
|
ret = -EPROBE_DEFER; |
|
goto err_free_master; |
|
} |
|
dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); |
|
master->dma_tx = NULL; |
|
} |
|
|
|
master->dma_rx = dma_request_chan(&pdev->dev, "rx"); |
|
if (IS_ERR(master->dma_rx)) { |
|
if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { |
|
ret = -EPROBE_DEFER; |
|
goto err_free_dma_tx; |
|
} |
|
dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); |
|
master->dma_rx = NULL; |
|
} |
|
|
|
if (master->dma_tx && master->dma_rx) { |
|
sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; |
|
sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; |
|
master->can_dma = sun6i_spi_can_dma; |
|
} |
|
|
|
/* |
|
* This wake-up/shutdown pattern is to be able to have the |
|
* device woken up, even if runtime_pm is disabled |
|
*/ |
|
ret = sun6i_spi_runtime_resume(&pdev->dev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Couldn't resume the device\n"); |
|
goto err_free_dma_rx; |
|
} |
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT); |
|
pm_runtime_use_autosuspend(&pdev->dev); |
|
pm_runtime_set_active(&pdev->dev); |
|
pm_runtime_enable(&pdev->dev); |
|
|
|
ret = devm_spi_register_master(&pdev->dev, master); |
|
if (ret) { |
|
dev_err(&pdev->dev, "cannot register SPI master\n"); |
|
goto err_pm_disable; |
|
} |
|
|
|
return 0; |
|
|
|
err_pm_disable: |
|
pm_runtime_disable(&pdev->dev); |
|
sun6i_spi_runtime_suspend(&pdev->dev); |
|
err_free_dma_rx: |
|
if (master->dma_rx) |
|
dma_release_channel(master->dma_rx); |
|
err_free_dma_tx: |
|
if (master->dma_tx) |
|
dma_release_channel(master->dma_tx); |
|
err_free_master: |
|
spi_master_put(master); |
|
return ret; |
|
} |
|
|
|
static int sun6i_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_force_suspend(&pdev->dev); |
|
|
|
if (master->dma_tx) |
|
dma_release_channel(master->dma_tx); |
|
if (master->dma_rx) |
|
dma_release_channel(master->dma_rx); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id sun6i_spi_match[] = { |
|
{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, |
|
{ .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, sun6i_spi_match); |
|
|
|
static const struct dev_pm_ops sun6i_spi_pm_ops = { |
|
.runtime_resume = sun6i_spi_runtime_resume, |
|
.runtime_suspend = sun6i_spi_runtime_suspend, |
|
}; |
|
|
|
static struct platform_driver sun6i_spi_driver = { |
|
.probe = sun6i_spi_probe, |
|
.remove = sun6i_spi_remove, |
|
.driver = { |
|
.name = "sun6i-spi", |
|
.of_match_table = sun6i_spi_match, |
|
.pm = &sun6i_spi_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(sun6i_spi_driver); |
|
|
|
MODULE_AUTHOR("Pan Nan <[email protected]>"); |
|
MODULE_AUTHOR("Maxime Ripard <[email protected]>"); |
|
MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); |
|
MODULE_LICENSE("GPL");
|
|
|