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512 lines
11 KiB
512 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* SH SPI bus driver |
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* |
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* Copyright (C) 2011 Renesas Solutions Corp. |
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* |
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* Based on pxa2xx_spi.c: |
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/errno.h> |
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#include <linux/timer.h> |
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#include <linux/delay.h> |
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#include <linux/list.h> |
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#include <linux/workqueue.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <linux/spi/spi.h> |
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#define SPI_SH_TBR 0x00 |
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#define SPI_SH_RBR 0x00 |
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#define SPI_SH_CR1 0x08 |
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#define SPI_SH_CR2 0x10 |
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#define SPI_SH_CR3 0x18 |
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#define SPI_SH_CR4 0x20 |
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#define SPI_SH_CR5 0x28 |
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/* CR1 */ |
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#define SPI_SH_TBE 0x80 |
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#define SPI_SH_TBF 0x40 |
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#define SPI_SH_RBE 0x20 |
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#define SPI_SH_RBF 0x10 |
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#define SPI_SH_PFONRD 0x08 |
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#define SPI_SH_SSDB 0x04 |
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#define SPI_SH_SSD 0x02 |
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#define SPI_SH_SSA 0x01 |
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|
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/* CR2 */ |
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#define SPI_SH_RSTF 0x80 |
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#define SPI_SH_LOOPBK 0x40 |
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#define SPI_SH_CPOL 0x20 |
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#define SPI_SH_CPHA 0x10 |
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#define SPI_SH_L1M0 0x08 |
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/* CR3 */ |
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#define SPI_SH_MAX_BYTE 0xFF |
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/* CR4 */ |
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#define SPI_SH_TBEI 0x80 |
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#define SPI_SH_TBFI 0x40 |
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#define SPI_SH_RBEI 0x20 |
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#define SPI_SH_RBFI 0x10 |
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#define SPI_SH_WPABRT 0x04 |
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#define SPI_SH_SSS 0x01 |
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/* CR8 */ |
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#define SPI_SH_P1L0 0x80 |
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#define SPI_SH_PP1L0 0x40 |
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#define SPI_SH_MUXI 0x20 |
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#define SPI_SH_MUXIRQ 0x10 |
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#define SPI_SH_FIFO_SIZE 32 |
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#define SPI_SH_SEND_TIMEOUT (3 * HZ) |
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#define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3) |
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#undef DEBUG |
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struct spi_sh_data { |
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void __iomem *addr; |
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int irq; |
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struct spi_master *master; |
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struct list_head queue; |
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struct work_struct ws; |
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unsigned long cr1; |
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wait_queue_head_t wait; |
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spinlock_t lock; |
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int width; |
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}; |
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static void spi_sh_write(struct spi_sh_data *ss, unsigned long data, |
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unsigned long offset) |
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{ |
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if (ss->width == 8) |
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iowrite8(data, ss->addr + (offset >> 2)); |
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else if (ss->width == 32) |
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iowrite32(data, ss->addr + offset); |
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} |
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static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset) |
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{ |
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if (ss->width == 8) |
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return ioread8(ss->addr + (offset >> 2)); |
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else if (ss->width == 32) |
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return ioread32(ss->addr + offset); |
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else |
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return 0; |
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} |
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static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val, |
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unsigned long offset) |
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{ |
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unsigned long tmp; |
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tmp = spi_sh_read(ss, offset); |
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tmp |= val; |
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spi_sh_write(ss, tmp, offset); |
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} |
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static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val, |
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unsigned long offset) |
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{ |
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unsigned long tmp; |
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tmp = spi_sh_read(ss, offset); |
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tmp &= ~val; |
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spi_sh_write(ss, tmp, offset); |
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} |
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static void clear_fifo(struct spi_sh_data *ss) |
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{ |
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spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2); |
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spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2); |
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} |
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static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss) |
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{ |
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int timeout = 100000; |
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while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { |
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udelay(10); |
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if (timeout-- < 0) |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss) |
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{ |
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int timeout = 100000; |
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while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) { |
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udelay(10); |
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if (timeout-- < 0) |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg, |
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struct spi_transfer *t) |
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{ |
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int i, retval = 0; |
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int remain = t->len; |
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int cur_len; |
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unsigned char *data; |
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long ret; |
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if (t->len) |
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); |
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data = (unsigned char *)t->tx_buf; |
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while (remain > 0) { |
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cur_len = min(SPI_SH_FIFO_SIZE, remain); |
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for (i = 0; i < cur_len && |
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!(spi_sh_read(ss, SPI_SH_CR4) & |
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SPI_SH_WPABRT) && |
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!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF); |
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i++) |
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spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR); |
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if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) { |
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/* Abort SPI operation */ |
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spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4); |
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retval = -EIO; |
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break; |
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} |
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cur_len = i; |
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remain -= cur_len; |
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data += cur_len; |
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if (remain > 0) { |
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ss->cr1 &= ~SPI_SH_TBE; |
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spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4); |
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ret = wait_event_interruptible_timeout(ss->wait, |
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ss->cr1 & SPI_SH_TBE, |
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SPI_SH_SEND_TIMEOUT); |
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if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) { |
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printk(KERN_ERR "%s: timeout\n", __func__); |
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return -ETIMEDOUT; |
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} |
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} |
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} |
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if (list_is_last(&t->transfer_list, &mesg->transfers)) { |
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spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); |
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); |
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ss->cr1 &= ~SPI_SH_TBE; |
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spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4); |
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ret = wait_event_interruptible_timeout(ss->wait, |
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ss->cr1 & SPI_SH_TBE, |
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SPI_SH_SEND_TIMEOUT); |
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if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) { |
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printk(KERN_ERR "%s: timeout\n", __func__); |
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return -ETIMEDOUT; |
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} |
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} |
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return retval; |
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} |
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static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg, |
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struct spi_transfer *t) |
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{ |
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int i; |
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int remain = t->len; |
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int cur_len; |
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unsigned char *data; |
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long ret; |
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if (t->len > SPI_SH_MAX_BYTE) |
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spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3); |
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else |
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spi_sh_write(ss, t->len, SPI_SH_CR3); |
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spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); |
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); |
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spi_sh_wait_write_buffer_empty(ss); |
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data = (unsigned char *)t->rx_buf; |
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while (remain > 0) { |
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if (remain >= SPI_SH_FIFO_SIZE) { |
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ss->cr1 &= ~SPI_SH_RBF; |
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spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4); |
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ret = wait_event_interruptible_timeout(ss->wait, |
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ss->cr1 & SPI_SH_RBF, |
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SPI_SH_RECEIVE_TIMEOUT); |
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if (ret == 0 && |
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spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { |
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printk(KERN_ERR "%s: timeout\n", __func__); |
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return -ETIMEDOUT; |
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} |
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} |
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cur_len = min(SPI_SH_FIFO_SIZE, remain); |
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for (i = 0; i < cur_len; i++) { |
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if (spi_sh_wait_receive_buffer(ss)) |
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break; |
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data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR); |
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} |
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remain -= cur_len; |
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data += cur_len; |
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} |
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/* deassert CS when SPI is receiving. */ |
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if (t->len > SPI_SH_MAX_BYTE) { |
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clear_fifo(ss); |
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spi_sh_write(ss, 1, SPI_SH_CR3); |
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} else { |
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spi_sh_write(ss, 0, SPI_SH_CR3); |
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} |
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return 0; |
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} |
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static void spi_sh_work(struct work_struct *work) |
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{ |
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struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws); |
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struct spi_message *mesg; |
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struct spi_transfer *t; |
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unsigned long flags; |
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int ret; |
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pr_debug("%s: enter\n", __func__); |
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spin_lock_irqsave(&ss->lock, flags); |
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while (!list_empty(&ss->queue)) { |
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mesg = list_entry(ss->queue.next, struct spi_message, queue); |
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list_del_init(&mesg->queue); |
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spin_unlock_irqrestore(&ss->lock, flags); |
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list_for_each_entry(t, &mesg->transfers, transfer_list) { |
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pr_debug("tx_buf = %p, rx_buf = %p\n", |
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t->tx_buf, t->rx_buf); |
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pr_debug("len = %d, delay_usecs = %d\n", |
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t->len, t->delay_usecs); |
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if (t->tx_buf) { |
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ret = spi_sh_send(ss, mesg, t); |
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if (ret < 0) |
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goto error; |
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} |
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if (t->rx_buf) { |
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ret = spi_sh_receive(ss, mesg, t); |
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if (ret < 0) |
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goto error; |
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} |
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mesg->actual_length += t->len; |
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} |
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spin_lock_irqsave(&ss->lock, flags); |
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mesg->status = 0; |
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if (mesg->complete) |
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mesg->complete(mesg->context); |
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} |
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clear_fifo(ss); |
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spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1); |
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udelay(100); |
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spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD, |
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SPI_SH_CR1); |
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clear_fifo(ss); |
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spin_unlock_irqrestore(&ss->lock, flags); |
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return; |
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error: |
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mesg->status = ret; |
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if (mesg->complete) |
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mesg->complete(mesg->context); |
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spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD, |
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SPI_SH_CR1); |
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clear_fifo(ss); |
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} |
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static int spi_sh_setup(struct spi_device *spi) |
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{ |
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struct spi_sh_data *ss = spi_master_get_devdata(spi->master); |
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pr_debug("%s: enter\n", __func__); |
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spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */ |
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spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */ |
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spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */ |
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clear_fifo(ss); |
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/* 1/8 clock */ |
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spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2); |
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udelay(10); |
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return 0; |
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} |
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static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg) |
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{ |
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struct spi_sh_data *ss = spi_master_get_devdata(spi->master); |
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unsigned long flags; |
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pr_debug("%s: enter\n", __func__); |
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pr_debug("\tmode = %02x\n", spi->mode); |
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spin_lock_irqsave(&ss->lock, flags); |
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mesg->actual_length = 0; |
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mesg->status = -EINPROGRESS; |
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spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1); |
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list_add_tail(&mesg->queue, &ss->queue); |
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schedule_work(&ss->ws); |
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spin_unlock_irqrestore(&ss->lock, flags); |
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return 0; |
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} |
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static void spi_sh_cleanup(struct spi_device *spi) |
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{ |
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struct spi_sh_data *ss = spi_master_get_devdata(spi->master); |
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pr_debug("%s: enter\n", __func__); |
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spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD, |
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SPI_SH_CR1); |
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} |
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static irqreturn_t spi_sh_irq(int irq, void *_ss) |
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{ |
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struct spi_sh_data *ss = (struct spi_sh_data *)_ss; |
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unsigned long cr1; |
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cr1 = spi_sh_read(ss, SPI_SH_CR1); |
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if (cr1 & SPI_SH_TBE) |
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ss->cr1 |= SPI_SH_TBE; |
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if (cr1 & SPI_SH_TBF) |
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ss->cr1 |= SPI_SH_TBF; |
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if (cr1 & SPI_SH_RBE) |
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ss->cr1 |= SPI_SH_RBE; |
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if (cr1 & SPI_SH_RBF) |
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ss->cr1 |= SPI_SH_RBF; |
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if (ss->cr1) { |
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spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4); |
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wake_up(&ss->wait); |
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} |
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return IRQ_HANDLED; |
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} |
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static int spi_sh_remove(struct platform_device *pdev) |
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{ |
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struct spi_sh_data *ss = platform_get_drvdata(pdev); |
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spi_unregister_master(ss->master); |
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flush_work(&ss->ws); |
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free_irq(ss->irq, ss); |
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return 0; |
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} |
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static int spi_sh_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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struct spi_master *master; |
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struct spi_sh_data *ss; |
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int ret, irq; |
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/* get base addr */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (unlikely(res == NULL)) { |
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dev_err(&pdev->dev, "invalid resource\n"); |
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return -EINVAL; |
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} |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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master = devm_spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data)); |
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if (master == NULL) { |
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dev_err(&pdev->dev, "spi_alloc_master error.\n"); |
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return -ENOMEM; |
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} |
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ss = spi_master_get_devdata(master); |
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platform_set_drvdata(pdev, ss); |
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switch (res->flags & IORESOURCE_MEM_TYPE_MASK) { |
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case IORESOURCE_MEM_8BIT: |
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ss->width = 8; |
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break; |
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case IORESOURCE_MEM_32BIT: |
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ss->width = 32; |
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break; |
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default: |
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dev_err(&pdev->dev, "No support width\n"); |
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return -ENODEV; |
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} |
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ss->irq = irq; |
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ss->master = master; |
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ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
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if (ss->addr == NULL) { |
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dev_err(&pdev->dev, "ioremap error.\n"); |
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return -ENOMEM; |
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} |
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INIT_LIST_HEAD(&ss->queue); |
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spin_lock_init(&ss->lock); |
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INIT_WORK(&ss->ws, spi_sh_work); |
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init_waitqueue_head(&ss->wait); |
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ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "request_irq error\n"); |
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return ret; |
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} |
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master->num_chipselect = 2; |
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master->bus_num = pdev->id; |
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master->setup = spi_sh_setup; |
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master->transfer = spi_sh_transfer; |
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master->cleanup = spi_sh_cleanup; |
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ret = spi_register_master(master); |
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if (ret < 0) { |
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printk(KERN_ERR "spi_register_master error.\n"); |
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goto error3; |
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} |
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return 0; |
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error3: |
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free_irq(irq, ss); |
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return ret; |
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} |
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static struct platform_driver spi_sh_driver = { |
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.probe = spi_sh_probe, |
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.remove = spi_sh_remove, |
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.driver = { |
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.name = "sh_spi", |
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}, |
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}; |
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module_platform_driver(spi_sh_driver); |
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|
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MODULE_DESCRIPTION("SH SPI bus driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_AUTHOR("Yoshihiro Shimoda"); |
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MODULE_ALIAS("platform:sh_spi");
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