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197 lines
4.7 KiB
197 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* SH SCI SPI interface |
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* |
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* Copyright (c) 2008 Magnus Damm |
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* |
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* Based on S3C24XX GPIO based SPI driver, which is: |
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* Copyright (c) 2006 Ben Dooks |
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* Copyright (c) 2006 Simtec Electronics |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/spinlock.h> |
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#include <linux/platform_device.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/spi_bitbang.h> |
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#include <linux/module.h> |
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#include <asm/spi.h> |
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#include <asm/io.h> |
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struct sh_sci_spi { |
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struct spi_bitbang bitbang; |
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void __iomem *membase; |
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unsigned char val; |
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struct sh_spi_info *info; |
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struct platform_device *dev; |
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}; |
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#define SCSPTR(sp) (sp->membase + 0x1c) |
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#define PIN_SCK (1 << 2) |
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#define PIN_TXD (1 << 0) |
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#define PIN_RXD PIN_TXD |
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#define PIN_INIT ((1 << 1) | (1 << 3) | PIN_SCK | PIN_TXD) |
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static inline void setbits(struct sh_sci_spi *sp, int bits, int on) |
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{ |
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/* |
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* We are the only user of SCSPTR so no locking is required. |
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* Reading bit 2 and 0 in SCSPTR gives pin state as input. |
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* Writing the same bits sets the output value. |
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* This makes regular read-modify-write difficult so we |
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* use sp->val to keep track of the latest register value. |
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*/ |
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if (on) |
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sp->val |= bits; |
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else |
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sp->val &= ~bits; |
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iowrite8(sp->val, SCSPTR(sp)); |
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} |
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static inline void setsck(struct spi_device *dev, int on) |
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{ |
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setbits(spi_master_get_devdata(dev->master), PIN_SCK, on); |
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} |
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static inline void setmosi(struct spi_device *dev, int on) |
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{ |
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setbits(spi_master_get_devdata(dev->master), PIN_TXD, on); |
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} |
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static inline u32 getmiso(struct spi_device *dev) |
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{ |
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struct sh_sci_spi *sp = spi_master_get_devdata(dev->master); |
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return (ioread8(SCSPTR(sp)) & PIN_RXD) ? 1 : 0; |
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} |
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#define spidelay(x) ndelay(x) |
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#include "spi-bitbang-txrx.h" |
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static u32 sh_sci_spi_txrx_mode0(struct spi_device *spi, |
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unsigned nsecs, u32 word, u8 bits, |
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unsigned flags) |
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{ |
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return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits); |
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} |
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static u32 sh_sci_spi_txrx_mode1(struct spi_device *spi, |
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unsigned nsecs, u32 word, u8 bits, |
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unsigned flags) |
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{ |
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return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits); |
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} |
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static u32 sh_sci_spi_txrx_mode2(struct spi_device *spi, |
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unsigned nsecs, u32 word, u8 bits, |
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unsigned flags) |
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{ |
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return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits); |
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} |
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static u32 sh_sci_spi_txrx_mode3(struct spi_device *spi, |
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unsigned nsecs, u32 word, u8 bits, |
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unsigned flags) |
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{ |
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return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits); |
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} |
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static void sh_sci_spi_chipselect(struct spi_device *dev, int value) |
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{ |
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struct sh_sci_spi *sp = spi_master_get_devdata(dev->master); |
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if (sp->info->chip_select) |
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(sp->info->chip_select)(sp->info, dev->chip_select, value); |
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} |
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static int sh_sci_spi_probe(struct platform_device *dev) |
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{ |
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struct resource *r; |
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struct spi_master *master; |
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struct sh_sci_spi *sp; |
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int ret; |
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master = spi_alloc_master(&dev->dev, sizeof(struct sh_sci_spi)); |
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if (master == NULL) { |
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dev_err(&dev->dev, "failed to allocate spi master\n"); |
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ret = -ENOMEM; |
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goto err0; |
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} |
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sp = spi_master_get_devdata(master); |
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platform_set_drvdata(dev, sp); |
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sp->info = dev_get_platdata(&dev->dev); |
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if (!sp->info) { |
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dev_err(&dev->dev, "platform data is missing\n"); |
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ret = -ENOENT; |
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goto err1; |
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} |
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/* setup spi bitbang adaptor */ |
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sp->bitbang.master = master; |
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sp->bitbang.master->bus_num = sp->info->bus_num; |
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sp->bitbang.master->num_chipselect = sp->info->num_chipselect; |
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sp->bitbang.chipselect = sh_sci_spi_chipselect; |
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sp->bitbang.txrx_word[SPI_MODE_0] = sh_sci_spi_txrx_mode0; |
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sp->bitbang.txrx_word[SPI_MODE_1] = sh_sci_spi_txrx_mode1; |
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sp->bitbang.txrx_word[SPI_MODE_2] = sh_sci_spi_txrx_mode2; |
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sp->bitbang.txrx_word[SPI_MODE_3] = sh_sci_spi_txrx_mode3; |
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r = platform_get_resource(dev, IORESOURCE_MEM, 0); |
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if (r == NULL) { |
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ret = -ENOENT; |
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goto err1; |
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} |
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sp->membase = ioremap(r->start, resource_size(r)); |
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if (!sp->membase) { |
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ret = -ENXIO; |
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goto err1; |
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} |
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sp->val = ioread8(SCSPTR(sp)); |
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setbits(sp, PIN_INIT, 1); |
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ret = spi_bitbang_start(&sp->bitbang); |
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if (!ret) |
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return 0; |
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setbits(sp, PIN_INIT, 0); |
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iounmap(sp->membase); |
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err1: |
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spi_master_put(sp->bitbang.master); |
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err0: |
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return ret; |
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} |
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static int sh_sci_spi_remove(struct platform_device *dev) |
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{ |
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struct sh_sci_spi *sp = platform_get_drvdata(dev); |
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spi_bitbang_stop(&sp->bitbang); |
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setbits(sp, PIN_INIT, 0); |
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iounmap(sp->membase); |
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spi_master_put(sp->bitbang.master); |
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return 0; |
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} |
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static struct platform_driver sh_sci_spi_drv = { |
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.probe = sh_sci_spi_probe, |
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.remove = sh_sci_spi_remove, |
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.driver = { |
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.name = "spi_sh_sci", |
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}, |
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}; |
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module_platform_driver(sh_sci_spi_drv); |
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MODULE_DESCRIPTION("SH SCI SPI Driver"); |
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MODULE_AUTHOR("Magnus Damm <[email protected]>"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:spi_sh_sci");
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