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213 lines
5.2 KiB
213 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* SPI controller driver for the Mikrotik RB4xx boards |
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* |
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* Copyright (C) 2010 Gabor Juhos <[email protected]> |
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* Copyright (C) 2015 Bert Vermeulen <[email protected]> |
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* |
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* This file was based on the patches for Linux 2.6.27.39 published by |
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* MikroTik for their RouterBoard 4xx series devices. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/spi/spi.h> |
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#include <linux/of.h> |
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#include <asm/mach-ath79/ar71xx_regs.h> |
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struct rb4xx_spi { |
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void __iomem *base; |
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struct clk *clk; |
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}; |
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static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg) |
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{ |
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return __raw_readl(rbspi->base + reg); |
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} |
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static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value) |
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{ |
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__raw_writel(value, rbspi->base + reg); |
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} |
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static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value) |
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{ |
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u32 regval; |
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regval = spi_ioc; |
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if (value & BIT(0)) |
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regval |= AR71XX_SPI_IOC_DO; |
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); |
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK); |
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} |
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static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte) |
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{ |
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int i; |
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for (i = 7; i >= 0; i--) |
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do_spi_clk(rbspi, spi_ioc, byte >> i); |
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} |
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/* The CS2 pin is used to clock in a second bit per clock cycle. */ |
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static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc, |
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u8 value) |
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{ |
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u32 regval; |
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regval = spi_ioc; |
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if (value & BIT(1)) |
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regval |= AR71XX_SPI_IOC_DO; |
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if (value & BIT(0)) |
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regval |= AR71XX_SPI_IOC_CS2; |
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); |
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK); |
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} |
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/* Two bits at a time, msb first */ |
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static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte) |
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{ |
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do_spi_clk_two(rbspi, spi_ioc, byte >> 6); |
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do_spi_clk_two(rbspi, spi_ioc, byte >> 4); |
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do_spi_clk_two(rbspi, spi_ioc, byte >> 2); |
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do_spi_clk_two(rbspi, spi_ioc, byte >> 0); |
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} |
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static void rb4xx_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); |
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/* |
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* Setting CS is done along with bitbanging the actual values, |
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* since it's all on the same hardware register. However the |
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* CPLD needs CS deselected after every command. |
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*/ |
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if (enable) |
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, |
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AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1); |
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} |
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static int rb4xx_transfer_one(struct spi_master *master, |
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struct spi_device *spi, struct spi_transfer *t) |
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{ |
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struct rb4xx_spi *rbspi = spi_master_get_devdata(master); |
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int i; |
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u32 spi_ioc; |
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u8 *rx_buf; |
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const u8 *tx_buf; |
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/* |
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* Prime the SPI register with the SPI device selected. The m25p80 boot |
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* flash and CPLD share the CS0 pin. This works because the CPLD's |
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* command set was designed to almost not clash with that of the |
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* boot flash. |
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*/ |
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if (spi->chip_select == 2) |
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/* MMC */ |
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spi_ioc = AR71XX_SPI_IOC_CS0; |
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else |
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/* Boot flash and CPLD */ |
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spi_ioc = AR71XX_SPI_IOC_CS1; |
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tx_buf = t->tx_buf; |
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rx_buf = t->rx_buf; |
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for (i = 0; i < t->len; ++i) { |
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if (t->tx_nbits == SPI_NBITS_DUAL) |
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/* CPLD can use two-wire transfers */ |
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do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]); |
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else |
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do_spi_byte(rbspi, spi_ioc, tx_buf[i]); |
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if (!rx_buf) |
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continue; |
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rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS); |
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} |
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spi_finalize_current_transfer(master); |
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return 0; |
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} |
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static int rb4xx_spi_probe(struct platform_device *pdev) |
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{ |
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struct spi_master *master; |
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struct clk *ahb_clk; |
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struct rb4xx_spi *rbspi; |
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int err; |
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void __iomem *spi_base; |
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spi_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(spi_base)) |
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return PTR_ERR(spi_base); |
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master = devm_spi_alloc_master(&pdev->dev, sizeof(*rbspi)); |
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if (!master) |
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return -ENOMEM; |
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ahb_clk = devm_clk_get(&pdev->dev, "ahb"); |
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if (IS_ERR(ahb_clk)) |
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return PTR_ERR(ahb_clk); |
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master->dev.of_node = pdev->dev.of_node; |
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master->bus_num = 0; |
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master->num_chipselect = 3; |
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master->mode_bits = SPI_TX_DUAL; |
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master->bits_per_word_mask = SPI_BPW_MASK(8); |
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master->flags = SPI_MASTER_MUST_TX; |
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master->transfer_one = rb4xx_transfer_one; |
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master->set_cs = rb4xx_set_cs; |
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rbspi = spi_master_get_devdata(master); |
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rbspi->base = spi_base; |
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rbspi->clk = ahb_clk; |
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platform_set_drvdata(pdev, rbspi); |
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err = devm_spi_register_master(&pdev->dev, master); |
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if (err) { |
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dev_err(&pdev->dev, "failed to register SPI master\n"); |
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return err; |
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} |
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err = clk_prepare_enable(ahb_clk); |
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if (err) |
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return err; |
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/* Enable SPI */ |
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rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); |
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return 0; |
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} |
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static int rb4xx_spi_remove(struct platform_device *pdev) |
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{ |
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struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); |
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clk_disable_unprepare(rbspi->clk); |
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return 0; |
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} |
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static const struct of_device_id rb4xx_spi_dt_match[] = { |
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{ .compatible = "mikrotik,rb4xx-spi" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, rb4xx_spi_dt_match); |
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static struct platform_driver rb4xx_spi_drv = { |
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.probe = rb4xx_spi_probe, |
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.remove = rb4xx_spi_remove, |
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.driver = { |
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.name = "rb4xx-spi", |
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.of_match_table = of_match_ptr(rb4xx_spi_dt_match), |
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}, |
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}; |
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module_platform_driver(rb4xx_spi_drv); |
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MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver"); |
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MODULE_AUTHOR("Gabor Juhos <[email protected]>"); |
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MODULE_AUTHOR("Bert Vermeulen <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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