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857 lines
21 KiB
857 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Marvell Orion SPI controller driver |
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* |
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* Author: Shadi Ammouri <[email protected]> |
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* Copyright (C) 2007-2008 Marvell Ltd. |
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*/ |
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|
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#include <linux/interrupt.h> |
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#include <linux/delay.h> |
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#include <linux/platform_device.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/spi/spi.h> |
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#include <linux/module.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/clk.h> |
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#include <linux/sizes.h> |
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#include <asm/unaligned.h> |
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#define DRIVER_NAME "orion_spi" |
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/* Runtime PM autosuspend timeout: PM is fairly light on this driver */ |
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#define SPI_AUTOSUSPEND_TIMEOUT 200 |
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/* Some SoCs using this driver support up to 8 chip selects. |
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* It is up to the implementer to only use the chip selects |
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* that are available. |
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*/ |
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#define ORION_NUM_CHIPSELECTS 8 |
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#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ |
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#define ORION_SPI_IF_CTRL_REG 0x00 |
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#define ORION_SPI_IF_CONFIG_REG 0x04 |
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#define ORION_SPI_IF_RXLSBF BIT(14) |
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#define ORION_SPI_IF_TXLSBF BIT(13) |
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#define ORION_SPI_DATA_OUT_REG 0x08 |
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#define ORION_SPI_DATA_IN_REG 0x0c |
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#define ORION_SPI_INT_CAUSE_REG 0x10 |
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#define ORION_SPI_TIMING_PARAMS_REG 0x18 |
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|
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/* Register for the "Direct Mode" */ |
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#define SPI_DIRECT_WRITE_CONFIG_REG 0x20 |
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#define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) |
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#define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) |
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#define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) |
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#define ORION_SPI_MODE_CPOL (1 << 11) |
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#define ORION_SPI_MODE_CPHA (1 << 12) |
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#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) |
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#define ORION_SPI_CLK_PRESCALE_MASK 0x1F |
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#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF |
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#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ |
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ORION_SPI_MODE_CPHA) |
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#define ORION_SPI_CS_MASK 0x1C |
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#define ORION_SPI_CS_SHIFT 2 |
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#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ |
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ORION_SPI_CS_MASK) |
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enum orion_spi_type { |
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ORION_SPI, |
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ARMADA_SPI, |
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}; |
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struct orion_spi_dev { |
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enum orion_spi_type typ; |
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/* |
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* min_divisor and max_hz should be exclusive, the only we can |
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* have both is for managing the armada-370-spi case with old |
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* device tree |
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*/ |
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unsigned long max_hz; |
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unsigned int min_divisor; |
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unsigned int max_divisor; |
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u32 prescale_mask; |
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bool is_errata_50mhz_ac; |
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}; |
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struct orion_direct_acc { |
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void __iomem *vaddr; |
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u32 size; |
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}; |
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struct orion_child_options { |
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struct orion_direct_acc direct_access; |
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}; |
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struct orion_spi { |
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struct spi_master *master; |
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void __iomem *base; |
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struct clk *clk; |
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struct clk *axi_clk; |
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const struct orion_spi_dev *devdata; |
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struct device *dev; |
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struct orion_child_options child[ORION_NUM_CHIPSELECTS]; |
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}; |
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#ifdef CONFIG_PM |
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static int orion_spi_runtime_suspend(struct device *dev); |
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static int orion_spi_runtime_resume(struct device *dev); |
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#endif |
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static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) |
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{ |
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return orion_spi->base + reg; |
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} |
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static inline void |
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orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) |
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{ |
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void __iomem *reg_addr = spi_reg(orion_spi, reg); |
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u32 val; |
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val = readl(reg_addr); |
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val |= mask; |
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writel(val, reg_addr); |
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} |
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static inline void |
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orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) |
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{ |
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void __iomem *reg_addr = spi_reg(orion_spi, reg); |
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u32 val; |
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val = readl(reg_addr); |
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val &= ~mask; |
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writel(val, reg_addr); |
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} |
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static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) |
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{ |
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u32 tclk_hz; |
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u32 rate; |
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u32 prescale; |
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u32 reg; |
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struct orion_spi *orion_spi; |
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const struct orion_spi_dev *devdata; |
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orion_spi = spi_master_get_devdata(spi->master); |
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devdata = orion_spi->devdata; |
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tclk_hz = clk_get_rate(orion_spi->clk); |
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if (devdata->typ == ARMADA_SPI) { |
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/* |
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* Given the core_clk (tclk_hz) and the target rate (speed) we |
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* determine the best values for SPR (in [0 .. 15]) and SPPR (in |
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* [0..7]) such that |
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* |
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* core_clk / (SPR * 2 ** SPPR) |
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* |
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* is as big as possible but not bigger than speed. |
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*/ |
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/* best integer divider: */ |
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unsigned divider = DIV_ROUND_UP(tclk_hz, speed); |
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unsigned spr, sppr; |
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if (divider < 16) { |
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/* This is the easy case, divider is less than 16 */ |
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spr = divider; |
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sppr = 0; |
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} else { |
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unsigned two_pow_sppr; |
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/* |
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* Find the highest bit set in divider. This and the |
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* three next bits define SPR (apart from rounding). |
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* SPPR is then the number of zero bits that must be |
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* appended: |
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*/ |
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sppr = fls(divider) - 4; |
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/* |
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* As SPR only has 4 bits, we have to round divider up |
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* to the next multiple of 2 ** sppr. |
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*/ |
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two_pow_sppr = 1 << sppr; |
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divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; |
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/* |
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* recalculate sppr as rounding up divider might have |
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* increased it enough to change the position of the |
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* highest set bit. In this case the bit that now |
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* doesn't make it into SPR is 0, so there is no need to |
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* round again. |
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*/ |
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sppr = fls(divider) - 4; |
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spr = divider >> sppr; |
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/* |
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* Now do range checking. SPR is constructed to have a |
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* width of 4 bits, so this is fine for sure. So we |
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* still need to check for sppr to fit into 3 bits: |
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*/ |
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if (sppr > 7) |
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return -EINVAL; |
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} |
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prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; |
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} else { |
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/* |
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* the supported rates are: 4,6,8...30 |
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* round up as we look for equal or less speed |
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*/ |
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rate = DIV_ROUND_UP(tclk_hz, speed); |
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rate = roundup(rate, 2); |
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/* check if requested speed is too small */ |
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if (rate > 30) |
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return -EINVAL; |
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if (rate < 4) |
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rate = 4; |
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/* Convert the rate to SPI clock divisor value. */ |
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prescale = 0x10 + rate/2; |
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} |
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reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
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reg = ((reg & ~devdata->prescale_mask) | prescale); |
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writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
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return 0; |
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} |
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static void |
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orion_spi_mode_set(struct spi_device *spi) |
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{ |
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u32 reg; |
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struct orion_spi *orion_spi; |
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orion_spi = spi_master_get_devdata(spi->master); |
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reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
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reg &= ~ORION_SPI_MODE_MASK; |
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if (spi->mode & SPI_CPOL) |
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reg |= ORION_SPI_MODE_CPOL; |
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if (spi->mode & SPI_CPHA) |
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reg |= ORION_SPI_MODE_CPHA; |
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if (spi->mode & SPI_LSB_FIRST) |
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reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; |
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else |
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reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); |
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writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
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} |
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static void |
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orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) |
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{ |
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u32 reg; |
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struct orion_spi *orion_spi; |
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orion_spi = spi_master_get_devdata(spi->master); |
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/* |
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* Erratum description: (Erratum NO. FE-9144572) The device |
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* SPI interface supports frequencies of up to 50 MHz. |
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* However, due to this erratum, when the device core clock is |
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* 250 MHz and the SPI interfaces is configured for 50MHz SPI |
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* clock and CPOL=CPHA=1 there might occur data corruption on |
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* reads from the SPI device. |
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* Erratum Workaround: |
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* Work in one of the following configurations: |
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* 1. Set CPOL=CPHA=0 in "SPI Interface Configuration |
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* Register". |
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* 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 |
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* Register" before setting the interface. |
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*/ |
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reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); |
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reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; |
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if (clk_get_rate(orion_spi->clk) == 250000000 && |
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speed == 50000000 && spi->mode & SPI_CPOL && |
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spi->mode & SPI_CPHA) |
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reg |= ORION_SPI_TMISO_SAMPLE_2; |
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else |
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reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ |
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writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); |
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} |
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/* |
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* called only when no transfer is active on the bus |
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*/ |
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static int |
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orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
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{ |
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struct orion_spi *orion_spi; |
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unsigned int speed = spi->max_speed_hz; |
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unsigned int bits_per_word = spi->bits_per_word; |
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int rc; |
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orion_spi = spi_master_get_devdata(spi->master); |
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if ((t != NULL) && t->speed_hz) |
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speed = t->speed_hz; |
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if ((t != NULL) && t->bits_per_word) |
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bits_per_word = t->bits_per_word; |
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orion_spi_mode_set(spi); |
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if (orion_spi->devdata->is_errata_50mhz_ac) |
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orion_spi_50mhz_ac_timing_erratum(spi, speed); |
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rc = orion_spi_baudrate_set(spi, speed); |
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if (rc) |
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return rc; |
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if (bits_per_word == 16) |
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orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, |
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ORION_SPI_IF_8_16_BIT_MODE); |
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else |
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orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, |
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ORION_SPI_IF_8_16_BIT_MODE); |
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return 0; |
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} |
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static void orion_spi_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct orion_spi *orion_spi; |
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orion_spi = spi_master_get_devdata(spi->master); |
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/* |
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* If this line is using a GPIO to control chip select, this internal |
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* .set_cs() function will still be called, so we clear any previous |
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* chip select. The CS we activate will not have any elecrical effect, |
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* as it is handled by a GPIO, but that doesn't matter. What we need |
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* is to deassert the old chip select and assert some other chip select. |
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*/ |
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orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); |
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orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, |
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ORION_SPI_CS(spi->chip_select)); |
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/* |
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* Chip select logic is inverted from spi_set_cs(). For lines using a |
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* GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens |
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* in the GPIO library, but we don't care about that, because in those |
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* cases we are dealing with an unused native CS anyways so the polarity |
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* doesn't matter. |
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*/ |
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if (!enable) |
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orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
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else |
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orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
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} |
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static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) |
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{ |
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int i; |
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for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { |
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if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) |
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return 1; |
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udelay(1); |
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} |
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return -1; |
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} |
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static inline int |
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orion_spi_write_read_8bit(struct spi_device *spi, |
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const u8 **tx_buf, u8 **rx_buf) |
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{ |
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void __iomem *tx_reg, *rx_reg, *int_reg; |
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struct orion_spi *orion_spi; |
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bool cs_single_byte; |
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cs_single_byte = spi->mode & SPI_CS_WORD; |
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orion_spi = spi_master_get_devdata(spi->master); |
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if (cs_single_byte) |
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orion_spi_set_cs(spi, 0); |
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tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); |
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rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); |
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int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); |
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/* clear the interrupt cause register */ |
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writel(0x0, int_reg); |
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if (tx_buf && *tx_buf) |
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writel(*(*tx_buf)++, tx_reg); |
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else |
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writel(0, tx_reg); |
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if (orion_spi_wait_till_ready(orion_spi) < 0) { |
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if (cs_single_byte) { |
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orion_spi_set_cs(spi, 1); |
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/* Satisfy some SLIC devices requirements */ |
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udelay(4); |
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} |
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dev_err(&spi->dev, "TXS timed out\n"); |
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return -1; |
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} |
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if (rx_buf && *rx_buf) |
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*(*rx_buf)++ = readl(rx_reg); |
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if (cs_single_byte) { |
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orion_spi_set_cs(spi, 1); |
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/* Satisfy some SLIC devices requirements */ |
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udelay(4); |
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} |
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return 1; |
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} |
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static inline int |
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orion_spi_write_read_16bit(struct spi_device *spi, |
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const u16 **tx_buf, u16 **rx_buf) |
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{ |
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void __iomem *tx_reg, *rx_reg, *int_reg; |
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struct orion_spi *orion_spi; |
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if (spi->mode & SPI_CS_WORD) { |
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dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n"); |
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return -1; |
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} |
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orion_spi = spi_master_get_devdata(spi->master); |
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tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); |
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rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); |
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int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); |
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/* clear the interrupt cause register */ |
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writel(0x0, int_reg); |
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if (tx_buf && *tx_buf) |
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writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); |
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else |
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writel(0, tx_reg); |
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if (orion_spi_wait_till_ready(orion_spi) < 0) { |
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dev_err(&spi->dev, "TXS timed out\n"); |
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return -1; |
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} |
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if (rx_buf && *rx_buf) |
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put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); |
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return 1; |
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} |
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static unsigned int |
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orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) |
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{ |
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unsigned int count; |
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int word_len; |
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struct orion_spi *orion_spi; |
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int cs = spi->chip_select; |
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void __iomem *vaddr; |
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word_len = spi->bits_per_word; |
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count = xfer->len; |
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orion_spi = spi_master_get_devdata(spi->master); |
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/* |
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* Use SPI direct write mode if base address is available |
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* and SPI_CS_WORD flag is not set. |
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* Otherwise fall back to PIO mode for this transfer. |
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*/ |
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vaddr = orion_spi->child[cs].direct_access.vaddr; |
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if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) { |
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unsigned int cnt = count / 4; |
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unsigned int rem = count % 4; |
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/* |
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* Send the TX-data to the SPI device via the direct |
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* mapped address window |
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*/ |
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iowrite32_rep(vaddr, xfer->tx_buf, cnt); |
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if (rem) { |
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u32 *buf = (u32 *)xfer->tx_buf; |
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iowrite8_rep(vaddr, &buf[cnt], rem); |
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} |
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return count; |
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} |
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if (word_len == 8) { |
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const u8 *tx = xfer->tx_buf; |
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u8 *rx = xfer->rx_buf; |
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do { |
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if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) |
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goto out; |
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count--; |
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spi_delay_exec(&xfer->word_delay, xfer); |
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} while (count); |
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} else if (word_len == 16) { |
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const u16 *tx = xfer->tx_buf; |
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u16 *rx = xfer->rx_buf; |
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do { |
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if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) |
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goto out; |
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count -= 2; |
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spi_delay_exec(&xfer->word_delay, xfer); |
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} while (count); |
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} |
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out: |
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return xfer->len - count; |
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} |
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static int orion_spi_transfer_one(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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int status = 0; |
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status = orion_spi_setup_transfer(spi, t); |
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if (status < 0) |
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return status; |
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if (t->len) |
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orion_spi_write_read(spi, t); |
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return status; |
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} |
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static int orion_spi_setup(struct spi_device *spi) |
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{ |
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int ret; |
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#ifdef CONFIG_PM |
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struct orion_spi *orion_spi = spi_master_get_devdata(spi->master); |
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struct device *dev = orion_spi->dev; |
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orion_spi_runtime_resume(dev); |
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#endif |
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ret = orion_spi_setup_transfer(spi, NULL); |
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|
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#ifdef CONFIG_PM |
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orion_spi_runtime_suspend(dev); |
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#endif |
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|
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return ret; |
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} |
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|
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static int orion_spi_reset(struct orion_spi *orion_spi) |
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{ |
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/* Verify that the CS is deasserted */ |
|
orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
|
|
|
/* Don't deassert CS between the direct mapped SPI transfers */ |
|
writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct orion_spi_dev orion_spi_dev_data = { |
|
.typ = ORION_SPI, |
|
.min_divisor = 4, |
|
.max_divisor = 30, |
|
.prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, |
|
}; |
|
|
|
static const struct orion_spi_dev armada_370_spi_dev_data = { |
|
.typ = ARMADA_SPI, |
|
.min_divisor = 4, |
|
.max_divisor = 1920, |
|
.max_hz = 50000000, |
|
.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
|
}; |
|
|
|
static const struct orion_spi_dev armada_xp_spi_dev_data = { |
|
.typ = ARMADA_SPI, |
|
.max_hz = 50000000, |
|
.max_divisor = 1920, |
|
.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
|
}; |
|
|
|
static const struct orion_spi_dev armada_375_spi_dev_data = { |
|
.typ = ARMADA_SPI, |
|
.min_divisor = 15, |
|
.max_divisor = 1920, |
|
.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
|
}; |
|
|
|
static const struct orion_spi_dev armada_380_spi_dev_data = { |
|
.typ = ARMADA_SPI, |
|
.max_hz = 50000000, |
|
.max_divisor = 1920, |
|
.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
|
.is_errata_50mhz_ac = true, |
|
}; |
|
|
|
static const struct of_device_id orion_spi_of_match_table[] = { |
|
{ |
|
.compatible = "marvell,orion-spi", |
|
.data = &orion_spi_dev_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-370-spi", |
|
.data = &armada_370_spi_dev_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-375-spi", |
|
.data = &armada_375_spi_dev_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-380-spi", |
|
.data = &armada_380_spi_dev_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-390-spi", |
|
.data = &armada_xp_spi_dev_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-xp-spi", |
|
.data = &armada_xp_spi_dev_data, |
|
}, |
|
|
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); |
|
|
|
static int orion_spi_probe(struct platform_device *pdev) |
|
{ |
|
const struct of_device_id *of_id; |
|
const struct orion_spi_dev *devdata; |
|
struct spi_master *master; |
|
struct orion_spi *spi; |
|
struct resource *r; |
|
unsigned long tclk_hz; |
|
int status = 0; |
|
struct device_node *np; |
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*spi)); |
|
if (master == NULL) { |
|
dev_dbg(&pdev->dev, "master allocation failed\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
if (pdev->id != -1) |
|
master->bus_num = pdev->id; |
|
if (pdev->dev.of_node) { |
|
u32 cell_index; |
|
|
|
if (!of_property_read_u32(pdev->dev.of_node, "cell-index", |
|
&cell_index)) |
|
master->bus_num = cell_index; |
|
} |
|
|
|
/* we support all 4 SPI modes and LSB first option */ |
|
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD; |
|
master->set_cs = orion_spi_set_cs; |
|
master->transfer_one = orion_spi_transfer_one; |
|
master->num_chipselect = ORION_NUM_CHIPSELECTS; |
|
master->setup = orion_spi_setup; |
|
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
|
master->auto_runtime_pm = true; |
|
master->use_gpio_descriptors = true; |
|
master->flags = SPI_MASTER_GPIO_SS; |
|
|
|
platform_set_drvdata(pdev, master); |
|
|
|
spi = spi_master_get_devdata(master); |
|
spi->master = master; |
|
spi->dev = &pdev->dev; |
|
|
|
of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); |
|
devdata = (of_id) ? of_id->data : &orion_spi_dev_data; |
|
spi->devdata = devdata; |
|
|
|
spi->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(spi->clk)) { |
|
status = PTR_ERR(spi->clk); |
|
goto out; |
|
} |
|
|
|
status = clk_prepare_enable(spi->clk); |
|
if (status) |
|
goto out; |
|
|
|
/* The following clock is only used by some SoCs */ |
|
spi->axi_clk = devm_clk_get(&pdev->dev, "axi"); |
|
if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) { |
|
status = -EPROBE_DEFER; |
|
goto out_rel_clk; |
|
} |
|
if (!IS_ERR(spi->axi_clk)) |
|
clk_prepare_enable(spi->axi_clk); |
|
|
|
tclk_hz = clk_get_rate(spi->clk); |
|
|
|
/* |
|
* With old device tree, armada-370-spi could be used with |
|
* Armada XP, however for this SoC the maximum frequency is |
|
* 50MHz instead of tclk/4. On Armada 370, tclk cannot be |
|
* higher than 200MHz. So, in order to be able to handle both |
|
* SoCs, we can take the minimum of 50MHz and tclk/4. |
|
*/ |
|
if (of_device_is_compatible(pdev->dev.of_node, |
|
"marvell,armada-370-spi")) |
|
master->max_speed_hz = min(devdata->max_hz, |
|
DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); |
|
else if (devdata->min_divisor) |
|
master->max_speed_hz = |
|
DIV_ROUND_UP(tclk_hz, devdata->min_divisor); |
|
else |
|
master->max_speed_hz = devdata->max_hz; |
|
master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); |
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
spi->base = devm_ioremap_resource(&pdev->dev, r); |
|
if (IS_ERR(spi->base)) { |
|
status = PTR_ERR(spi->base); |
|
goto out_rel_axi_clk; |
|
} |
|
|
|
for_each_available_child_of_node(pdev->dev.of_node, np) { |
|
struct orion_direct_acc *dir_acc; |
|
u32 cs; |
|
|
|
/* Get chip-select number from the "reg" property */ |
|
status = of_property_read_u32(np, "reg", &cs); |
|
if (status) { |
|
dev_err(&pdev->dev, |
|
"%pOF has no valid 'reg' property (%d)\n", |
|
np, status); |
|
continue; |
|
} |
|
|
|
/* |
|
* Check if an address is configured for this SPI device. If |
|
* not, the MBus mapping via the 'ranges' property in the 'soc' |
|
* node is not configured and this device should not use the |
|
* direct mode. In this case, just continue with the next |
|
* device. |
|
*/ |
|
status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); |
|
if (status) |
|
continue; |
|
|
|
/* |
|
* Only map one page for direct access. This is enough for the |
|
* simple TX transfer which only writes to the first word. |
|
* This needs to get extended for the direct SPI NOR / SPI NAND |
|
* support, once this gets implemented. |
|
*/ |
|
dir_acc = &spi->child[cs].direct_access; |
|
dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); |
|
if (!dir_acc->vaddr) { |
|
status = -ENOMEM; |
|
goto out_rel_axi_clk; |
|
} |
|
dir_acc->size = PAGE_SIZE; |
|
|
|
dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); |
|
} |
|
|
|
pm_runtime_set_active(&pdev->dev); |
|
pm_runtime_use_autosuspend(&pdev->dev); |
|
pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); |
|
pm_runtime_enable(&pdev->dev); |
|
|
|
status = orion_spi_reset(spi); |
|
if (status < 0) |
|
goto out_rel_pm; |
|
|
|
master->dev.of_node = pdev->dev.of_node; |
|
status = spi_register_master(master); |
|
if (status < 0) |
|
goto out_rel_pm; |
|
|
|
return status; |
|
|
|
out_rel_pm: |
|
pm_runtime_disable(&pdev->dev); |
|
out_rel_axi_clk: |
|
clk_disable_unprepare(spi->axi_clk); |
|
out_rel_clk: |
|
clk_disable_unprepare(spi->clk); |
|
out: |
|
spi_master_put(master); |
|
return status; |
|
} |
|
|
|
|
|
static int orion_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master = platform_get_drvdata(pdev); |
|
struct orion_spi *spi = spi_master_get_devdata(master); |
|
|
|
pm_runtime_get_sync(&pdev->dev); |
|
clk_disable_unprepare(spi->axi_clk); |
|
clk_disable_unprepare(spi->clk); |
|
|
|
spi_unregister_master(master); |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME); |
|
|
|
#ifdef CONFIG_PM |
|
static int orion_spi_runtime_suspend(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct orion_spi *spi = spi_master_get_devdata(master); |
|
|
|
clk_disable_unprepare(spi->axi_clk); |
|
clk_disable_unprepare(spi->clk); |
|
return 0; |
|
} |
|
|
|
static int orion_spi_runtime_resume(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct orion_spi *spi = spi_master_get_devdata(master); |
|
|
|
if (!IS_ERR(spi->axi_clk)) |
|
clk_prepare_enable(spi->axi_clk); |
|
return clk_prepare_enable(spi->clk); |
|
} |
|
#endif |
|
|
|
static const struct dev_pm_ops orion_spi_pm_ops = { |
|
SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, |
|
orion_spi_runtime_resume, |
|
NULL) |
|
}; |
|
|
|
static struct platform_driver orion_spi_driver = { |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.pm = &orion_spi_pm_ops, |
|
.of_match_table = of_match_ptr(orion_spi_of_match_table), |
|
}, |
|
.probe = orion_spi_probe, |
|
.remove = orion_spi_remove, |
|
}; |
|
|
|
module_platform_driver(orion_spi_driver); |
|
|
|
MODULE_DESCRIPTION("Orion SPI driver"); |
|
MODULE_AUTHOR("Shadi Ammouri <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|