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463 lines
10 KiB
463 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (c) 2018 Nuvoton Technology corporation. |
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#include <linux/kernel.h> |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/spi/spi.h> |
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#include <linux/reset.h> |
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#include <asm/unaligned.h> |
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#include <linux/regmap.h> |
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#include <linux/mfd/syscon.h> |
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struct npcm_pspi { |
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struct completion xfer_done; |
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struct reset_control *reset; |
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struct spi_master *master; |
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unsigned int tx_bytes; |
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unsigned int rx_bytes; |
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void __iomem *base; |
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bool is_save_param; |
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u8 bits_per_word; |
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const u8 *tx_buf; |
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struct clk *clk; |
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u32 speed_hz; |
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u8 *rx_buf; |
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u16 mode; |
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u32 id; |
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}; |
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#define DRIVER_NAME "npcm-pspi" |
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#define NPCM_PSPI_DATA 0x00 |
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#define NPCM_PSPI_CTL1 0x02 |
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#define NPCM_PSPI_STAT 0x04 |
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/* definitions for control and status register */ |
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#define NPCM_PSPI_CTL1_SPIEN BIT(0) |
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#define NPCM_PSPI_CTL1_MOD BIT(2) |
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#define NPCM_PSPI_CTL1_EIR BIT(5) |
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#define NPCM_PSPI_CTL1_EIW BIT(6) |
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#define NPCM_PSPI_CTL1_SCM BIT(7) |
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#define NPCM_PSPI_CTL1_SCIDL BIT(8) |
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#define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9) |
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#define NPCM_PSPI_STAT_BSY BIT(0) |
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#define NPCM_PSPI_STAT_RBF BIT(1) |
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/* general definitions */ |
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#define NPCM_PSPI_TIMEOUT_MS 2000 |
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#define NPCM_PSPI_MAX_CLK_DIVIDER 256 |
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#define NPCM_PSPI_MIN_CLK_DIVIDER 4 |
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#define NPCM_PSPI_DEFAULT_CLK 25000000 |
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static inline unsigned int bytes_per_word(unsigned int bits) |
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{ |
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return bits <= 8 ? 1 : 2; |
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} |
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static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask) |
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{ |
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u16 val; |
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val = ioread16(priv->base + NPCM_PSPI_CTL1); |
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val |= mask; |
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iowrite16(val, priv->base + NPCM_PSPI_CTL1); |
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} |
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static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask) |
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{ |
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u16 val; |
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val = ioread16(priv->base + NPCM_PSPI_CTL1); |
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val &= ~mask; |
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iowrite16(val, priv->base + NPCM_PSPI_CTL1); |
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} |
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static inline void npcm_pspi_enable(struct npcm_pspi *priv) |
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{ |
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u16 val; |
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val = ioread16(priv->base + NPCM_PSPI_CTL1); |
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val |= NPCM_PSPI_CTL1_SPIEN; |
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iowrite16(val, priv->base + NPCM_PSPI_CTL1); |
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} |
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static inline void npcm_pspi_disable(struct npcm_pspi *priv) |
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{ |
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u16 val; |
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val = ioread16(priv->base + NPCM_PSPI_CTL1); |
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val &= ~NPCM_PSPI_CTL1_SPIEN; |
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iowrite16(val, priv->base + NPCM_PSPI_CTL1); |
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} |
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static void npcm_pspi_set_mode(struct spi_device *spi) |
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{ |
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struct npcm_pspi *priv = spi_master_get_devdata(spi->master); |
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u16 regtemp; |
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u16 mode_val; |
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switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { |
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case SPI_MODE_0: |
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mode_val = 0; |
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break; |
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case SPI_MODE_1: |
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mode_val = NPCM_PSPI_CTL1_SCIDL; |
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break; |
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case SPI_MODE_2: |
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mode_val = NPCM_PSPI_CTL1_SCM; |
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break; |
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case SPI_MODE_3: |
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mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM; |
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break; |
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} |
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regtemp = ioread16(priv->base + NPCM_PSPI_CTL1); |
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regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL); |
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iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1); |
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} |
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static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size) |
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{ |
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u16 regtemp; |
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regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); |
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switch (size) { |
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case 8: |
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regtemp &= ~NPCM_PSPI_CTL1_MOD; |
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break; |
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case 16: |
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regtemp |= NPCM_PSPI_CTL1_MOD; |
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break; |
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} |
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iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base); |
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} |
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static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed) |
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{ |
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u32 ckdiv; |
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u16 regtemp; |
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/* the supported rates are numbers from 4 to 256. */ |
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ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1; |
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regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); |
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regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0; |
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iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base); |
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} |
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static void npcm_pspi_setup_transfer(struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct npcm_pspi *priv = spi_master_get_devdata(spi->master); |
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priv->tx_buf = t->tx_buf; |
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priv->rx_buf = t->rx_buf; |
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priv->tx_bytes = t->len; |
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priv->rx_bytes = t->len; |
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if (!priv->is_save_param || priv->mode != spi->mode) { |
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npcm_pspi_set_mode(spi); |
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priv->mode = spi->mode; |
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} |
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/* |
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* If transfer is even length, and 8 bits per word transfer, |
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* then implement 16 bits-per-word transfer. |
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*/ |
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if (priv->bits_per_word == 8 && !(t->len & 0x1)) |
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t->bits_per_word = 16; |
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if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) { |
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npcm_pspi_set_transfer_size(priv, t->bits_per_word); |
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priv->bits_per_word = t->bits_per_word; |
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} |
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if (!priv->is_save_param || priv->speed_hz != t->speed_hz) { |
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npcm_pspi_set_baudrate(priv, t->speed_hz); |
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priv->speed_hz = t->speed_hz; |
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} |
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if (!priv->is_save_param) |
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priv->is_save_param = true; |
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} |
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static void npcm_pspi_send(struct npcm_pspi *priv) |
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{ |
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int wsize; |
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u16 val; |
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wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes); |
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priv->tx_bytes -= wsize; |
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if (!priv->tx_buf) |
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return; |
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switch (wsize) { |
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case 1: |
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val = *priv->tx_buf++; |
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iowrite8(val, NPCM_PSPI_DATA + priv->base); |
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break; |
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case 2: |
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val = *priv->tx_buf++; |
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val = *priv->tx_buf++ | (val << 8); |
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iowrite16(val, NPCM_PSPI_DATA + priv->base); |
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break; |
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default: |
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WARN_ON_ONCE(1); |
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return; |
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} |
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} |
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static void npcm_pspi_recv(struct npcm_pspi *priv) |
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{ |
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int rsize; |
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u16 val; |
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rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes); |
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priv->rx_bytes -= rsize; |
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if (!priv->rx_buf) |
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return; |
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switch (rsize) { |
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case 1: |
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*priv->rx_buf++ = ioread8(priv->base + NPCM_PSPI_DATA); |
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break; |
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case 2: |
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val = ioread16(priv->base + NPCM_PSPI_DATA); |
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*priv->rx_buf++ = (val >> 8); |
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*priv->rx_buf++ = val & 0xff; |
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break; |
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default: |
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WARN_ON_ONCE(1); |
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return; |
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} |
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} |
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static int npcm_pspi_transfer_one(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct npcm_pspi *priv = spi_master_get_devdata(master); |
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int status; |
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npcm_pspi_setup_transfer(spi, t); |
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reinit_completion(&priv->xfer_done); |
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npcm_pspi_enable(priv); |
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status = wait_for_completion_timeout(&priv->xfer_done, |
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msecs_to_jiffies |
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(NPCM_PSPI_TIMEOUT_MS)); |
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if (status == 0) { |
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npcm_pspi_disable(priv); |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master) |
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{ |
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struct npcm_pspi *priv = spi_master_get_devdata(master); |
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npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); |
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return 0; |
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} |
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static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master) |
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{ |
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struct npcm_pspi *priv = spi_master_get_devdata(master); |
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npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW); |
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return 0; |
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} |
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static void npcm_pspi_reset_hw(struct npcm_pspi *priv) |
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{ |
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reset_control_assert(priv->reset); |
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udelay(5); |
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reset_control_deassert(priv->reset); |
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} |
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static irqreturn_t npcm_pspi_handler(int irq, void *dev_id) |
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{ |
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struct npcm_pspi *priv = dev_id; |
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u8 stat; |
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stat = ioread8(priv->base + NPCM_PSPI_STAT); |
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if (!priv->tx_buf && !priv->rx_buf) |
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return IRQ_NONE; |
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if (priv->tx_buf) { |
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if (stat & NPCM_PSPI_STAT_RBF) { |
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ioread8(NPCM_PSPI_DATA + priv->base); |
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if (priv->tx_bytes == 0) { |
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npcm_pspi_disable(priv); |
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complete(&priv->xfer_done); |
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return IRQ_HANDLED; |
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} |
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} |
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if ((stat & NPCM_PSPI_STAT_BSY) == 0) |
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if (priv->tx_bytes) |
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npcm_pspi_send(priv); |
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} |
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if (priv->rx_buf) { |
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if (stat & NPCM_PSPI_STAT_RBF) { |
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if (!priv->rx_bytes) |
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return IRQ_NONE; |
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npcm_pspi_recv(priv); |
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if (!priv->rx_bytes) { |
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npcm_pspi_disable(priv); |
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complete(&priv->xfer_done); |
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return IRQ_HANDLED; |
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} |
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} |
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if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf) |
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iowrite8(0x0, NPCM_PSPI_DATA + priv->base); |
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} |
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return IRQ_HANDLED; |
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} |
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static int npcm_pspi_probe(struct platform_device *pdev) |
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{ |
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struct npcm_pspi *priv; |
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struct spi_master *master; |
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unsigned long clk_hz; |
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int irq; |
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int ret; |
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master = spi_alloc_master(&pdev->dev, sizeof(*priv)); |
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if (!master) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, master); |
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priv = spi_master_get_devdata(master); |
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priv->master = master; |
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priv->is_save_param = false; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) { |
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ret = PTR_ERR(priv->base); |
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goto out_master_put; |
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} |
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priv->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(priv->clk)) { |
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dev_err(&pdev->dev, "failed to get clock\n"); |
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ret = PTR_ERR(priv->clk); |
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goto out_master_put; |
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} |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) |
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goto out_master_put; |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) { |
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ret = irq; |
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goto out_disable_clk; |
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} |
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priv->reset = devm_reset_control_get(&pdev->dev, NULL); |
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if (IS_ERR(priv->reset)) { |
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ret = PTR_ERR(priv->reset); |
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goto out_disable_clk; |
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} |
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/* reset SPI-HW block */ |
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npcm_pspi_reset_hw(priv); |
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ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0, |
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"npcm-pspi", priv); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to request IRQ\n"); |
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goto out_disable_clk; |
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} |
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init_completion(&priv->xfer_done); |
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clk_hz = clk_get_rate(priv->clk); |
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master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER); |
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master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER); |
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master->mode_bits = SPI_CPHA | SPI_CPOL; |
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master->dev.of_node = pdev->dev.of_node; |
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master->bus_num = -1; |
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master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
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master->transfer_one = npcm_pspi_transfer_one; |
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master->prepare_transfer_hardware = |
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npcm_pspi_prepare_transfer_hardware; |
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master->unprepare_transfer_hardware = |
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npcm_pspi_unprepare_transfer_hardware; |
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master->use_gpio_descriptors = true; |
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/* set to default clock rate */ |
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npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK); |
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ret = devm_spi_register_master(&pdev->dev, master); |
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if (ret) |
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goto out_disable_clk; |
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pr_info("NPCM Peripheral SPI %d probed\n", master->bus_num); |
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return 0; |
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out_disable_clk: |
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clk_disable_unprepare(priv->clk); |
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out_master_put: |
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spi_master_put(master); |
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return ret; |
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} |
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static int npcm_pspi_remove(struct platform_device *pdev) |
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{ |
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struct spi_master *master = platform_get_drvdata(pdev); |
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struct npcm_pspi *priv = spi_master_get_devdata(master); |
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npcm_pspi_reset_hw(priv); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static const struct of_device_id npcm_pspi_match[] = { |
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{ .compatible = "nuvoton,npcm750-pspi", .data = NULL }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, npcm_pspi_match); |
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static struct platform_driver npcm_pspi_driver = { |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = npcm_pspi_match, |
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}, |
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.probe = npcm_pspi_probe, |
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.remove = npcm_pspi_remove, |
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}; |
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module_platform_driver(npcm_pspi_driver); |
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MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver"); |
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MODULE_AUTHOR("Tomer Maimon <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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