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502 lines
13 KiB
502 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* MPC52xx PSC in SPI mode driver. |
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* |
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* Maintainer: Dragos Carp |
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* |
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* Copyright (C) 2006 TOPTICA Photonics AG. |
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*/ |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/errno.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/workqueue.h> |
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#include <linux/completion.h> |
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#include <linux/io.h> |
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#include <linux/delay.h> |
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#include <linux/spi/spi.h> |
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#include <linux/fsl_devices.h> |
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#include <linux/slab.h> |
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#include <asm/mpc52xx.h> |
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#include <asm/mpc52xx_psc.h> |
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#define MCLK 20000000 /* PSC port MClk in hz */ |
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struct mpc52xx_psc_spi { |
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/* fsl_spi_platform data */ |
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void (*cs_control)(struct spi_device *spi, bool on); |
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u32 sysclk; |
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/* driver internal data */ |
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struct mpc52xx_psc __iomem *psc; |
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struct mpc52xx_psc_fifo __iomem *fifo; |
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unsigned int irq; |
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u8 bits_per_word; |
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u8 busy; |
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struct work_struct work; |
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struct list_head queue; |
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spinlock_t lock; |
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struct completion done; |
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}; |
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/* controller state */ |
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struct mpc52xx_psc_spi_cs { |
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int bits_per_word; |
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int speed_hz; |
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}; |
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/* set clock freq, clock ramp, bits per work |
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* if t is NULL then reset the values to the default values |
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*/ |
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static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct mpc52xx_psc_spi_cs *cs = spi->controller_state; |
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cs->speed_hz = (t && t->speed_hz) |
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? t->speed_hz : spi->max_speed_hz; |
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cs->bits_per_word = (t && t->bits_per_word) |
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? t->bits_per_word : spi->bits_per_word; |
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cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; |
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return 0; |
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} |
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static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) |
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{ |
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struct mpc52xx_psc_spi_cs *cs = spi->controller_state; |
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); |
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struct mpc52xx_psc __iomem *psc = mps->psc; |
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u32 sicr; |
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u16 ccr; |
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sicr = in_be32(&psc->sicr); |
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/* Set clock phase and polarity */ |
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if (spi->mode & SPI_CPHA) |
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sicr |= 0x00001000; |
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else |
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sicr &= ~0x00001000; |
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if (spi->mode & SPI_CPOL) |
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sicr |= 0x00002000; |
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else |
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sicr &= ~0x00002000; |
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if (spi->mode & SPI_LSB_FIRST) |
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sicr |= 0x10000000; |
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else |
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sicr &= ~0x10000000; |
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out_be32(&psc->sicr, sicr); |
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/* Set clock frequency and bits per word |
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* Because psc->ccr is defined as 16bit register instead of 32bit |
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* just set the lower byte of BitClkDiv |
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*/ |
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ccr = in_be16((u16 __iomem *)&psc->ccr); |
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ccr &= 0xFF00; |
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if (cs->speed_hz) |
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ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; |
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else /* by default SPI Clk 1MHz */ |
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ccr |= (MCLK / 1000000 - 1) & 0xFF; |
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out_be16((u16 __iomem *)&psc->ccr, ccr); |
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mps->bits_per_word = cs->bits_per_word; |
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if (mps->cs_control) |
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mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0); |
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} |
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static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi) |
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{ |
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); |
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if (mps->cs_control) |
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mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1); |
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} |
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#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1) |
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/* wake up when 80% fifo full */ |
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#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100) |
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static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); |
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struct mpc52xx_psc __iomem *psc = mps->psc; |
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struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; |
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unsigned rb = 0; /* number of bytes receieved */ |
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unsigned sb = 0; /* number of bytes sent */ |
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unsigned char *rx_buf = (unsigned char *)t->rx_buf; |
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unsigned char *tx_buf = (unsigned char *)t->tx_buf; |
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unsigned rfalarm; |
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unsigned send_at_once = MPC52xx_PSC_BUFSIZE; |
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unsigned recv_at_once; |
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int last_block = 0; |
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if (!t->tx_buf && !t->rx_buf && t->len) |
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return -EINVAL; |
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/* enable transmiter/receiver */ |
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out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); |
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while (rb < t->len) { |
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if (t->len - rb > MPC52xx_PSC_BUFSIZE) { |
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rfalarm = MPC52xx_PSC_RFALARM; |
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last_block = 0; |
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} else { |
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send_at_once = t->len - sb; |
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rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb); |
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last_block = 1; |
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} |
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dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once); |
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for (; send_at_once; sb++, send_at_once--) { |
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/* set EOF flag before the last word is sent */ |
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if (send_at_once == 1 && last_block) |
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out_8(&psc->ircr2, 0x01); |
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if (tx_buf) |
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out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]); |
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else |
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out_8(&psc->mpc52xx_psc_buffer_8, 0); |
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} |
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/* enable interrupts and wait for wake up |
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* if just one byte is expected the Rx FIFO genererates no |
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* FFULL interrupt, so activate the RxRDY interrupt |
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*/ |
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out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
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if (t->len - rb == 1) { |
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out_8(&psc->mode, 0); |
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} else { |
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out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); |
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out_be16(&fifo->rfalarm, rfalarm); |
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} |
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out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY); |
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wait_for_completion(&mps->done); |
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recv_at_once = in_be16(&fifo->rfnum); |
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dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once); |
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send_at_once = recv_at_once; |
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if (rx_buf) { |
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for (; recv_at_once; rb++, recv_at_once--) |
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rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8); |
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} else { |
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for (; recv_at_once; rb++, recv_at_once--) |
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in_8(&psc->mpc52xx_psc_buffer_8); |
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} |
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} |
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/* disable transmiter/receiver */ |
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out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); |
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return 0; |
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} |
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static void mpc52xx_psc_spi_work(struct work_struct *work) |
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{ |
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struct mpc52xx_psc_spi *mps = |
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container_of(work, struct mpc52xx_psc_spi, work); |
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spin_lock_irq(&mps->lock); |
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mps->busy = 1; |
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while (!list_empty(&mps->queue)) { |
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struct spi_message *m; |
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struct spi_device *spi; |
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struct spi_transfer *t = NULL; |
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unsigned cs_change; |
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int status; |
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m = container_of(mps->queue.next, struct spi_message, queue); |
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list_del_init(&m->queue); |
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spin_unlock_irq(&mps->lock); |
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spi = m->spi; |
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cs_change = 1; |
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status = 0; |
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list_for_each_entry (t, &m->transfers, transfer_list) { |
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if (t->bits_per_word || t->speed_hz) { |
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status = mpc52xx_psc_spi_transfer_setup(spi, t); |
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if (status < 0) |
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break; |
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} |
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if (cs_change) |
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mpc52xx_psc_spi_activate_cs(spi); |
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cs_change = t->cs_change; |
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status = mpc52xx_psc_spi_transfer_rxtx(spi, t); |
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if (status) |
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break; |
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m->actual_length += t->len; |
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spi_transfer_delay_exec(t); |
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if (cs_change) |
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mpc52xx_psc_spi_deactivate_cs(spi); |
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} |
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m->status = status; |
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if (m->complete) |
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m->complete(m->context); |
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if (status || !cs_change) |
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mpc52xx_psc_spi_deactivate_cs(spi); |
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mpc52xx_psc_spi_transfer_setup(spi, NULL); |
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spin_lock_irq(&mps->lock); |
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} |
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mps->busy = 0; |
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spin_unlock_irq(&mps->lock); |
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} |
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static int mpc52xx_psc_spi_setup(struct spi_device *spi) |
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{ |
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); |
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struct mpc52xx_psc_spi_cs *cs = spi->controller_state; |
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unsigned long flags; |
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if (spi->bits_per_word%8) |
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return -EINVAL; |
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if (!cs) { |
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cs = kzalloc(sizeof *cs, GFP_KERNEL); |
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if (!cs) |
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return -ENOMEM; |
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spi->controller_state = cs; |
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} |
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cs->bits_per_word = spi->bits_per_word; |
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cs->speed_hz = spi->max_speed_hz; |
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spin_lock_irqsave(&mps->lock, flags); |
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if (!mps->busy) |
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mpc52xx_psc_spi_deactivate_cs(spi); |
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spin_unlock_irqrestore(&mps->lock, flags); |
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return 0; |
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} |
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static int mpc52xx_psc_spi_transfer(struct spi_device *spi, |
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struct spi_message *m) |
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{ |
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); |
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unsigned long flags; |
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m->actual_length = 0; |
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m->status = -EINPROGRESS; |
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spin_lock_irqsave(&mps->lock, flags); |
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list_add_tail(&m->queue, &mps->queue); |
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schedule_work(&mps->work); |
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spin_unlock_irqrestore(&mps->lock, flags); |
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return 0; |
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} |
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static void mpc52xx_psc_spi_cleanup(struct spi_device *spi) |
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{ |
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kfree(spi->controller_state); |
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} |
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static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) |
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{ |
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struct mpc52xx_psc __iomem *psc = mps->psc; |
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struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; |
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u32 mclken_div; |
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int ret; |
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/* default sysclk is 512MHz */ |
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mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; |
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ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div); |
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if (ret) |
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return ret; |
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/* Reset the PSC into a known state */ |
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out_8(&psc->command, MPC52xx_PSC_RST_RX); |
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out_8(&psc->command, MPC52xx_PSC_RST_TX); |
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out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); |
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/* Disable interrupts, interrupts are based on alarm level */ |
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out_be16(&psc->mpc52xx_psc_imr, 0); |
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out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
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out_8(&fifo->rfcntl, 0); |
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out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); |
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/* Configure 8bit codec mode as a SPI master and use EOF flags */ |
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/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ |
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out_be32(&psc->sicr, 0x0180C800); |
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out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */ |
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/* Set 2ms DTL delay */ |
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out_8(&psc->ctur, 0x00); |
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out_8(&psc->ctlr, 0x84); |
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mps->bits_per_word = 8; |
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return 0; |
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} |
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static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id) |
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{ |
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struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id; |
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struct mpc52xx_psc __iomem *psc = mps->psc; |
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/* disable interrupt and wake up the work queue */ |
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if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) { |
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out_be16(&psc->mpc52xx_psc_imr, 0); |
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complete(&mps->done); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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/* bus_num is used only for the case dev->platform_data == NULL */ |
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static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, |
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u32 size, unsigned int irq, s16 bus_num) |
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{ |
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
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struct mpc52xx_psc_spi *mps; |
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struct spi_master *master; |
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int ret; |
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master = spi_alloc_master(dev, sizeof *mps); |
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if (master == NULL) |
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return -ENOMEM; |
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dev_set_drvdata(dev, master); |
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mps = spi_master_get_devdata(master); |
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/* the spi->mode bits understood by this driver: */ |
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
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mps->irq = irq; |
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if (pdata == NULL) { |
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dev_warn(dev, |
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"probe called without platform data, no cs_control function will be called\n"); |
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mps->cs_control = NULL; |
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mps->sysclk = 0; |
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master->bus_num = bus_num; |
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master->num_chipselect = 255; |
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} else { |
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mps->cs_control = pdata->cs_control; |
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mps->sysclk = pdata->sysclk; |
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master->bus_num = pdata->bus_num; |
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master->num_chipselect = pdata->max_chipselect; |
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} |
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master->setup = mpc52xx_psc_spi_setup; |
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master->transfer = mpc52xx_psc_spi_transfer; |
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master->cleanup = mpc52xx_psc_spi_cleanup; |
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master->dev.of_node = dev->of_node; |
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mps->psc = ioremap(regaddr, size); |
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if (!mps->psc) { |
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dev_err(dev, "could not ioremap I/O port range\n"); |
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ret = -EFAULT; |
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goto free_master; |
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} |
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/* On the 5200, fifo regs are immediately ajacent to the psc regs */ |
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mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc); |
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ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi", |
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mps); |
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if (ret) |
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goto free_master; |
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ret = mpc52xx_psc_spi_port_config(master->bus_num, mps); |
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if (ret < 0) { |
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dev_err(dev, "can't configure PSC! Is it capable of SPI?\n"); |
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goto free_irq; |
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} |
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spin_lock_init(&mps->lock); |
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init_completion(&mps->done); |
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INIT_WORK(&mps->work, mpc52xx_psc_spi_work); |
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INIT_LIST_HEAD(&mps->queue); |
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ret = spi_register_master(master); |
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if (ret < 0) |
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goto free_irq; |
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return ret; |
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free_irq: |
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free_irq(mps->irq, mps); |
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free_master: |
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if (mps->psc) |
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iounmap(mps->psc); |
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spi_master_put(master); |
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return ret; |
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} |
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static int mpc52xx_psc_spi_of_probe(struct platform_device *op) |
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{ |
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const u32 *regaddr_p; |
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u64 regaddr64, size64; |
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s16 id = -1; |
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regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); |
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if (!regaddr_p) { |
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dev_err(&op->dev, "Invalid PSC address\n"); |
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return -EINVAL; |
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} |
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regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); |
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/* get PSC id (1..6, used by port_config) */ |
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if (op->dev.platform_data == NULL) { |
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const u32 *psc_nump; |
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psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL); |
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if (!psc_nump || *psc_nump > 5) { |
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dev_err(&op->dev, "Invalid cell-index property\n"); |
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return -EINVAL; |
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} |
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id = *psc_nump + 1; |
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} |
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return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64, |
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irq_of_parse_and_map(op->dev.of_node, 0), id); |
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} |
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static int mpc52xx_psc_spi_of_remove(struct platform_device *op) |
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{ |
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struct spi_master *master = spi_master_get(platform_get_drvdata(op)); |
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); |
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flush_work(&mps->work); |
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spi_unregister_master(master); |
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free_irq(mps->irq, mps); |
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if (mps->psc) |
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iounmap(mps->psc); |
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spi_master_put(master); |
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return 0; |
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} |
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static const struct of_device_id mpc52xx_psc_spi_of_match[] = { |
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{ .compatible = "fsl,mpc5200-psc-spi", }, |
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{ .compatible = "mpc5200-psc-spi", }, /* old */ |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match); |
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static struct platform_driver mpc52xx_psc_spi_of_driver = { |
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.probe = mpc52xx_psc_spi_of_probe, |
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.remove = mpc52xx_psc_spi_of_remove, |
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.driver = { |
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.name = "mpc52xx-psc-spi", |
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.of_match_table = mpc52xx_psc_spi_of_match, |
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}, |
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}; |
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module_platform_driver(mpc52xx_psc_spi_of_driver); |
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MODULE_AUTHOR("Dragos Carp"); |
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MODULE_DESCRIPTION("MPC52xx PSC SPI Driver"); |
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MODULE_LICENSE("GPL");
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