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26 KiB
1010 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Freescale QuadSPI driver. |
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* |
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* Copyright (C) 2013 Freescale Semiconductor, Inc. |
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* Copyright (C) 2018 Bootlin |
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* Copyright (C) 2018 exceet electronics GmbH |
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* Copyright (C) 2018 Kontron Electronics GmbH |
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* |
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* Transition to SPI MEM interface: |
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* Authors: |
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* Boris Brezillon <[email protected]> |
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* Frieder Schrempf <[email protected]> |
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* Yogesh Gaur <[email protected]> |
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* Suresh Gupta <[email protected]> |
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* |
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* Based on the original fsl-quadspi.c SPI NOR driver: |
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* Author: Freescale Semiconductor, Inc. |
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* |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/errno.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/jiffies.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_qos.h> |
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#include <linux/sizes.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/spi-mem.h> |
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/* |
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* The driver only uses one single LUT entry, that is updated on |
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* each call of exec_op(). Index 0 is preset at boot with a basic |
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* read operation, so let's use the last entry (15). |
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*/ |
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#define SEQID_LUT 15 |
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/* Registers used by the driver */ |
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#define QUADSPI_MCR 0x00 |
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#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) |
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#define QUADSPI_MCR_MDIS_MASK BIT(14) |
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#define QUADSPI_MCR_CLR_TXF_MASK BIT(11) |
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#define QUADSPI_MCR_CLR_RXF_MASK BIT(10) |
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#define QUADSPI_MCR_DDR_EN_MASK BIT(7) |
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#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) |
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#define QUADSPI_MCR_SWRSTHD_MASK BIT(1) |
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#define QUADSPI_MCR_SWRSTSD_MASK BIT(0) |
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#define QUADSPI_IPCR 0x08 |
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#define QUADSPI_IPCR_SEQID(x) ((x) << 24) |
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#define QUADSPI_FLSHCR 0x0c |
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#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) |
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#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) |
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#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) |
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#define QUADSPI_BUF0CR 0x10 |
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#define QUADSPI_BUF1CR 0x14 |
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#define QUADSPI_BUF2CR 0x18 |
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#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe |
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#define QUADSPI_BUF3CR 0x1c |
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#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) |
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#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) |
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#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) |
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#define QUADSPI_BFGENCR 0x20 |
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#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) |
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#define QUADSPI_BUF0IND 0x30 |
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#define QUADSPI_BUF1IND 0x34 |
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#define QUADSPI_BUF2IND 0x38 |
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#define QUADSPI_SFAR 0x100 |
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#define QUADSPI_SMPR 0x108 |
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#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16) |
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#define QUADSPI_SMPR_FSDLY_MASK BIT(6) |
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#define QUADSPI_SMPR_FSPHS_MASK BIT(5) |
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#define QUADSPI_SMPR_HSENA_MASK BIT(0) |
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#define QUADSPI_RBCT 0x110 |
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#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0) |
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#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) |
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#define QUADSPI_TBDR 0x154 |
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#define QUADSPI_SR 0x15c |
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#define QUADSPI_SR_IP_ACC_MASK BIT(1) |
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#define QUADSPI_SR_AHB_ACC_MASK BIT(2) |
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#define QUADSPI_FR 0x160 |
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#define QUADSPI_FR_TFF_MASK BIT(0) |
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#define QUADSPI_RSER 0x164 |
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#define QUADSPI_RSER_TFIE BIT(0) |
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#define QUADSPI_SPTRCLR 0x16c |
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#define QUADSPI_SPTRCLR_IPPTRC BIT(8) |
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#define QUADSPI_SPTRCLR_BFPTRC BIT(0) |
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#define QUADSPI_SFA1AD 0x180 |
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#define QUADSPI_SFA2AD 0x184 |
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#define QUADSPI_SFB1AD 0x188 |
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#define QUADSPI_SFB2AD 0x18c |
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#define QUADSPI_RBDR(x) (0x200 + ((x) * 4)) |
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#define QUADSPI_LUTKEY 0x300 |
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#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0 |
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#define QUADSPI_LCKCR 0x304 |
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#define QUADSPI_LCKER_LOCK BIT(0) |
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#define QUADSPI_LCKER_UNLOCK BIT(1) |
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#define QUADSPI_LUT_BASE 0x310 |
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#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) |
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#define QUADSPI_LUT_REG(idx) \ |
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(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4) |
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/* Instruction set for the LUT register */ |
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#define LUT_STOP 0 |
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#define LUT_CMD 1 |
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#define LUT_ADDR 2 |
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#define LUT_DUMMY 3 |
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#define LUT_MODE 4 |
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#define LUT_MODE2 5 |
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#define LUT_MODE4 6 |
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#define LUT_FSL_READ 7 |
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#define LUT_FSL_WRITE 8 |
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#define LUT_JMP_ON_CS 9 |
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#define LUT_ADDR_DDR 10 |
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#define LUT_MODE_DDR 11 |
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#define LUT_MODE2_DDR 12 |
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#define LUT_MODE4_DDR 13 |
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#define LUT_FSL_READ_DDR 14 |
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#define LUT_FSL_WRITE_DDR 15 |
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#define LUT_DATA_LEARN 16 |
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/* |
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* The PAD definitions for LUT register. |
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* |
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* The pad stands for the number of IO lines [0:3]. |
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* For example, the quad read needs four IO lines, |
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* so you should use LUT_PAD(4). |
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*/ |
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#define LUT_PAD(x) (fls(x) - 1) |
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/* |
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* Macro for constructing the LUT entries with the following |
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* register layout: |
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* |
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* --------------------------------------------------- |
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* | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | |
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* --------------------------------------------------- |
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*/ |
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#define LUT_DEF(idx, ins, pad, opr) \ |
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((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16)) |
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/* Controller needs driver to swap endianness */ |
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#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) |
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/* Controller needs 4x internal clock */ |
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#define QUADSPI_QUIRK_4X_INT_CLK BIT(1) |
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/* |
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* TKT253890, the controller needs the driver to fill the txfifo with |
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* 16 bytes at least to trigger a data transfer, even though the extra |
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* data won't be transferred. |
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*/ |
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#define QUADSPI_QUIRK_TKT253890 BIT(2) |
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|
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/* TKT245618, the controller cannot wake up from wait mode */ |
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#define QUADSPI_QUIRK_TKT245618 BIT(3) |
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/* |
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* Controller adds QSPI_AMBA_BASE (base address of the mapped memory) |
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* internally. No need to add it when setting SFXXAD and SFAR registers |
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*/ |
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#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) |
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/* |
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* Controller uses TDH bits in register QUADSPI_FLSHCR. |
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* They need to be set in accordance with the DDR/SDR mode. |
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*/ |
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#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) |
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struct fsl_qspi_devtype_data { |
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unsigned int rxfifo; |
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unsigned int txfifo; |
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int invalid_mstrid; |
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unsigned int ahb_buf_size; |
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unsigned int quirks; |
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bool little_endian; |
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}; |
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static const struct fsl_qspi_devtype_data vybrid_data = { |
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.rxfifo = SZ_128, |
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.txfifo = SZ_64, |
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
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.ahb_buf_size = SZ_1K, |
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.quirks = QUADSPI_QUIRK_SWAP_ENDIAN, |
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.little_endian = true, |
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}; |
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static const struct fsl_qspi_devtype_data imx6sx_data = { |
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.rxfifo = SZ_128, |
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.txfifo = SZ_512, |
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
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.ahb_buf_size = SZ_1K, |
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.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, |
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.little_endian = true, |
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}; |
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static const struct fsl_qspi_devtype_data imx7d_data = { |
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.rxfifo = SZ_128, |
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.txfifo = SZ_512, |
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
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.ahb_buf_size = SZ_1K, |
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
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QUADSPI_QUIRK_USE_TDH_SETTING, |
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.little_endian = true, |
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}; |
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static const struct fsl_qspi_devtype_data imx6ul_data = { |
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.rxfifo = SZ_128, |
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.txfifo = SZ_512, |
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
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.ahb_buf_size = SZ_1K, |
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
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QUADSPI_QUIRK_USE_TDH_SETTING, |
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.little_endian = true, |
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}; |
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static const struct fsl_qspi_devtype_data ls1021a_data = { |
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.rxfifo = SZ_128, |
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.txfifo = SZ_64, |
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
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.ahb_buf_size = SZ_1K, |
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.quirks = 0, |
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.little_endian = false, |
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}; |
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static const struct fsl_qspi_devtype_data ls2080a_data = { |
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.rxfifo = SZ_128, |
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.txfifo = SZ_64, |
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.ahb_buf_size = SZ_1K, |
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.invalid_mstrid = 0x0, |
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, |
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.little_endian = true, |
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}; |
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struct fsl_qspi { |
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void __iomem *iobase; |
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void __iomem *ahb_addr; |
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u32 memmap_phy; |
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struct clk *clk, *clk_en; |
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struct device *dev; |
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struct completion c; |
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const struct fsl_qspi_devtype_data *devtype_data; |
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struct mutex lock; |
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struct pm_qos_request pm_qos_req; |
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int selected; |
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}; |
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static inline int needs_swap_endian(struct fsl_qspi *q) |
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{ |
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return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; |
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} |
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static inline int needs_4x_clock(struct fsl_qspi *q) |
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{ |
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return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; |
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} |
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static inline int needs_fill_txfifo(struct fsl_qspi *q) |
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{ |
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return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; |
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} |
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static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) |
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{ |
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return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; |
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} |
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static inline int needs_amba_base_offset(struct fsl_qspi *q) |
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{ |
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return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); |
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} |
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static inline int needs_tdh_setting(struct fsl_qspi *q) |
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{ |
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return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; |
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} |
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/* |
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* An IC bug makes it necessary to rearrange the 32-bit data. |
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* Later chips, such as IMX6SLX, have fixed this bug. |
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*/ |
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static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) |
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{ |
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return needs_swap_endian(q) ? __swab32(a) : a; |
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} |
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/* |
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* R/W functions for big- or little-endian registers: |
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* The QSPI controller's endianness is independent of |
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* the CPU core's endianness. So far, although the CPU |
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* core is little-endian the QSPI controller can use |
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* big-endian or little-endian. |
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*/ |
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static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) |
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{ |
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if (q->devtype_data->little_endian) |
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iowrite32(val, addr); |
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else |
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iowrite32be(val, addr); |
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} |
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static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) |
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{ |
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if (q->devtype_data->little_endian) |
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return ioread32(addr); |
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return ioread32be(addr); |
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} |
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static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) |
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{ |
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struct fsl_qspi *q = dev_id; |
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u32 reg; |
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/* clear interrupt */ |
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reg = qspi_readl(q, q->iobase + QUADSPI_FR); |
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qspi_writel(q, reg, q->iobase + QUADSPI_FR); |
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if (reg & QUADSPI_FR_TFF_MASK) |
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complete(&q->c); |
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dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg); |
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return IRQ_HANDLED; |
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} |
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static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) |
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{ |
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switch (width) { |
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case 1: |
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case 2: |
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case 4: |
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return 0; |
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} |
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return -ENOTSUPP; |
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} |
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static bool fsl_qspi_supports_op(struct spi_mem *mem, |
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const struct spi_mem_op *op) |
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{ |
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struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master); |
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int ret; |
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ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth); |
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if (op->addr.nbytes) |
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ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth); |
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if (op->dummy.nbytes) |
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ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth); |
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if (op->data.nbytes) |
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ret |= fsl_qspi_check_buswidth(q, op->data.buswidth); |
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if (ret) |
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return false; |
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/* |
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* The number of instructions needed for the op, needs |
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* to fit into a single LUT entry. |
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*/ |
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if (op->addr.nbytes + |
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(op->dummy.nbytes ? 1:0) + |
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(op->data.nbytes ? 1:0) > 6) |
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return false; |
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/* Max 64 dummy clock cycles supported */ |
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if (op->dummy.nbytes && |
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(op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) |
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return false; |
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/* Max data length, check controller limits and alignment */ |
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if (op->data.dir == SPI_MEM_DATA_IN && |
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(op->data.nbytes > q->devtype_data->ahb_buf_size || |
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(op->data.nbytes > q->devtype_data->rxfifo - 4 && |
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!IS_ALIGNED(op->data.nbytes, 8)))) |
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return false; |
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if (op->data.dir == SPI_MEM_DATA_OUT && |
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op->data.nbytes > q->devtype_data->txfifo) |
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return false; |
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return spi_mem_default_supports_op(mem, op); |
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} |
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static void fsl_qspi_prepare_lut(struct fsl_qspi *q, |
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const struct spi_mem_op *op) |
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{ |
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void __iomem *base = q->iobase; |
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u32 lutval[4] = {}; |
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int lutidx = 1, i; |
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lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), |
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op->cmd.opcode); |
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/* |
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* For some unknown reason, using LUT_ADDR doesn't work in some |
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* cases (at least with only one byte long addresses), so |
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* let's use LUT_MODE to write the address bytes one by one |
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*/ |
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for (i = 0; i < op->addr.nbytes; i++) { |
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u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); |
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lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE, |
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LUT_PAD(op->addr.buswidth), |
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addrbyte); |
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lutidx++; |
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} |
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if (op->dummy.nbytes) { |
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lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, |
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LUT_PAD(op->dummy.buswidth), |
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op->dummy.nbytes * 8 / |
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op->dummy.buswidth); |
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lutidx++; |
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} |
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if (op->data.nbytes) { |
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lutval[lutidx / 2] |= LUT_DEF(lutidx, |
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op->data.dir == SPI_MEM_DATA_IN ? |
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LUT_FSL_READ : LUT_FSL_WRITE, |
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LUT_PAD(op->data.buswidth), |
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0); |
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lutidx++; |
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} |
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lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); |
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|
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/* unlock LUT */ |
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qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); |
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qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); |
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/* fill LUT */ |
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for (i = 0; i < ARRAY_SIZE(lutval); i++) |
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qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); |
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|
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/* lock LUT */ |
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qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); |
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qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); |
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} |
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static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) |
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{ |
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int ret; |
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ret = clk_prepare_enable(q->clk_en); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(q->clk); |
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if (ret) { |
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clk_disable_unprepare(q->clk_en); |
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return ret; |
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} |
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if (needs_wakeup_wait_mode(q)) |
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cpu_latency_qos_add_request(&q->pm_qos_req, 0); |
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return 0; |
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} |
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static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) |
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{ |
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if (needs_wakeup_wait_mode(q)) |
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cpu_latency_qos_remove_request(&q->pm_qos_req); |
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|
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clk_disable_unprepare(q->clk); |
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clk_disable_unprepare(q->clk_en); |
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} |
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|
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/* |
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* If we have changed the content of the flash by writing or erasing, or if we |
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* read from flash with a different offset into the page buffer, we need to |
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* invalidate the AHB buffer. If we do not do so, we may read out the wrong |
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* data. The spec tells us reset the AHB domain and Serial Flash domain at |
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* the same time. |
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*/ |
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static void fsl_qspi_invalidate(struct fsl_qspi *q) |
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{ |
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u32 reg; |
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|
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reg = qspi_readl(q, q->iobase + QUADSPI_MCR); |
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reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; |
|
qspi_writel(q, reg, q->iobase + QUADSPI_MCR); |
|
|
|
/* |
|
* The minimum delay : 1 AHB + 2 SFCK clocks. |
|
* Delay 1 us is enough. |
|
*/ |
|
udelay(1); |
|
|
|
reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); |
|
qspi_writel(q, reg, q->iobase + QUADSPI_MCR); |
|
} |
|
|
|
static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi) |
|
{ |
|
unsigned long rate = spi->max_speed_hz; |
|
int ret; |
|
|
|
if (q->selected == spi->chip_select) |
|
return; |
|
|
|
if (needs_4x_clock(q)) |
|
rate *= 4; |
|
|
|
fsl_qspi_clk_disable_unprep(q); |
|
|
|
ret = clk_set_rate(q->clk, rate); |
|
if (ret) |
|
return; |
|
|
|
ret = fsl_qspi_clk_prep_enable(q); |
|
if (ret) |
|
return; |
|
|
|
q->selected = spi->chip_select; |
|
|
|
fsl_qspi_invalidate(q); |
|
} |
|
|
|
static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) |
|
{ |
|
memcpy_fromio(op->data.buf.in, |
|
q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, |
|
op->data.nbytes); |
|
} |
|
|
|
static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, |
|
const struct spi_mem_op *op) |
|
{ |
|
void __iomem *base = q->iobase; |
|
int i; |
|
u32 val; |
|
|
|
for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { |
|
memcpy(&val, op->data.buf.out + i, 4); |
|
val = fsl_qspi_endian_xchg(q, val); |
|
qspi_writel(q, val, base + QUADSPI_TBDR); |
|
} |
|
|
|
if (i < op->data.nbytes) { |
|
memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); |
|
val = fsl_qspi_endian_xchg(q, val); |
|
qspi_writel(q, val, base + QUADSPI_TBDR); |
|
} |
|
|
|
if (needs_fill_txfifo(q)) { |
|
for (i = op->data.nbytes; i < 16; i += 4) |
|
qspi_writel(q, 0, base + QUADSPI_TBDR); |
|
} |
|
} |
|
|
|
static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, |
|
const struct spi_mem_op *op) |
|
{ |
|
void __iomem *base = q->iobase; |
|
int i; |
|
u8 *buf = op->data.buf.in; |
|
u32 val; |
|
|
|
for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { |
|
val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); |
|
val = fsl_qspi_endian_xchg(q, val); |
|
memcpy(buf + i, &val, 4); |
|
} |
|
|
|
if (i < op->data.nbytes) { |
|
val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); |
|
val = fsl_qspi_endian_xchg(q, val); |
|
memcpy(buf + i, &val, op->data.nbytes - i); |
|
} |
|
} |
|
|
|
static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) |
|
{ |
|
void __iomem *base = q->iobase; |
|
int err = 0; |
|
|
|
init_completion(&q->c); |
|
|
|
/* |
|
* Always start the sequence at the same index since we update |
|
* the LUT at each exec_op() call. And also specify the DATA |
|
* length, since it's has not been specified in the LUT. |
|
*/ |
|
qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT), |
|
base + QUADSPI_IPCR); |
|
|
|
/* Wait for the interrupt. */ |
|
if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) |
|
err = -ETIMEDOUT; |
|
|
|
if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) |
|
fsl_qspi_read_rxfifo(q, op); |
|
|
|
return err; |
|
} |
|
|
|
static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, |
|
u32 mask, u32 delay_us, u32 timeout_us) |
|
{ |
|
u32 reg; |
|
|
|
if (!q->devtype_data->little_endian) |
|
mask = (u32)cpu_to_be32(mask); |
|
|
|
return readl_poll_timeout(base, reg, !(reg & mask), delay_us, |
|
timeout_us); |
|
} |
|
|
|
static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) |
|
{ |
|
struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master); |
|
void __iomem *base = q->iobase; |
|
u32 addr_offset = 0; |
|
int err = 0; |
|
int invalid_mstrid = q->devtype_data->invalid_mstrid; |
|
|
|
mutex_lock(&q->lock); |
|
|
|
/* wait for the controller being ready */ |
|
fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | |
|
QUADSPI_SR_AHB_ACC_MASK), 10, 1000); |
|
|
|
fsl_qspi_select_mem(q, mem->spi); |
|
|
|
if (needs_amba_base_offset(q)) |
|
addr_offset = q->memmap_phy; |
|
|
|
qspi_writel(q, |
|
q->selected * q->devtype_data->ahb_buf_size + addr_offset, |
|
base + QUADSPI_SFAR); |
|
|
|
qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | |
|
QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK, |
|
base + QUADSPI_MCR); |
|
|
|
qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, |
|
base + QUADSPI_SPTRCLR); |
|
|
|
qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR); |
|
qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR); |
|
qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR); |
|
|
|
fsl_qspi_prepare_lut(q, op); |
|
|
|
/* |
|
* If we have large chunks of data, we read them through the AHB bus |
|
* by accessing the mapped memory. In all other cases we use |
|
* IP commands to access the flash. |
|
*/ |
|
if (op->data.nbytes > (q->devtype_data->rxfifo - 4) && |
|
op->data.dir == SPI_MEM_DATA_IN) { |
|
fsl_qspi_read_ahb(q, op); |
|
} else { |
|
qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | |
|
QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); |
|
|
|
if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) |
|
fsl_qspi_fill_txfifo(q, op); |
|
|
|
err = fsl_qspi_do_op(q, op); |
|
} |
|
|
|
/* Invalidate the data in the AHB buffer. */ |
|
fsl_qspi_invalidate(q); |
|
|
|
mutex_unlock(&q->lock); |
|
|
|
return err; |
|
} |
|
|
|
static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) |
|
{ |
|
struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master); |
|
|
|
if (op->data.dir == SPI_MEM_DATA_OUT) { |
|
if (op->data.nbytes > q->devtype_data->txfifo) |
|
op->data.nbytes = q->devtype_data->txfifo; |
|
} else { |
|
if (op->data.nbytes > q->devtype_data->ahb_buf_size) |
|
op->data.nbytes = q->devtype_data->ahb_buf_size; |
|
else if (op->data.nbytes > (q->devtype_data->rxfifo - 4)) |
|
op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int fsl_qspi_default_setup(struct fsl_qspi *q) |
|
{ |
|
void __iomem *base = q->iobase; |
|
u32 reg, addr_offset = 0; |
|
int ret; |
|
|
|
/* disable and unprepare clock to avoid glitch pass to controller */ |
|
fsl_qspi_clk_disable_unprep(q); |
|
|
|
/* the default frequency, we will change it later if necessary. */ |
|
ret = clk_set_rate(q->clk, 66000000); |
|
if (ret) |
|
return ret; |
|
|
|
ret = fsl_qspi_clk_prep_enable(q); |
|
if (ret) |
|
return ret; |
|
|
|
/* Reset the module */ |
|
qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, |
|
base + QUADSPI_MCR); |
|
udelay(1); |
|
|
|
/* Disable the module */ |
|
qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, |
|
base + QUADSPI_MCR); |
|
|
|
/* |
|
* Previous boot stages (BootROM, bootloader) might have used DDR |
|
* mode and did not clear the TDH bits. As we currently use SDR mode |
|
* only, clear the TDH bits if necessary. |
|
*/ |
|
if (needs_tdh_setting(q)) |
|
qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & |
|
~QUADSPI_FLSHCR_TDH_MASK, |
|
base + QUADSPI_FLSHCR); |
|
|
|
reg = qspi_readl(q, base + QUADSPI_SMPR); |
|
qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK |
|
| QUADSPI_SMPR_FSPHS_MASK |
|
| QUADSPI_SMPR_HSENA_MASK |
|
| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); |
|
|
|
/* We only use the buffer3 for AHB read */ |
|
qspi_writel(q, 0, base + QUADSPI_BUF0IND); |
|
qspi_writel(q, 0, base + QUADSPI_BUF1IND); |
|
qspi_writel(q, 0, base + QUADSPI_BUF2IND); |
|
|
|
qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT), |
|
q->iobase + QUADSPI_BFGENCR); |
|
qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); |
|
qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | |
|
QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8), |
|
base + QUADSPI_BUF3CR); |
|
|
|
if (needs_amba_base_offset(q)) |
|
addr_offset = q->memmap_phy; |
|
|
|
/* |
|
* In HW there can be a maximum of four chips on two buses with |
|
* two chip selects on each bus. We use four chip selects in SW |
|
* to differentiate between the four chips. |
|
* We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, |
|
* SFB2AD accordingly. |
|
*/ |
|
qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, |
|
base + QUADSPI_SFA1AD); |
|
qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, |
|
base + QUADSPI_SFA2AD); |
|
qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, |
|
base + QUADSPI_SFB1AD); |
|
qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, |
|
base + QUADSPI_SFB2AD); |
|
|
|
q->selected = -1; |
|
|
|
/* Enable the module */ |
|
qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, |
|
base + QUADSPI_MCR); |
|
|
|
/* clear all interrupt status */ |
|
qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR); |
|
|
|
/* enable the interrupt */ |
|
qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); |
|
|
|
return 0; |
|
} |
|
|
|
static const char *fsl_qspi_get_name(struct spi_mem *mem) |
|
{ |
|
struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master); |
|
struct device *dev = &mem->spi->dev; |
|
const char *name; |
|
|
|
/* |
|
* In order to keep mtdparts compatible with the old MTD driver at |
|
* mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the |
|
* platform_device of the controller. |
|
*/ |
|
if (of_get_available_child_count(q->dev->of_node) == 1) |
|
return dev_name(q->dev); |
|
|
|
name = devm_kasprintf(dev, GFP_KERNEL, |
|
"%s-%d", dev_name(q->dev), |
|
mem->spi->chip_select); |
|
|
|
if (!name) { |
|
dev_err(dev, "failed to get memory for custom flash name\n"); |
|
return ERR_PTR(-ENOMEM); |
|
} |
|
|
|
return name; |
|
} |
|
|
|
static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { |
|
.adjust_op_size = fsl_qspi_adjust_op_size, |
|
.supports_op = fsl_qspi_supports_op, |
|
.exec_op = fsl_qspi_exec_op, |
|
.get_name = fsl_qspi_get_name, |
|
}; |
|
|
|
static int fsl_qspi_probe(struct platform_device *pdev) |
|
{ |
|
struct spi_controller *ctlr; |
|
struct device *dev = &pdev->dev; |
|
struct device_node *np = dev->of_node; |
|
struct resource *res; |
|
struct fsl_qspi *q; |
|
int ret; |
|
|
|
ctlr = spi_alloc_master(&pdev->dev, sizeof(*q)); |
|
if (!ctlr) |
|
return -ENOMEM; |
|
|
|
ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | |
|
SPI_TX_DUAL | SPI_TX_QUAD; |
|
|
|
q = spi_controller_get_devdata(ctlr); |
|
q->dev = dev; |
|
q->devtype_data = of_device_get_match_data(dev); |
|
if (!q->devtype_data) { |
|
ret = -ENODEV; |
|
goto err_put_ctrl; |
|
} |
|
|
|
platform_set_drvdata(pdev, q); |
|
|
|
/* find the resources */ |
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI"); |
|
q->iobase = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(q->iobase)) { |
|
ret = PTR_ERR(q->iobase); |
|
goto err_put_ctrl; |
|
} |
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
|
"QuadSPI-memory"); |
|
q->memmap_phy = res->start; |
|
/* Since there are 4 cs, map size required is 4 times ahb_buf_size */ |
|
q->ahb_addr = devm_ioremap(dev, q->memmap_phy, |
|
(q->devtype_data->ahb_buf_size * 4)); |
|
if (!q->ahb_addr) { |
|
ret = -ENOMEM; |
|
goto err_put_ctrl; |
|
} |
|
|
|
/* find the clocks */ |
|
q->clk_en = devm_clk_get(dev, "qspi_en"); |
|
if (IS_ERR(q->clk_en)) { |
|
ret = PTR_ERR(q->clk_en); |
|
goto err_put_ctrl; |
|
} |
|
|
|
q->clk = devm_clk_get(dev, "qspi"); |
|
if (IS_ERR(q->clk)) { |
|
ret = PTR_ERR(q->clk); |
|
goto err_put_ctrl; |
|
} |
|
|
|
ret = fsl_qspi_clk_prep_enable(q); |
|
if (ret) { |
|
dev_err(dev, "can not enable the clock\n"); |
|
goto err_put_ctrl; |
|
} |
|
|
|
/* find the irq */ |
|
ret = platform_get_irq(pdev, 0); |
|
if (ret < 0) |
|
goto err_disable_clk; |
|
|
|
ret = devm_request_irq(dev, ret, |
|
fsl_qspi_irq_handler, 0, pdev->name, q); |
|
if (ret) { |
|
dev_err(dev, "failed to request irq: %d\n", ret); |
|
goto err_disable_clk; |
|
} |
|
|
|
mutex_init(&q->lock); |
|
|
|
ctlr->bus_num = -1; |
|
ctlr->num_chipselect = 4; |
|
ctlr->mem_ops = &fsl_qspi_mem_ops; |
|
|
|
fsl_qspi_default_setup(q); |
|
|
|
ctlr->dev.of_node = np; |
|
|
|
ret = devm_spi_register_controller(dev, ctlr); |
|
if (ret) |
|
goto err_destroy_mutex; |
|
|
|
return 0; |
|
|
|
err_destroy_mutex: |
|
mutex_destroy(&q->lock); |
|
|
|
err_disable_clk: |
|
fsl_qspi_clk_disable_unprep(q); |
|
|
|
err_put_ctrl: |
|
spi_controller_put(ctlr); |
|
|
|
dev_err(dev, "Freescale QuadSPI probe failed\n"); |
|
return ret; |
|
} |
|
|
|
static int fsl_qspi_remove(struct platform_device *pdev) |
|
{ |
|
struct fsl_qspi *q = platform_get_drvdata(pdev); |
|
|
|
/* disable the hardware */ |
|
qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); |
|
qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); |
|
|
|
fsl_qspi_clk_disable_unprep(q); |
|
|
|
mutex_destroy(&q->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static int fsl_qspi_suspend(struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
|
|
static int fsl_qspi_resume(struct device *dev) |
|
{ |
|
struct fsl_qspi *q = dev_get_drvdata(dev); |
|
|
|
fsl_qspi_default_setup(q); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id fsl_qspi_dt_ids[] = { |
|
{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, }, |
|
{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, }, |
|
{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, }, |
|
{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, }, |
|
{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, }, |
|
{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); |
|
|
|
static const struct dev_pm_ops fsl_qspi_pm_ops = { |
|
.suspend = fsl_qspi_suspend, |
|
.resume = fsl_qspi_resume, |
|
}; |
|
|
|
static struct platform_driver fsl_qspi_driver = { |
|
.driver = { |
|
.name = "fsl-quadspi", |
|
.of_match_table = fsl_qspi_dt_ids, |
|
.pm = &fsl_qspi_pm_ops, |
|
}, |
|
.probe = fsl_qspi_probe, |
|
.remove = fsl_qspi_remove, |
|
}; |
|
module_platform_driver(fsl_qspi_driver); |
|
|
|
MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver"); |
|
MODULE_AUTHOR("Freescale Semiconductor Inc."); |
|
MODULE_AUTHOR("Boris Brezillon <[email protected]>"); |
|
MODULE_AUTHOR("Frieder Schrempf <[email protected]>"); |
|
MODULE_AUTHOR("Yogesh Gaur <[email protected]>"); |
|
MODULE_AUTHOR("Suresh Gupta <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|