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679 lines
17 KiB
679 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Broadcom BCM63xx SPI controller support |
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* |
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* Copyright (C) 2009-2012 Florian Fainelli <[email protected]> |
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* Copyright (C) 2010 Tanguy Bouzeloc <[email protected]> |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/spi/spi.h> |
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#include <linux/completion.h> |
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#include <linux/err.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/of.h> |
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#include <linux/reset.h> |
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|
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/* BCM 6338/6348 SPI core */ |
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#define SPI_6348_RSET_SIZE 64 |
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#define SPI_6348_CMD 0x00 /* 16-bits register */ |
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#define SPI_6348_INT_STATUS 0x02 |
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#define SPI_6348_INT_MASK_ST 0x03 |
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#define SPI_6348_INT_MASK 0x04 |
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#define SPI_6348_ST 0x05 |
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#define SPI_6348_CLK_CFG 0x06 |
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#define SPI_6348_FILL_BYTE 0x07 |
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#define SPI_6348_MSG_TAIL 0x09 |
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#define SPI_6348_RX_TAIL 0x0b |
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#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ |
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#define SPI_6348_MSG_CTL_WIDTH 8 |
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#define SPI_6348_MSG_DATA 0x41 |
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#define SPI_6348_MSG_DATA_SIZE 0x3f |
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#define SPI_6348_RX_DATA 0x80 |
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#define SPI_6348_RX_DATA_SIZE 0x3f |
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|
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/* BCM 3368/6358/6262/6368 SPI core */ |
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#define SPI_6358_RSET_SIZE 1804 |
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#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ |
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#define SPI_6358_MSG_CTL_WIDTH 16 |
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#define SPI_6358_MSG_DATA 0x02 |
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#define SPI_6358_MSG_DATA_SIZE 0x21e |
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#define SPI_6358_RX_DATA 0x400 |
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#define SPI_6358_RX_DATA_SIZE 0x220 |
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#define SPI_6358_CMD 0x700 /* 16-bits register */ |
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#define SPI_6358_INT_STATUS 0x702 |
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#define SPI_6358_INT_MASK_ST 0x703 |
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#define SPI_6358_INT_MASK 0x704 |
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#define SPI_6358_ST 0x705 |
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#define SPI_6358_CLK_CFG 0x706 |
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#define SPI_6358_FILL_BYTE 0x707 |
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#define SPI_6358_MSG_TAIL 0x709 |
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#define SPI_6358_RX_TAIL 0x70B |
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|
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/* Shared SPI definitions */ |
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|
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/* Message configuration */ |
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#define SPI_FD_RW 0x00 |
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#define SPI_HD_W 0x01 |
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#define SPI_HD_R 0x02 |
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#define SPI_BYTE_CNT_SHIFT 0 |
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#define SPI_6348_MSG_TYPE_SHIFT 6 |
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#define SPI_6358_MSG_TYPE_SHIFT 14 |
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|
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/* Command */ |
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#define SPI_CMD_NOOP 0x00 |
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#define SPI_CMD_SOFT_RESET 0x01 |
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#define SPI_CMD_HARD_RESET 0x02 |
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#define SPI_CMD_START_IMMEDIATE 0x03 |
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#define SPI_CMD_COMMAND_SHIFT 0 |
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#define SPI_CMD_COMMAND_MASK 0x000f |
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#define SPI_CMD_DEVICE_ID_SHIFT 4 |
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#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 |
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#define SPI_CMD_ONE_BYTE_SHIFT 11 |
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#define SPI_CMD_ONE_WIRE_SHIFT 12 |
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#define SPI_DEV_ID_0 0 |
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#define SPI_DEV_ID_1 1 |
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#define SPI_DEV_ID_2 2 |
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#define SPI_DEV_ID_3 3 |
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|
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/* Interrupt mask */ |
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#define SPI_INTR_CMD_DONE 0x01 |
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#define SPI_INTR_RX_OVERFLOW 0x02 |
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#define SPI_INTR_TX_UNDERFLOW 0x04 |
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#define SPI_INTR_TX_OVERFLOW 0x08 |
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#define SPI_INTR_RX_UNDERFLOW 0x10 |
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#define SPI_INTR_CLEAR_ALL 0x1f |
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|
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/* Status */ |
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#define SPI_RX_EMPTY 0x02 |
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#define SPI_CMD_BUSY 0x04 |
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#define SPI_SERIAL_BUSY 0x08 |
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|
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/* Clock configuration */ |
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#define SPI_CLK_20MHZ 0x00 |
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#define SPI_CLK_0_391MHZ 0x01 |
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#define SPI_CLK_0_781MHZ 0x02 /* default */ |
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#define SPI_CLK_1_563MHZ 0x03 |
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#define SPI_CLK_3_125MHZ 0x04 |
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#define SPI_CLK_6_250MHZ 0x05 |
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#define SPI_CLK_12_50MHZ 0x06 |
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#define SPI_CLK_MASK 0x07 |
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#define SPI_SSOFFTIME_MASK 0x38 |
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#define SPI_SSOFFTIME_SHIFT 3 |
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#define SPI_BYTE_SWAP 0x80 |
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enum bcm63xx_regs_spi { |
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SPI_CMD, |
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SPI_INT_STATUS, |
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SPI_INT_MASK_ST, |
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SPI_INT_MASK, |
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SPI_ST, |
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SPI_CLK_CFG, |
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SPI_FILL_BYTE, |
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SPI_MSG_TAIL, |
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SPI_RX_TAIL, |
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SPI_MSG_CTL, |
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SPI_MSG_DATA, |
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SPI_RX_DATA, |
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SPI_MSG_TYPE_SHIFT, |
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SPI_MSG_CTL_WIDTH, |
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SPI_MSG_DATA_SIZE, |
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}; |
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#define BCM63XX_SPI_MAX_PREPEND 15 |
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#define BCM63XX_SPI_MAX_CS 8 |
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#define BCM63XX_SPI_BUS_NUM 0 |
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struct bcm63xx_spi { |
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struct completion done; |
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void __iomem *regs; |
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int irq; |
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/* Platform data */ |
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const unsigned long *reg_offsets; |
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unsigned int fifo_size; |
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unsigned int msg_type_shift; |
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unsigned int msg_ctl_width; |
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|
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/* data iomem */ |
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u8 __iomem *tx_io; |
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const u8 __iomem *rx_io; |
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struct clk *clk; |
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struct platform_device *pdev; |
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}; |
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static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, |
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unsigned int offset) |
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{ |
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return readb(bs->regs + bs->reg_offsets[offset]); |
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} |
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static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, |
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unsigned int offset) |
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{ |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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return ioread16be(bs->regs + bs->reg_offsets[offset]); |
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#else |
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return readw(bs->regs + bs->reg_offsets[offset]); |
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#endif |
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} |
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static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, |
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u8 value, unsigned int offset) |
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{ |
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writeb(value, bs->regs + bs->reg_offsets[offset]); |
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} |
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static inline void bcm_spi_writew(struct bcm63xx_spi *bs, |
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u16 value, unsigned int offset) |
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{ |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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iowrite16be(value, bs->regs + bs->reg_offsets[offset]); |
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#else |
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writew(value, bs->regs + bs->reg_offsets[offset]); |
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#endif |
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} |
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static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { |
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{ 20000000, SPI_CLK_20MHZ }, |
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{ 12500000, SPI_CLK_12_50MHZ }, |
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{ 6250000, SPI_CLK_6_250MHZ }, |
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{ 3125000, SPI_CLK_3_125MHZ }, |
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{ 1563000, SPI_CLK_1_563MHZ }, |
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{ 781000, SPI_CLK_0_781MHZ }, |
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{ 391000, SPI_CLK_0_391MHZ } |
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}; |
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static void bcm63xx_spi_setup_transfer(struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
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u8 clk_cfg, reg; |
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int i; |
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/* Default to lowest clock configuration */ |
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clk_cfg = SPI_CLK_0_391MHZ; |
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/* Find the closest clock configuration */ |
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for (i = 0; i < SPI_CLK_MASK; i++) { |
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if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { |
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clk_cfg = bcm63xx_spi_freq_table[i][1]; |
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break; |
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} |
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} |
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/* clear existing clock configuration bits of the register */ |
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reg = bcm_spi_readb(bs, SPI_CLK_CFG); |
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reg &= ~SPI_CLK_MASK; |
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reg |= clk_cfg; |
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bcm_spi_writeb(bs, reg, SPI_CLK_CFG); |
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dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", |
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clk_cfg, t->speed_hz); |
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} |
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/* the spi->mode bits understood by this driver: */ |
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#define MODEBITS (SPI_CPOL | SPI_CPHA) |
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static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, |
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unsigned int num_transfers) |
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{ |
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
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u16 msg_ctl; |
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u16 cmd; |
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unsigned int i, timeout = 0, prepend_len = 0, len = 0; |
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struct spi_transfer *t = first; |
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bool do_rx = false; |
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bool do_tx = false; |
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/* Disable the CMD_DONE interrupt */ |
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bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
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dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
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t->tx_buf, t->rx_buf, t->len); |
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if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) |
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prepend_len = t->len; |
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/* prepare the buffer */ |
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for (i = 0; i < num_transfers; i++) { |
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if (t->tx_buf) { |
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do_tx = true; |
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memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); |
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/* don't prepend more than one tx */ |
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if (t != first) |
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prepend_len = 0; |
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} |
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if (t->rx_buf) { |
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do_rx = true; |
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/* prepend is half-duplex write only */ |
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if (t == first) |
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prepend_len = 0; |
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} |
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len += t->len; |
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t = list_entry(t->transfer_list.next, struct spi_transfer, |
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transfer_list); |
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} |
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reinit_completion(&bs->done); |
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/* Fill in the Message control register */ |
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msg_ctl = (len << SPI_BYTE_CNT_SHIFT); |
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if (do_rx && do_tx && prepend_len == 0) |
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msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
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else if (do_rx) |
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msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
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else if (do_tx) |
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msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
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switch (bs->msg_ctl_width) { |
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case 8: |
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bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); |
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break; |
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case 16: |
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bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); |
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break; |
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} |
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/* Issue the transfer */ |
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cmd = SPI_CMD_START_IMMEDIATE; |
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cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
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cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
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bcm_spi_writew(bs, cmd, SPI_CMD); |
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/* Enable the CMD_DONE interrupt */ |
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bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); |
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timeout = wait_for_completion_timeout(&bs->done, HZ); |
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if (!timeout) |
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return -ETIMEDOUT; |
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if (!do_rx) |
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return 0; |
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len = 0; |
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t = first; |
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/* Read out all the data */ |
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for (i = 0; i < num_transfers; i++) { |
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if (t->rx_buf) |
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memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); |
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if (t != first || prepend_len == 0) |
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len += t->len; |
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t = list_entry(t->transfer_list.next, struct spi_transfer, |
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transfer_list); |
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} |
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return 0; |
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} |
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static int bcm63xx_spi_transfer_one(struct spi_master *master, |
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struct spi_message *m) |
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{ |
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struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
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struct spi_transfer *t, *first = NULL; |
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struct spi_device *spi = m->spi; |
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int status = 0; |
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unsigned int n_transfers = 0, total_len = 0; |
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bool can_use_prepend = false; |
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/* |
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* This SPI controller does not support keeping CS active after a |
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* transfer. |
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* Work around this by merging as many transfers we can into one big |
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* full-duplex transfers. |
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*/ |
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list_for_each_entry(t, &m->transfers, transfer_list) { |
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if (!first) |
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first = t; |
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n_transfers++; |
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total_len += t->len; |
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if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && |
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first->len <= BCM63XX_SPI_MAX_PREPEND) |
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can_use_prepend = true; |
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else if (can_use_prepend && t->tx_buf) |
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can_use_prepend = false; |
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/* we can only transfer one fifo worth of data */ |
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if ((can_use_prepend && |
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total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || |
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(!can_use_prepend && total_len > bs->fifo_size)) { |
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dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", |
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total_len, bs->fifo_size); |
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status = -EINVAL; |
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goto exit; |
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} |
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/* all combined transfers have to have the same speed */ |
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if (t->speed_hz != first->speed_hz) { |
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dev_err(&spi->dev, "unable to change speed between transfers\n"); |
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status = -EINVAL; |
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goto exit; |
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} |
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/* CS will be deasserted directly after transfer */ |
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if (t->delay_usecs || t->delay.value) { |
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dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); |
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status = -EINVAL; |
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goto exit; |
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} |
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if (t->cs_change || |
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list_is_last(&t->transfer_list, &m->transfers)) { |
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/* configure adapter for a new transfer */ |
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bcm63xx_spi_setup_transfer(spi, first); |
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/* send the data */ |
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status = bcm63xx_txrx_bufs(spi, first, n_transfers); |
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if (status) |
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goto exit; |
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m->actual_length += total_len; |
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first = NULL; |
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n_transfers = 0; |
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total_len = 0; |
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can_use_prepend = false; |
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} |
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} |
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exit: |
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m->status = status; |
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spi_finalize_current_message(master); |
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return 0; |
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} |
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/* This driver supports single master mode only. Hence |
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* CMD_DONE is the only interrupt we care about |
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*/ |
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static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) |
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{ |
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struct spi_master *master = (struct spi_master *)dev_id; |
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struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
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u8 intr; |
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/* Read interupts and clear them immediately */ |
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intr = bcm_spi_readb(bs, SPI_INT_STATUS); |
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bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
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bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
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/* A transfer completed */ |
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if (intr & SPI_INTR_CMD_DONE) |
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complete(&bs->done); |
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return IRQ_HANDLED; |
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} |
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static size_t bcm63xx_spi_max_length(struct spi_device *spi) |
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{ |
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struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
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return bs->fifo_size; |
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} |
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static const unsigned long bcm6348_spi_reg_offsets[] = { |
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[SPI_CMD] = SPI_6348_CMD, |
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[SPI_INT_STATUS] = SPI_6348_INT_STATUS, |
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[SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST, |
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[SPI_INT_MASK] = SPI_6348_INT_MASK, |
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[SPI_ST] = SPI_6348_ST, |
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[SPI_CLK_CFG] = SPI_6348_CLK_CFG, |
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[SPI_FILL_BYTE] = SPI_6348_FILL_BYTE, |
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[SPI_MSG_TAIL] = SPI_6348_MSG_TAIL, |
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[SPI_RX_TAIL] = SPI_6348_RX_TAIL, |
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[SPI_MSG_CTL] = SPI_6348_MSG_CTL, |
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[SPI_MSG_DATA] = SPI_6348_MSG_DATA, |
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[SPI_RX_DATA] = SPI_6348_RX_DATA, |
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[SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT, |
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[SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH, |
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[SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE, |
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}; |
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static const unsigned long bcm6358_spi_reg_offsets[] = { |
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[SPI_CMD] = SPI_6358_CMD, |
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[SPI_INT_STATUS] = SPI_6358_INT_STATUS, |
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[SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST, |
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[SPI_INT_MASK] = SPI_6358_INT_MASK, |
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[SPI_ST] = SPI_6358_ST, |
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[SPI_CLK_CFG] = SPI_6358_CLK_CFG, |
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[SPI_FILL_BYTE] = SPI_6358_FILL_BYTE, |
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[SPI_MSG_TAIL] = SPI_6358_MSG_TAIL, |
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[SPI_RX_TAIL] = SPI_6358_RX_TAIL, |
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[SPI_MSG_CTL] = SPI_6358_MSG_CTL, |
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[SPI_MSG_DATA] = SPI_6358_MSG_DATA, |
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[SPI_RX_DATA] = SPI_6358_RX_DATA, |
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[SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT, |
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[SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH, |
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[SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE, |
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}; |
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static const struct platform_device_id bcm63xx_spi_dev_match[] = { |
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{ |
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.name = "bcm6348-spi", |
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.driver_data = (unsigned long)bcm6348_spi_reg_offsets, |
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}, |
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{ |
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.name = "bcm6358-spi", |
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.driver_data = (unsigned long)bcm6358_spi_reg_offsets, |
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}, |
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{ |
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}, |
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}; |
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static const struct of_device_id bcm63xx_spi_of_match[] = { |
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{ .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets }, |
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{ .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets }, |
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{ }, |
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}; |
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|
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static int bcm63xx_spi_probe(struct platform_device *pdev) |
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{ |
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struct resource *r; |
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const unsigned long *bcm63xx_spireg; |
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struct device *dev = &pdev->dev; |
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int irq, bus_num; |
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struct spi_master *master; |
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struct clk *clk; |
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struct bcm63xx_spi *bs; |
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int ret; |
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u32 num_cs = BCM63XX_SPI_MAX_CS; |
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struct reset_control *reset; |
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|
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if (dev->of_node) { |
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const struct of_device_id *match; |
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match = of_match_node(bcm63xx_spi_of_match, dev->of_node); |
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if (!match) |
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return -EINVAL; |
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bcm63xx_spireg = match->data; |
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of_property_read_u32(dev->of_node, "num-cs", &num_cs); |
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if (num_cs > BCM63XX_SPI_MAX_CS) { |
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dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", |
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num_cs); |
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num_cs = BCM63XX_SPI_MAX_CS; |
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} |
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|
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bus_num = -1; |
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} else if (pdev->id_entry->driver_data) { |
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const struct platform_device_id *match = pdev->id_entry; |
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|
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bcm63xx_spireg = (const unsigned long *)match->driver_data; |
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bus_num = BCM63XX_SPI_BUS_NUM; |
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} else { |
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return -EINVAL; |
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} |
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|
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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|
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clk = devm_clk_get(dev, "spi"); |
|
if (IS_ERR(clk)) { |
|
dev_err(dev, "no clock for device\n"); |
|
return PTR_ERR(clk); |
|
} |
|
|
|
reset = devm_reset_control_get_optional_exclusive(dev, NULL); |
|
if (IS_ERR(reset)) |
|
return PTR_ERR(reset); |
|
|
|
master = spi_alloc_master(dev, sizeof(*bs)); |
|
if (!master) { |
|
dev_err(dev, "out of memory\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
bs = spi_master_get_devdata(master); |
|
init_completion(&bs->done); |
|
|
|
platform_set_drvdata(pdev, master); |
|
bs->pdev = pdev; |
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
bs->regs = devm_ioremap_resource(&pdev->dev, r); |
|
if (IS_ERR(bs->regs)) { |
|
ret = PTR_ERR(bs->regs); |
|
goto out_err; |
|
} |
|
|
|
bs->irq = irq; |
|
bs->clk = clk; |
|
bs->reg_offsets = bcm63xx_spireg; |
|
bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; |
|
|
|
ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, |
|
pdev->name, master); |
|
if (ret) { |
|
dev_err(dev, "unable to request irq\n"); |
|
goto out_err; |
|
} |
|
|
|
master->dev.of_node = dev->of_node; |
|
master->bus_num = bus_num; |
|
master->num_chipselect = num_cs; |
|
master->transfer_one_message = bcm63xx_spi_transfer_one; |
|
master->mode_bits = MODEBITS; |
|
master->bits_per_word_mask = SPI_BPW_MASK(8); |
|
master->max_transfer_size = bcm63xx_spi_max_length; |
|
master->max_message_size = bcm63xx_spi_max_length; |
|
master->auto_runtime_pm = true; |
|
bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; |
|
bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH]; |
|
bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]); |
|
bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]); |
|
|
|
/* Initialize hardware */ |
|
ret = clk_prepare_enable(bs->clk); |
|
if (ret) |
|
goto out_err; |
|
|
|
ret = reset_control_reset(reset); |
|
if (ret) { |
|
dev_err(dev, "unable to reset device: %d\n", ret); |
|
goto out_clk_disable; |
|
} |
|
|
|
bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
|
|
|
/* register and we are done */ |
|
ret = devm_spi_register_master(dev, master); |
|
if (ret) { |
|
dev_err(dev, "spi register failed\n"); |
|
goto out_clk_disable; |
|
} |
|
|
|
dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n", |
|
r, irq, bs->fifo_size); |
|
|
|
return 0; |
|
|
|
out_clk_disable: |
|
clk_disable_unprepare(clk); |
|
out_err: |
|
spi_master_put(master); |
|
return ret; |
|
} |
|
|
|
static int bcm63xx_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master = platform_get_drvdata(pdev); |
|
struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
|
|
|
/* reset spi block */ |
|
bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
|
|
|
/* HW shutdown */ |
|
clk_disable_unprepare(bs->clk); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int bcm63xx_spi_suspend(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
|
|
|
spi_master_suspend(master); |
|
|
|
clk_disable_unprepare(bs->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int bcm63xx_spi_resume(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
|
int ret; |
|
|
|
ret = clk_prepare_enable(bs->clk); |
|
if (ret) |
|
return ret; |
|
|
|
spi_master_resume(master); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static const struct dev_pm_ops bcm63xx_spi_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) |
|
}; |
|
|
|
static struct platform_driver bcm63xx_spi_driver = { |
|
.driver = { |
|
.name = "bcm63xx-spi", |
|
.pm = &bcm63xx_spi_pm_ops, |
|
.of_match_table = bcm63xx_spi_of_match, |
|
}, |
|
.id_table = bcm63xx_spi_dev_match, |
|
.probe = bcm63xx_spi_probe, |
|
.remove = bcm63xx_spi_remove, |
|
}; |
|
|
|
module_platform_driver(bcm63xx_spi_driver); |
|
|
|
MODULE_ALIAS("platform:bcm63xx_spi"); |
|
MODULE_AUTHOR("Florian Fainelli <[email protected]>"); |
|
MODULE_AUTHOR("Tanguy Bouzeloc <[email protected]>"); |
|
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); |
|
MODULE_LICENSE("GPL");
|
|
|