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533 lines
14 KiB
533 lines
14 KiB
/* |
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* Broadcom BCM63XX High Speed SPI Controller driver |
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* |
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* Copyright 2000-2010 Broadcom Corporation |
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* Copyright 2012-2013 Jonas Gorski <[email protected]> |
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* |
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* Licensed under the GNU/GPL. See COPYING for details. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/spi/spi.h> |
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#include <linux/mutex.h> |
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#include <linux/of.h> |
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#include <linux/reset.h> |
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#define HSSPI_GLOBAL_CTRL_REG 0x0 |
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#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 |
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#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff |
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#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8 |
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#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00 |
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#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16) |
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#define GLOBAL_CTRL_CLK_POLARITY BIT(17) |
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#define GLOBAL_CTRL_MOSI_IDLE BIT(18) |
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#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4 |
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#define HSSPI_INT_STATUS_REG 0x8 |
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#define HSSPI_INT_STATUS_MASKED_REG 0xc |
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#define HSSPI_INT_MASK_REG 0x10 |
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#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0) |
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#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1) |
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#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2) |
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#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3) |
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#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4) |
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#define HSSPI_INT_CLEAR_ALL 0xff001f1f |
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#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40) |
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#define PINGPONG_CMD_COMMAND_MASK 0xf |
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#define PINGPONG_COMMAND_NOOP 0 |
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#define PINGPONG_COMMAND_START_NOW 1 |
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#define PINGPONG_COMMAND_START_TRIGGER 2 |
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#define PINGPONG_COMMAND_HALT 3 |
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#define PINGPONG_COMMAND_FLUSH 4 |
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#define PINGPONG_CMD_PROFILE_SHIFT 8 |
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#define PINGPONG_CMD_SS_SHIFT 12 |
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#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) |
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#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) |
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#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff |
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#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) |
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#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) |
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#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20) |
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#define SIGNAL_CTRL_LATCH_RISING BIT(12) |
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#define SIGNAL_CTRL_LAUNCH_RISING BIT(13) |
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#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16) |
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#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20) |
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#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8 |
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#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12 |
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#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16 |
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#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18 |
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#define MODE_CTRL_MODE_3WIRE BIT(20) |
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#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24 |
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#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200) |
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#define HSSPI_OP_MULTIBIT BIT(11) |
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#define HSSPI_OP_CODE_SHIFT 13 |
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#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT) |
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#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT) |
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#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT) |
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#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT) |
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#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT) |
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#define HSSPI_BUFFER_LEN 512 |
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#define HSSPI_OPCODE_LEN 2 |
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#define HSSPI_MAX_PREPEND_LEN 15 |
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#define HSSPI_MAX_SYNC_CLOCK 30000000 |
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#define HSSPI_SPI_MAX_CS 8 |
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#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ |
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struct bcm63xx_hsspi { |
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struct completion done; |
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struct mutex bus_mutex; |
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struct platform_device *pdev; |
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struct clk *clk; |
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struct clk *pll_clk; |
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void __iomem *regs; |
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u8 __iomem *fifo; |
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u32 speed_hz; |
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u8 cs_polarity; |
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}; |
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static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, |
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bool active) |
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{ |
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u32 reg; |
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mutex_lock(&bs->bus_mutex); |
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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reg &= ~BIT(cs); |
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if (active == !(bs->cs_polarity & BIT(cs))) |
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reg |= BIT(cs); |
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__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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mutex_unlock(&bs->bus_mutex); |
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} |
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static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, |
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struct spi_device *spi, int hz) |
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{ |
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unsigned int profile = spi->chip_select; |
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u32 reg; |
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reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); |
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__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, |
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bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); |
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reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); |
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if (hz > HSSPI_MAX_SYNC_CLOCK) |
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reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH; |
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else |
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reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH; |
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__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); |
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mutex_lock(&bs->bus_mutex); |
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/* setup clock polarity */ |
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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reg &= ~GLOBAL_CTRL_CLK_POLARITY; |
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if (spi->mode & SPI_CPOL) |
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reg |= GLOBAL_CTRL_CLK_POLARITY; |
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__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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mutex_unlock(&bs->bus_mutex); |
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} |
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static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) |
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{ |
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struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); |
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unsigned int chip_select = spi->chip_select; |
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u16 opcode = 0; |
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int pending = t->len; |
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int step_size = HSSPI_BUFFER_LEN; |
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const u8 *tx = t->tx_buf; |
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u8 *rx = t->rx_buf; |
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bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); |
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bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); |
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if (tx && rx) |
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opcode = HSSPI_OP_READ_WRITE; |
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else if (tx) |
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opcode = HSSPI_OP_WRITE; |
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else if (rx) |
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opcode = HSSPI_OP_READ; |
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if (opcode != HSSPI_OP_READ) |
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step_size -= HSSPI_OPCODE_LEN; |
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if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || |
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(opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) |
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opcode |= HSSPI_OP_MULTIBIT; |
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__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | |
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1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, |
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bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); |
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while (pending > 0) { |
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int curr_step = min_t(int, step_size, pending); |
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reinit_completion(&bs->done); |
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if (tx) { |
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memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); |
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tx += curr_step; |
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} |
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__raw_writew(opcode | curr_step, bs->fifo); |
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/* enable interrupt */ |
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__raw_writel(HSSPI_PINGx_CMD_DONE(0), |
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bs->regs + HSSPI_INT_MASK_REG); |
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/* start the transfer */ |
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__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | |
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chip_select << PINGPONG_CMD_PROFILE_SHIFT | |
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PINGPONG_COMMAND_START_NOW, |
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bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); |
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if (wait_for_completion_timeout(&bs->done, HZ) == 0) { |
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dev_err(&bs->pdev->dev, "transfer timed out!\n"); |
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return -ETIMEDOUT; |
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} |
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if (rx) { |
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memcpy_fromio(rx, bs->fifo, curr_step); |
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rx += curr_step; |
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} |
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pending -= curr_step; |
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} |
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return 0; |
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} |
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static int bcm63xx_hsspi_setup(struct spi_device *spi) |
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{ |
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struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); |
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u32 reg; |
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reg = __raw_readl(bs->regs + |
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HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); |
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reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); |
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if (spi->mode & SPI_CPHA) |
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reg |= SIGNAL_CTRL_LAUNCH_RISING; |
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else |
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reg |= SIGNAL_CTRL_LATCH_RISING; |
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__raw_writel(reg, bs->regs + |
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HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); |
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mutex_lock(&bs->bus_mutex); |
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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/* only change actual polarities if there is no transfer */ |
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if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) { |
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if (spi->mode & SPI_CS_HIGH) |
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reg |= BIT(spi->chip_select); |
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else |
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reg &= ~BIT(spi->chip_select); |
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__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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} |
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if (spi->mode & SPI_CS_HIGH) |
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bs->cs_polarity |= BIT(spi->chip_select); |
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else |
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bs->cs_polarity &= ~BIT(spi->chip_select); |
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mutex_unlock(&bs->bus_mutex); |
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return 0; |
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} |
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static int bcm63xx_hsspi_transfer_one(struct spi_master *master, |
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struct spi_message *msg) |
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{ |
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struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); |
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struct spi_transfer *t; |
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struct spi_device *spi = msg->spi; |
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int status = -EINVAL; |
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int dummy_cs; |
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u32 reg; |
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/* This controller does not support keeping CS active during idle. |
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* To work around this, we use the following ugly hack: |
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* |
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* a. Invert the target chip select's polarity so it will be active. |
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* b. Select a "dummy" chip select to use as the hardware target. |
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* c. Invert the dummy chip select's polarity so it will be inactive |
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* during the actual transfers. |
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* d. Tell the hardware to send to the dummy chip select. Thanks to |
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* the multiplexed nature of SPI the actual target will receive |
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* the transfer and we see its response. |
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* |
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* e. At the end restore the polarities again to their default values. |
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*/ |
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dummy_cs = !spi->chip_select; |
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bcm63xx_hsspi_set_cs(bs, dummy_cs, true); |
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list_for_each_entry(t, &msg->transfers, transfer_list) { |
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status = bcm63xx_hsspi_do_txrx(spi, t); |
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if (status) |
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break; |
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msg->actual_length += t->len; |
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spi_transfer_delay_exec(t); |
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if (t->cs_change) |
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bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); |
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} |
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mutex_lock(&bs->bus_mutex); |
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK; |
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reg |= bs->cs_polarity; |
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__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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mutex_unlock(&bs->bus_mutex); |
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msg->status = status; |
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spi_finalize_current_message(master); |
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return 0; |
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} |
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static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id) |
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{ |
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struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id; |
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if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) |
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return IRQ_NONE; |
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__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); |
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__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); |
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complete(&bs->done); |
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return IRQ_HANDLED; |
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} |
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static int bcm63xx_hsspi_probe(struct platform_device *pdev) |
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{ |
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struct spi_master *master; |
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struct bcm63xx_hsspi *bs; |
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void __iomem *regs; |
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struct device *dev = &pdev->dev; |
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struct clk *clk, *pll_clk = NULL; |
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int irq, ret; |
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u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; |
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struct reset_control *reset; |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(regs)) |
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return PTR_ERR(regs); |
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clk = devm_clk_get(dev, "hsspi"); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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reset = devm_reset_control_get_optional_exclusive(dev, NULL); |
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if (IS_ERR(reset)) |
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return PTR_ERR(reset); |
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ret = clk_prepare_enable(clk); |
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if (ret) |
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return ret; |
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ret = reset_control_reset(reset); |
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if (ret) { |
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dev_err(dev, "unable to reset device: %d\n", ret); |
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goto out_disable_clk; |
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} |
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rate = clk_get_rate(clk); |
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if (!rate) { |
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pll_clk = devm_clk_get(dev, "pll"); |
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if (IS_ERR(pll_clk)) { |
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ret = PTR_ERR(pll_clk); |
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goto out_disable_clk; |
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} |
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ret = clk_prepare_enable(pll_clk); |
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if (ret) |
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goto out_disable_clk; |
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rate = clk_get_rate(pll_clk); |
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if (!rate) { |
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ret = -EINVAL; |
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goto out_disable_pll_clk; |
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} |
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} |
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master = spi_alloc_master(&pdev->dev, sizeof(*bs)); |
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if (!master) { |
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ret = -ENOMEM; |
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goto out_disable_pll_clk; |
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} |
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bs = spi_master_get_devdata(master); |
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bs->pdev = pdev; |
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bs->clk = clk; |
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bs->pll_clk = pll_clk; |
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bs->regs = regs; |
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bs->speed_hz = rate; |
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bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); |
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mutex_init(&bs->bus_mutex); |
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init_completion(&bs->done); |
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master->dev.of_node = dev->of_node; |
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if (!dev->of_node) |
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master->bus_num = HSSPI_BUS_NUM; |
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of_property_read_u32(dev->of_node, "num-cs", &num_cs); |
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if (num_cs > 8) { |
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dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", |
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num_cs); |
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num_cs = HSSPI_SPI_MAX_CS; |
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} |
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master->num_chipselect = num_cs; |
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master->setup = bcm63xx_hsspi_setup; |
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master->transfer_one_message = bcm63xx_hsspi_transfer_one; |
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
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SPI_RX_DUAL | SPI_TX_DUAL; |
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master->bits_per_word_mask = SPI_BPW_MASK(8); |
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master->auto_runtime_pm = true; |
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platform_set_drvdata(pdev, master); |
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/* Initialize the hardware */ |
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__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); |
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/* clean up any pending interrupts */ |
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__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); |
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/* read out default CS polarities */ |
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK; |
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__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, |
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bs->regs + HSSPI_GLOBAL_CTRL_REG); |
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ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, |
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pdev->name, bs); |
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if (ret) |
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goto out_put_master; |
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/* register and we are done */ |
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ret = devm_spi_register_master(dev, master); |
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if (ret) |
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goto out_put_master; |
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return 0; |
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out_put_master: |
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spi_master_put(master); |
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out_disable_pll_clk: |
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clk_disable_unprepare(pll_clk); |
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out_disable_clk: |
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clk_disable_unprepare(clk); |
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return ret; |
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} |
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static int bcm63xx_hsspi_remove(struct platform_device *pdev) |
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{ |
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struct spi_master *master = platform_get_drvdata(pdev); |
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struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); |
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/* reset the hardware and block queue progress */ |
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__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); |
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clk_disable_unprepare(bs->pll_clk); |
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clk_disable_unprepare(bs->clk); |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int bcm63xx_hsspi_suspend(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); |
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spi_master_suspend(master); |
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clk_disable_unprepare(bs->pll_clk); |
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clk_disable_unprepare(bs->clk); |
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return 0; |
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} |
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static int bcm63xx_hsspi_resume(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); |
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int ret; |
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ret = clk_prepare_enable(bs->clk); |
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if (ret) |
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return ret; |
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if (bs->pll_clk) { |
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ret = clk_prepare_enable(bs->pll_clk); |
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if (ret) { |
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clk_disable_unprepare(bs->clk); |
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return ret; |
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} |
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} |
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spi_master_resume(master); |
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return 0; |
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} |
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#endif |
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static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend, |
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bcm63xx_hsspi_resume); |
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|
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static const struct of_device_id bcm63xx_hsspi_of_match[] = { |
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{ .compatible = "brcm,bcm6328-hsspi", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match); |
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static struct platform_driver bcm63xx_hsspi_driver = { |
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.driver = { |
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.name = "bcm63xx-hsspi", |
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.pm = &bcm63xx_hsspi_pm_ops, |
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.of_match_table = bcm63xx_hsspi_of_match, |
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}, |
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.probe = bcm63xx_hsspi_probe, |
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.remove = bcm63xx_hsspi_remove, |
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}; |
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module_platform_driver(bcm63xx_hsspi_driver); |
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MODULE_ALIAS("platform:bcm63xx_hsspi"); |
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MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver"); |
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MODULE_AUTHOR("Jonas Gorski <[email protected]>"); |
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MODULE_LICENSE("GPL");
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