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618 lines
17 KiB
618 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for Broadcom BCM2835 auxiliary SPI Controllers |
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* |
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* the driver does not rely on the native chipselects at all |
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* but only uses the gpio type chipselects |
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* |
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* Based on: spi-bcm2835.c |
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* |
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* Copyright (C) 2015 Martin Sperl |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/debugfs.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_gpio.h> |
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#include <linux/of_irq.h> |
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#include <linux/regmap.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spinlock.h> |
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/* define polling limits */ |
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static unsigned int polling_limit_us = 30; |
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module_param(polling_limit_us, uint, 0664); |
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MODULE_PARM_DESC(polling_limit_us, |
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"time in us to run a transfer in polling mode - if zero no polling is used\n"); |
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/* |
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* spi register defines |
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* |
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* note there is garbage in the "official" documentation, |
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* so some data is taken from the file: |
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* brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h |
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* inside of: |
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* http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz |
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*/ |
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|
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/* SPI register offsets */ |
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#define BCM2835_AUX_SPI_CNTL0 0x00 |
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#define BCM2835_AUX_SPI_CNTL1 0x04 |
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#define BCM2835_AUX_SPI_STAT 0x08 |
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#define BCM2835_AUX_SPI_PEEK 0x0C |
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#define BCM2835_AUX_SPI_IO 0x20 |
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#define BCM2835_AUX_SPI_TXHOLD 0x30 |
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|
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/* Bitfields in CNTL0 */ |
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#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 |
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#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF |
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#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 |
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#define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 |
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#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 |
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#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 |
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#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 |
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#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 |
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#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 |
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#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 |
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#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 |
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#define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 |
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#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 |
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#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 |
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#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F |
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|
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/* Bitfields in CNTL1 */ |
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#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 |
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#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 |
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#define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 |
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#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 |
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#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 |
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/* Bitfields in STAT */ |
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#define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 |
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#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 |
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#define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 |
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#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 |
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#define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 |
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#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 |
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#define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 |
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#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F |
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struct bcm2835aux_spi { |
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void __iomem *regs; |
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struct clk *clk; |
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int irq; |
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u32 cntl[2]; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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int tx_len; |
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int rx_len; |
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int pending; |
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u64 count_transfer_polling; |
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u64 count_transfer_irq; |
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u64 count_transfer_irq_after_poll; |
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struct dentry *debugfs_dir; |
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}; |
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#if defined(CONFIG_DEBUG_FS) |
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static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, |
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const char *dname) |
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{ |
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char name[64]; |
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struct dentry *dir; |
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|
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/* get full name */ |
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snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); |
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/* the base directory */ |
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dir = debugfs_create_dir(name, NULL); |
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bs->debugfs_dir = dir; |
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/* the counters */ |
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debugfs_create_u64("count_transfer_polling", 0444, dir, |
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&bs->count_transfer_polling); |
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debugfs_create_u64("count_transfer_irq", 0444, dir, |
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&bs->count_transfer_irq); |
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debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir, |
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&bs->count_transfer_irq_after_poll); |
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} |
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static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) |
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{ |
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debugfs_remove_recursive(bs->debugfs_dir); |
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bs->debugfs_dir = NULL; |
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} |
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#else |
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static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, |
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const char *dname) |
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{ |
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} |
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static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) |
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{ |
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} |
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#endif /* CONFIG_DEBUG_FS */ |
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static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) |
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{ |
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return readl(bs->regs + reg); |
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} |
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static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, |
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u32 val) |
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{ |
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writel(val, bs->regs + reg); |
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} |
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static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) |
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{ |
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u32 data; |
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int count = min(bs->rx_len, 3); |
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data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); |
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if (bs->rx_buf) { |
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switch (count) { |
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case 3: |
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*bs->rx_buf++ = (data >> 16) & 0xff; |
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fallthrough; |
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case 2: |
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*bs->rx_buf++ = (data >> 8) & 0xff; |
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fallthrough; |
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case 1: |
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*bs->rx_buf++ = (data >> 0) & 0xff; |
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/* fallthrough - no default */ |
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} |
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} |
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bs->rx_len -= count; |
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bs->pending -= count; |
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} |
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static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) |
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{ |
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u32 data; |
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u8 byte; |
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int count; |
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int i; |
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/* gather up to 3 bytes to write to the FIFO */ |
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count = min(bs->tx_len, 3); |
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data = 0; |
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for (i = 0; i < count; i++) { |
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byte = bs->tx_buf ? *bs->tx_buf++ : 0; |
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data |= byte << (8 * (2 - i)); |
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} |
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/* and set the variable bit-length */ |
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data |= (count * 8) << 24; |
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/* and decrement length */ |
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bs->tx_len -= count; |
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bs->pending += count; |
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/* write to the correct TX-register */ |
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if (bs->tx_len) |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); |
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else |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); |
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} |
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static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) |
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{ |
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/* disable spi clearing fifo and interrupts */ |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, |
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BCM2835_AUX_SPI_CNTL0_CLEARFIFO); |
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} |
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static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) |
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{ |
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u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); |
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/* check if we have data to read */ |
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for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL); |
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stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT)) |
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bcm2835aux_rd_fifo(bs); |
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/* check if we have data to write */ |
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while (bs->tx_len && |
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(bs->pending < 12) && |
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(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
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BCM2835_AUX_SPI_STAT_TX_FULL))) { |
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bcm2835aux_wr_fifo(bs); |
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} |
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} |
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static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) |
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{ |
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struct spi_master *master = dev_id; |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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/* IRQ may be shared, so return if our interrupts are disabled */ |
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if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & |
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(BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) |
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return IRQ_NONE; |
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/* do common fifo handling */ |
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bcm2835aux_spi_transfer_helper(bs); |
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if (!bs->tx_len) { |
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/* disable tx fifo empty interrupt */ |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | |
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BCM2835_AUX_SPI_CNTL1_IDLE); |
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} |
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/* and if rx_len is 0 then disable interrupts and wake up completion */ |
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if (!bs->rx_len) { |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
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spi_finalize_current_transfer(master); |
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} |
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return IRQ_HANDLED; |
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} |
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static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *tfr) |
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{ |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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/* enable interrupts */ |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | |
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BCM2835_AUX_SPI_CNTL1_TXEMPTY | |
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BCM2835_AUX_SPI_CNTL1_IDLE); |
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/* and wait for finish... */ |
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return 1; |
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} |
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static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *tfr) |
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{ |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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/* update statistics */ |
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bs->count_transfer_irq++; |
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/* fill in registers and fifos before enabling interrupts */ |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); |
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/* fill in tx fifo with data before enabling interrupts */ |
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while ((bs->tx_len) && |
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(bs->pending < 12) && |
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(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
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BCM2835_AUX_SPI_STAT_TX_FULL))) { |
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bcm2835aux_wr_fifo(bs); |
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} |
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/* now run the interrupt mode */ |
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return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); |
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} |
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static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *tfr) |
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{ |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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unsigned long timeout; |
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/* update statistics */ |
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bs->count_transfer_polling++; |
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/* configure spi */ |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); |
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/* set the timeout to at least 2 jiffies */ |
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timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; |
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/* loop until finished the transfer */ |
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while (bs->rx_len) { |
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/* do common fifo handling */ |
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bcm2835aux_spi_transfer_helper(bs); |
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/* there is still data pending to read check the timeout */ |
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if (bs->rx_len && time_after(jiffies, timeout)) { |
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dev_dbg_ratelimited(&spi->dev, |
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"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", |
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jiffies - timeout, |
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bs->tx_len, bs->rx_len); |
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/* forward to interrupt handler */ |
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bs->count_transfer_irq_after_poll++; |
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return __bcm2835aux_spi_transfer_one_irq(master, |
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spi, tfr); |
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} |
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} |
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/* and return without waiting for completion */ |
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return 0; |
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} |
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static int bcm2835aux_spi_transfer_one(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *tfr) |
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{ |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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unsigned long spi_hz, clk_hz, speed; |
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unsigned long hz_per_byte, byte_limit; |
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/* calculate the registers to handle |
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* |
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* note that we use the variable data mode, which |
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* is not optimal for longer transfers as we waste registers |
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* resulting (potentially) in more interrupts when transferring |
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* more than 12 bytes |
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*/ |
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/* set clock */ |
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spi_hz = tfr->speed_hz; |
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clk_hz = clk_get_rate(bs->clk); |
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if (spi_hz >= clk_hz / 2) { |
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speed = 0; |
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} else if (spi_hz) { |
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speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; |
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if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) |
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speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; |
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} else { /* the slowest we can go */ |
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speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; |
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} |
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/* mask out old speed from previous spi_transfer */ |
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bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); |
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/* set the new speed */ |
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bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; |
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tfr->effective_speed_hz = clk_hz / (2 * (speed + 1)); |
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/* set transmit buffers and length */ |
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bs->tx_buf = tfr->tx_buf; |
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bs->rx_buf = tfr->rx_buf; |
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bs->tx_len = tfr->len; |
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bs->rx_len = tfr->len; |
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bs->pending = 0; |
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/* Calculate the estimated time in us the transfer runs. Note that |
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* there are are 2 idle clocks cycles after each chunk getting |
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* transferred - in our case the chunk size is 3 bytes, so we |
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* approximate this by 9 cycles/byte. This is used to find the number |
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* of Hz per byte per polling limit. E.g., we can transfer 1 byte in |
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* 30 µs per 300,000 Hz of bus clock. |
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*/ |
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hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; |
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byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1; |
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/* run in polling mode for short transfers */ |
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if (tfr->len < byte_limit) |
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return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); |
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/* run in interrupt mode for all others */ |
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return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); |
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} |
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static int bcm2835aux_spi_prepare_message(struct spi_master *master, |
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struct spi_message *msg) |
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{ |
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struct spi_device *spi = msg->spi; |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | |
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BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | |
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BCM2835_AUX_SPI_CNTL0_MSBF_OUT; |
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bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; |
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/* handle all the modes */ |
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if (spi->mode & SPI_CPOL) { |
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bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; |
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bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; |
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} else { |
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bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; |
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} |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
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bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); |
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return 0; |
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} |
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static int bcm2835aux_spi_unprepare_message(struct spi_master *master, |
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struct spi_message *msg) |
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{ |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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bcm2835aux_spi_reset_hw(bs); |
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return 0; |
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} |
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static void bcm2835aux_spi_handle_err(struct spi_master *master, |
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struct spi_message *msg) |
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{ |
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struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
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bcm2835aux_spi_reset_hw(bs); |
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} |
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static int bcm2835aux_spi_setup(struct spi_device *spi) |
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{ |
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int ret; |
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|
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/* sanity check for native cs */ |
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if (spi->mode & SPI_NO_CS) |
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return 0; |
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if (gpio_is_valid(spi->cs_gpio)) { |
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/* with gpio-cs set the GPIO to the correct level |
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* and as output (in case the dt has the gpio not configured |
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* as output but native cs) |
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*/ |
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ret = gpio_direction_output(spi->cs_gpio, |
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(spi->mode & SPI_CS_HIGH) ? 0 : 1); |
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if (ret) |
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dev_err(&spi->dev, |
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"could not set gpio %i as output: %i\n", |
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spi->cs_gpio, ret); |
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return ret; |
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} |
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|
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/* for dt-backwards compatibility: only support native on CS0 |
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* known things not supported with broken native CS: |
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* * multiple chip-selects: cs0-cs2 are all |
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* simultaniously asserted whenever there is a transfer |
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* this even includes SPI_NO_CS |
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* * SPI_CS_HIGH: cs are always asserted low |
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* * cs_change: cs is deasserted after each spi_transfer |
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* * cs_delay_usec: cs is always deasserted one SCK cycle |
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* after the last transfer |
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* probably more... |
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*/ |
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dev_warn(&spi->dev, |
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"Native CS is not supported - please configure cs-gpio in device-tree\n"); |
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if (spi->chip_select == 0) |
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return 0; |
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dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); |
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|
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return -EINVAL; |
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} |
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|
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static int bcm2835aux_spi_probe(struct platform_device *pdev) |
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{ |
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struct spi_master *master; |
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struct bcm2835aux_spi *bs; |
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unsigned long clk_hz; |
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int err; |
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master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs)); |
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if (!master) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, master); |
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master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); |
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master->bits_per_word_mask = SPI_BPW_MASK(8); |
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/* even though the driver never officially supported native CS |
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* allow a single native CS for legacy DT support purposes when |
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* no cs-gpio is configured. |
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* Known limitations for native cs are: |
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* * multiple chip-selects: cs0-cs2 are all simultaniously asserted |
|
* whenever there is a transfer - this even includes SPI_NO_CS |
|
* * SPI_CS_HIGH: is ignores - cs are always asserted low |
|
* * cs_change: cs is deasserted after each spi_transfer |
|
* * cs_delay_usec: cs is always deasserted one SCK cycle after |
|
* a spi_transfer |
|
*/ |
|
master->num_chipselect = 1; |
|
master->setup = bcm2835aux_spi_setup; |
|
master->transfer_one = bcm2835aux_spi_transfer_one; |
|
master->handle_err = bcm2835aux_spi_handle_err; |
|
master->prepare_message = bcm2835aux_spi_prepare_message; |
|
master->unprepare_message = bcm2835aux_spi_unprepare_message; |
|
master->dev.of_node = pdev->dev.of_node; |
|
|
|
bs = spi_master_get_devdata(master); |
|
|
|
/* the main area */ |
|
bs->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(bs->regs)) |
|
return PTR_ERR(bs->regs); |
|
|
|
bs->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(bs->clk)) { |
|
err = PTR_ERR(bs->clk); |
|
dev_err(&pdev->dev, "could not get clk: %d\n", err); |
|
return err; |
|
} |
|
|
|
bs->irq = platform_get_irq(pdev, 0); |
|
if (bs->irq <= 0) |
|
return bs->irq ? bs->irq : -ENODEV; |
|
|
|
/* this also enables the HW block */ |
|
err = clk_prepare_enable(bs->clk); |
|
if (err) { |
|
dev_err(&pdev->dev, "could not prepare clock: %d\n", err); |
|
return err; |
|
} |
|
|
|
/* just checking if the clock returns a sane value */ |
|
clk_hz = clk_get_rate(bs->clk); |
|
if (!clk_hz) { |
|
dev_err(&pdev->dev, "clock returns 0 Hz\n"); |
|
err = -ENODEV; |
|
goto out_clk_disable; |
|
} |
|
|
|
/* reset SPI-HW block */ |
|
bcm2835aux_spi_reset_hw(bs); |
|
|
|
err = devm_request_irq(&pdev->dev, bs->irq, |
|
bcm2835aux_spi_interrupt, |
|
IRQF_SHARED, |
|
dev_name(&pdev->dev), master); |
|
if (err) { |
|
dev_err(&pdev->dev, "could not request IRQ: %d\n", err); |
|
goto out_clk_disable; |
|
} |
|
|
|
err = spi_register_master(master); |
|
if (err) { |
|
dev_err(&pdev->dev, "could not register SPI master: %d\n", err); |
|
goto out_clk_disable; |
|
} |
|
|
|
bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev)); |
|
|
|
return 0; |
|
|
|
out_clk_disable: |
|
clk_disable_unprepare(bs->clk); |
|
return err; |
|
} |
|
|
|
static int bcm2835aux_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master = platform_get_drvdata(pdev); |
|
struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
|
|
|
bcm2835aux_debugfs_remove(bs); |
|
|
|
spi_unregister_master(master); |
|
|
|
bcm2835aux_spi_reset_hw(bs); |
|
|
|
/* disable the HW block by releasing the clock */ |
|
clk_disable_unprepare(bs->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id bcm2835aux_spi_match[] = { |
|
{ .compatible = "brcm,bcm2835-aux-spi", }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); |
|
|
|
static struct platform_driver bcm2835aux_spi_driver = { |
|
.driver = { |
|
.name = "spi-bcm2835aux", |
|
.of_match_table = bcm2835aux_spi_match, |
|
}, |
|
.probe = bcm2835aux_spi_probe, |
|
.remove = bcm2835aux_spi_remove, |
|
}; |
|
module_platform_driver(bcm2835aux_spi_driver); |
|
|
|
MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); |
|
MODULE_AUTHOR("Martin Sperl <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|