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698 lines
17 KiB
698 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Driver for AT91 USART Controllers as SPI |
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// |
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// Copyright (C) 2018 Microchip Technology Inc. |
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// |
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// Author: Radu Pirea <[email protected]> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-direction.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_gpio.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/spi/spi.h> |
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#define US_CR 0x00 |
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#define US_MR 0x04 |
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#define US_IER 0x08 |
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#define US_IDR 0x0C |
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#define US_CSR 0x14 |
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#define US_RHR 0x18 |
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#define US_THR 0x1C |
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#define US_BRGR 0x20 |
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#define US_VERSION 0xFC |
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#define US_CR_RSTRX BIT(2) |
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#define US_CR_RSTTX BIT(3) |
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#define US_CR_RXEN BIT(4) |
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#define US_CR_RXDIS BIT(5) |
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#define US_CR_TXEN BIT(6) |
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#define US_CR_TXDIS BIT(7) |
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#define US_MR_SPI_MASTER 0x0E |
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#define US_MR_CHRL GENMASK(7, 6) |
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#define US_MR_CPHA BIT(8) |
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#define US_MR_CPOL BIT(16) |
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#define US_MR_CLKO BIT(18) |
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#define US_MR_WRDBT BIT(20) |
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#define US_MR_LOOP BIT(15) |
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#define US_IR_RXRDY BIT(0) |
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#define US_IR_TXRDY BIT(1) |
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#define US_IR_OVRE BIT(5) |
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#define US_BRGR_SIZE BIT(16) |
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#define US_MIN_CLK_DIV 0x06 |
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#define US_MAX_CLK_DIV BIT(16) |
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#define US_RESET (US_CR_RSTRX | US_CR_RSTTX) |
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#define US_DISABLE (US_CR_RXDIS | US_CR_TXDIS) |
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#define US_ENABLE (US_CR_RXEN | US_CR_TXEN) |
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#define US_OVRE_RXRDY_IRQS (US_IR_OVRE | US_IR_RXRDY) |
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#define US_INIT \ |
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(US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT) |
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#define US_DMA_MIN_BYTES 16 |
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#define US_DMA_TIMEOUT (msecs_to_jiffies(1000)) |
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/* Register access macros */ |
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#define at91_usart_spi_readl(port, reg) \ |
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readl_relaxed((port)->regs + US_##reg) |
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#define at91_usart_spi_writel(port, reg, value) \ |
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writel_relaxed((value), (port)->regs + US_##reg) |
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#define at91_usart_spi_readb(port, reg) \ |
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readb_relaxed((port)->regs + US_##reg) |
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#define at91_usart_spi_writeb(port, reg, value) \ |
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writeb_relaxed((value), (port)->regs + US_##reg) |
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struct at91_usart_spi { |
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struct platform_device *mpdev; |
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struct spi_transfer *current_transfer; |
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void __iomem *regs; |
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struct device *dev; |
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struct clk *clk; |
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struct completion xfer_completion; |
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/*used in interrupt to protect data reading*/ |
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spinlock_t lock; |
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phys_addr_t phybase; |
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int irq; |
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unsigned int current_tx_remaining_bytes; |
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unsigned int current_rx_remaining_bytes; |
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u32 spi_clk; |
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u32 status; |
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bool xfer_failed; |
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bool use_dma; |
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}; |
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static void dma_callback(void *data) |
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{ |
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struct spi_controller *ctlr = data; |
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
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at91_usart_spi_writel(aus, IER, US_IR_RXRDY); |
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aus->current_rx_remaining_bytes = 0; |
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complete(&aus->xfer_completion); |
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} |
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static bool at91_usart_spi_can_dma(struct spi_controller *ctrl, |
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struct spi_device *spi, |
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struct spi_transfer *xfer) |
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{ |
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struct at91_usart_spi *aus = spi_master_get_devdata(ctrl); |
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return aus->use_dma && xfer->len >= US_DMA_MIN_BYTES; |
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} |
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static int at91_usart_spi_configure_dma(struct spi_controller *ctlr, |
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struct at91_usart_spi *aus) |
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{ |
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struct dma_slave_config slave_config; |
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struct device *dev = &aus->mpdev->dev; |
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phys_addr_t phybase = aus->phybase; |
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dma_cap_mask_t mask; |
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int err = 0; |
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dma_cap_zero(mask); |
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dma_cap_set(DMA_SLAVE, mask); |
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ctlr->dma_tx = dma_request_chan(dev, "tx"); |
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if (IS_ERR_OR_NULL(ctlr->dma_tx)) { |
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if (IS_ERR(ctlr->dma_tx)) { |
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err = PTR_ERR(ctlr->dma_tx); |
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goto at91_usart_spi_error_clear; |
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} |
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dev_dbg(dev, |
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"DMA TX channel not available, SPI unable to use DMA\n"); |
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err = -EBUSY; |
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goto at91_usart_spi_error_clear; |
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} |
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ctlr->dma_rx = dma_request_chan(dev, "rx"); |
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if (IS_ERR_OR_NULL(ctlr->dma_rx)) { |
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if (IS_ERR(ctlr->dma_rx)) { |
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err = PTR_ERR(ctlr->dma_rx); |
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goto at91_usart_spi_error; |
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} |
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dev_dbg(dev, |
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"DMA RX channel not available, SPI unable to use DMA\n"); |
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err = -EBUSY; |
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goto at91_usart_spi_error; |
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} |
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slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
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slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
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slave_config.dst_addr = (dma_addr_t)phybase + US_THR; |
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slave_config.src_addr = (dma_addr_t)phybase + US_RHR; |
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slave_config.src_maxburst = 1; |
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slave_config.dst_maxburst = 1; |
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slave_config.device_fc = false; |
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slave_config.direction = DMA_DEV_TO_MEM; |
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if (dmaengine_slave_config(ctlr->dma_rx, &slave_config)) { |
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dev_err(&ctlr->dev, |
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"failed to configure rx dma channel\n"); |
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err = -EINVAL; |
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goto at91_usart_spi_error; |
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} |
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slave_config.direction = DMA_MEM_TO_DEV; |
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if (dmaengine_slave_config(ctlr->dma_tx, &slave_config)) { |
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dev_err(&ctlr->dev, |
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"failed to configure tx dma channel\n"); |
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err = -EINVAL; |
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goto at91_usart_spi_error; |
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} |
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aus->use_dma = true; |
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return 0; |
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at91_usart_spi_error: |
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if (!IS_ERR_OR_NULL(ctlr->dma_tx)) |
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dma_release_channel(ctlr->dma_tx); |
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if (!IS_ERR_OR_NULL(ctlr->dma_rx)) |
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dma_release_channel(ctlr->dma_rx); |
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ctlr->dma_tx = NULL; |
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ctlr->dma_rx = NULL; |
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at91_usart_spi_error_clear: |
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return err; |
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} |
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static void at91_usart_spi_release_dma(struct spi_controller *ctlr) |
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{ |
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if (ctlr->dma_rx) |
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dma_release_channel(ctlr->dma_rx); |
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if (ctlr->dma_tx) |
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dma_release_channel(ctlr->dma_tx); |
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} |
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static void at91_usart_spi_stop_dma(struct spi_controller *ctlr) |
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{ |
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if (ctlr->dma_rx) |
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dmaengine_terminate_all(ctlr->dma_rx); |
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if (ctlr->dma_tx) |
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dmaengine_terminate_all(ctlr->dma_tx); |
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} |
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static int at91_usart_spi_dma_transfer(struct spi_controller *ctlr, |
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struct spi_transfer *xfer) |
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{ |
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
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struct dma_chan *rxchan = ctlr->dma_rx; |
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struct dma_chan *txchan = ctlr->dma_tx; |
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struct dma_async_tx_descriptor *rxdesc; |
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struct dma_async_tx_descriptor *txdesc; |
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dma_cookie_t cookie; |
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/* Disable RX interrupt */ |
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at91_usart_spi_writel(aus, IDR, US_IR_RXRDY); |
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rxdesc = dmaengine_prep_slave_sg(rxchan, |
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xfer->rx_sg.sgl, |
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xfer->rx_sg.nents, |
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DMA_DEV_TO_MEM, |
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DMA_PREP_INTERRUPT | |
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DMA_CTRL_ACK); |
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if (!rxdesc) |
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goto at91_usart_spi_err_dma; |
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txdesc = dmaengine_prep_slave_sg(txchan, |
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xfer->tx_sg.sgl, |
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xfer->tx_sg.nents, |
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DMA_MEM_TO_DEV, |
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DMA_PREP_INTERRUPT | |
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DMA_CTRL_ACK); |
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if (!txdesc) |
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goto at91_usart_spi_err_dma; |
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rxdesc->callback = dma_callback; |
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rxdesc->callback_param = ctlr; |
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cookie = rxdesc->tx_submit(rxdesc); |
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if (dma_submit_error(cookie)) |
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goto at91_usart_spi_err_dma; |
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cookie = txdesc->tx_submit(txdesc); |
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if (dma_submit_error(cookie)) |
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goto at91_usart_spi_err_dma; |
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rxchan->device->device_issue_pending(rxchan); |
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txchan->device->device_issue_pending(txchan); |
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return 0; |
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at91_usart_spi_err_dma: |
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/* Enable RX interrupt if something fails and fallback to PIO */ |
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at91_usart_spi_writel(aus, IER, US_IR_RXRDY); |
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at91_usart_spi_stop_dma(ctlr); |
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return -ENOMEM; |
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} |
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static unsigned long at91_usart_spi_dma_timeout(struct at91_usart_spi *aus) |
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{ |
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return wait_for_completion_timeout(&aus->xfer_completion, |
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US_DMA_TIMEOUT); |
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} |
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static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus) |
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{ |
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return aus->status & US_IR_TXRDY; |
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} |
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static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus) |
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{ |
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return aus->status & US_IR_RXRDY; |
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} |
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static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus) |
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{ |
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return aus->status & US_IR_OVRE; |
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} |
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static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus) |
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{ |
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aus->status = at91_usart_spi_readl(aus, CSR); |
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return aus->status; |
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} |
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static inline void at91_usart_spi_tx(struct at91_usart_spi *aus) |
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{ |
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unsigned int len = aus->current_transfer->len; |
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unsigned int remaining = aus->current_tx_remaining_bytes; |
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const u8 *tx_buf = aus->current_transfer->tx_buf; |
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if (!remaining) |
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return; |
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if (at91_usart_spi_tx_ready(aus)) { |
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at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]); |
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aus->current_tx_remaining_bytes--; |
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} |
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} |
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static inline void at91_usart_spi_rx(struct at91_usart_spi *aus) |
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{ |
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int len = aus->current_transfer->len; |
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int remaining = aus->current_rx_remaining_bytes; |
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u8 *rx_buf = aus->current_transfer->rx_buf; |
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if (!remaining) |
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return; |
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rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR); |
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aus->current_rx_remaining_bytes--; |
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} |
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static inline void |
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at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus, |
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struct spi_transfer *xfer) |
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{ |
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at91_usart_spi_writel(aus, BRGR, |
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DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz)); |
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} |
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static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id) |
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{ |
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struct spi_controller *controller = dev_id; |
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struct at91_usart_spi *aus = spi_master_get_devdata(controller); |
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spin_lock(&aus->lock); |
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at91_usart_spi_read_status(aus); |
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if (at91_usart_spi_check_overrun(aus)) { |
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aus->xfer_failed = true; |
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at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY); |
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spin_unlock(&aus->lock); |
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return IRQ_HANDLED; |
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} |
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if (at91_usart_spi_rx_ready(aus)) { |
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at91_usart_spi_rx(aus); |
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spin_unlock(&aus->lock); |
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return IRQ_HANDLED; |
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} |
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spin_unlock(&aus->lock); |
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return IRQ_NONE; |
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} |
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static int at91_usart_spi_setup(struct spi_device *spi) |
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{ |
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struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller); |
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u32 *ausd = spi->controller_state; |
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unsigned int mr = at91_usart_spi_readl(aus, MR); |
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if (spi->mode & SPI_CPOL) |
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mr |= US_MR_CPOL; |
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else |
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mr &= ~US_MR_CPOL; |
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if (spi->mode & SPI_CPHA) |
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mr |= US_MR_CPHA; |
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else |
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mr &= ~US_MR_CPHA; |
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if (spi->mode & SPI_LOOP) |
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mr |= US_MR_LOOP; |
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else |
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mr &= ~US_MR_LOOP; |
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if (!ausd) { |
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ausd = kzalloc(sizeof(*ausd), GFP_KERNEL); |
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if (!ausd) |
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return -ENOMEM; |
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spi->controller_state = ausd; |
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} |
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*ausd = mr; |
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dev_dbg(&spi->dev, |
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"setup: bpw %u mode 0x%x -> mr %d %08x\n", |
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spi->bits_per_word, spi->mode, spi->chip_select, mr); |
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return 0; |
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} |
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static int at91_usart_spi_transfer_one(struct spi_controller *ctlr, |
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struct spi_device *spi, |
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struct spi_transfer *xfer) |
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{ |
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
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unsigned long dma_timeout = 0; |
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int ret = 0; |
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at91_usart_spi_set_xfer_speed(aus, xfer); |
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aus->xfer_failed = false; |
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aus->current_transfer = xfer; |
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aus->current_tx_remaining_bytes = xfer->len; |
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aus->current_rx_remaining_bytes = xfer->len; |
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while ((aus->current_tx_remaining_bytes || |
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aus->current_rx_remaining_bytes) && !aus->xfer_failed) { |
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reinit_completion(&aus->xfer_completion); |
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if (at91_usart_spi_can_dma(ctlr, spi, xfer) && |
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!ret) { |
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ret = at91_usart_spi_dma_transfer(ctlr, xfer); |
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if (ret) |
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continue; |
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dma_timeout = at91_usart_spi_dma_timeout(aus); |
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if (WARN_ON(dma_timeout == 0)) { |
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dev_err(&spi->dev, "DMA transfer timeout\n"); |
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return -EIO; |
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} |
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aus->current_tx_remaining_bytes = 0; |
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} else { |
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at91_usart_spi_read_status(aus); |
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at91_usart_spi_tx(aus); |
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} |
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cpu_relax(); |
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} |
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if (aus->xfer_failed) { |
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dev_err(aus->dev, "Overrun!\n"); |
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return -EIO; |
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} |
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return 0; |
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} |
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static int at91_usart_spi_prepare_message(struct spi_controller *ctlr, |
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struct spi_message *message) |
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{ |
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
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struct spi_device *spi = message->spi; |
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u32 *ausd = spi->controller_state; |
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at91_usart_spi_writel(aus, CR, US_ENABLE); |
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at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS); |
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at91_usart_spi_writel(aus, MR, *ausd); |
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return 0; |
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} |
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static int at91_usart_spi_unprepare_message(struct spi_controller *ctlr, |
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struct spi_message *message) |
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{ |
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
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at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE); |
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at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS); |
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return 0; |
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} |
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static void at91_usart_spi_cleanup(struct spi_device *spi) |
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{ |
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struct at91_usart_spi_device *ausd = spi->controller_state; |
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spi->controller_state = NULL; |
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kfree(ausd); |
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} |
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static void at91_usart_spi_init(struct at91_usart_spi *aus) |
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{ |
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at91_usart_spi_writel(aus, MR, US_INIT); |
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at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE); |
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} |
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static int at91_usart_gpio_setup(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.parent->of_node; |
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int i; |
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int ret; |
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int nb; |
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if (!np) |
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return -EINVAL; |
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nb = of_gpio_named_count(np, "cs-gpios"); |
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for (i = 0; i < nb; i++) { |
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int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
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if (cs_gpio < 0) |
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return cs_gpio; |
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if (gpio_is_valid(cs_gpio)) { |
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ret = devm_gpio_request_one(&pdev->dev, cs_gpio, |
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GPIOF_DIR_OUT, |
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dev_name(&pdev->dev)); |
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if (ret) |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static int at91_usart_spi_probe(struct platform_device *pdev) |
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{ |
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struct resource *regs; |
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struct spi_controller *controller; |
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struct at91_usart_spi *aus; |
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struct clk *clk; |
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int irq; |
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int ret; |
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regs = platform_get_resource(to_platform_device(pdev->dev.parent), |
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IORESOURCE_MEM, 0); |
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if (!regs) |
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return -EINVAL; |
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irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0); |
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if (irq < 0) |
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return irq; |
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clk = devm_clk_get(pdev->dev.parent, "usart"); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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ret = -ENOMEM; |
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controller = spi_alloc_master(&pdev->dev, sizeof(*aus)); |
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if (!controller) |
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goto at91_usart_spi_probe_fail; |
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ret = at91_usart_gpio_setup(pdev); |
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if (ret) |
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goto at91_usart_spi_probe_fail; |
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controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; |
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controller->dev.of_node = pdev->dev.parent->of_node; |
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controller->bits_per_word_mask = SPI_BPW_MASK(8); |
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controller->setup = at91_usart_spi_setup; |
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controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; |
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controller->transfer_one = at91_usart_spi_transfer_one; |
|
controller->prepare_message = at91_usart_spi_prepare_message; |
|
controller->unprepare_message = at91_usart_spi_unprepare_message; |
|
controller->can_dma = at91_usart_spi_can_dma; |
|
controller->cleanup = at91_usart_spi_cleanup; |
|
controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk), |
|
US_MIN_CLK_DIV); |
|
controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk), |
|
US_MAX_CLK_DIV); |
|
platform_set_drvdata(pdev, controller); |
|
|
|
aus = spi_master_get_devdata(controller); |
|
|
|
aus->dev = &pdev->dev; |
|
aus->regs = devm_ioremap_resource(&pdev->dev, regs); |
|
if (IS_ERR(aus->regs)) { |
|
ret = PTR_ERR(aus->regs); |
|
goto at91_usart_spi_probe_fail; |
|
} |
|
|
|
aus->irq = irq; |
|
aus->clk = clk; |
|
|
|
ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0, |
|
dev_name(&pdev->dev), controller); |
|
if (ret) |
|
goto at91_usart_spi_probe_fail; |
|
|
|
ret = clk_prepare_enable(clk); |
|
if (ret) |
|
goto at91_usart_spi_probe_fail; |
|
|
|
aus->spi_clk = clk_get_rate(clk); |
|
at91_usart_spi_init(aus); |
|
|
|
aus->phybase = regs->start; |
|
|
|
aus->mpdev = to_platform_device(pdev->dev.parent); |
|
|
|
ret = at91_usart_spi_configure_dma(controller, aus); |
|
if (ret) |
|
goto at91_usart_fail_dma; |
|
|
|
spin_lock_init(&aus->lock); |
|
init_completion(&aus->xfer_completion); |
|
|
|
ret = devm_spi_register_master(&pdev->dev, controller); |
|
if (ret) |
|
goto at91_usart_fail_register_master; |
|
|
|
dev_info(&pdev->dev, |
|
"AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n", |
|
at91_usart_spi_readl(aus, VERSION), |
|
®s->start, irq); |
|
|
|
return 0; |
|
|
|
at91_usart_fail_register_master: |
|
at91_usart_spi_release_dma(controller); |
|
at91_usart_fail_dma: |
|
clk_disable_unprepare(clk); |
|
at91_usart_spi_probe_fail: |
|
spi_master_put(controller); |
|
return ret; |
|
} |
|
|
|
__maybe_unused static int at91_usart_spi_runtime_suspend(struct device *dev) |
|
{ |
|
struct spi_controller *ctlr = dev_get_drvdata(dev); |
|
struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
|
|
|
clk_disable_unprepare(aus->clk); |
|
pinctrl_pm_select_sleep_state(dev); |
|
|
|
return 0; |
|
} |
|
|
|
__maybe_unused static int at91_usart_spi_runtime_resume(struct device *dev) |
|
{ |
|
struct spi_controller *ctrl = dev_get_drvdata(dev); |
|
struct at91_usart_spi *aus = spi_master_get_devdata(ctrl); |
|
|
|
pinctrl_pm_select_default_state(dev); |
|
|
|
return clk_prepare_enable(aus->clk); |
|
} |
|
|
|
__maybe_unused static int at91_usart_spi_suspend(struct device *dev) |
|
{ |
|
struct spi_controller *ctrl = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = spi_controller_suspend(ctrl); |
|
if (ret) |
|
return ret; |
|
|
|
if (!pm_runtime_suspended(dev)) |
|
at91_usart_spi_runtime_suspend(dev); |
|
|
|
return 0; |
|
} |
|
|
|
__maybe_unused static int at91_usart_spi_resume(struct device *dev) |
|
{ |
|
struct spi_controller *ctrl = dev_get_drvdata(dev); |
|
struct at91_usart_spi *aus = spi_master_get_devdata(ctrl); |
|
int ret; |
|
|
|
if (!pm_runtime_suspended(dev)) { |
|
ret = at91_usart_spi_runtime_resume(dev); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
at91_usart_spi_init(aus); |
|
|
|
return spi_controller_resume(ctrl); |
|
} |
|
|
|
static int at91_usart_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_controller *ctlr = platform_get_drvdata(pdev); |
|
struct at91_usart_spi *aus = spi_master_get_devdata(ctlr); |
|
|
|
at91_usart_spi_release_dma(ctlr); |
|
clk_disable_unprepare(aus->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops at91_usart_spi_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(at91_usart_spi_suspend, at91_usart_spi_resume) |
|
SET_RUNTIME_PM_OPS(at91_usart_spi_runtime_suspend, |
|
at91_usart_spi_runtime_resume, NULL) |
|
}; |
|
|
|
static struct platform_driver at91_usart_spi_driver = { |
|
.driver = { |
|
.name = "at91_usart_spi", |
|
.pm = &at91_usart_spi_pm_ops, |
|
}, |
|
.probe = at91_usart_spi_probe, |
|
.remove = at91_usart_spi_remove, |
|
}; |
|
|
|
module_platform_driver(at91_usart_spi_driver); |
|
|
|
MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver"); |
|
MODULE_AUTHOR("Radu Pirea <[email protected]>"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:at91_usart_spi");
|
|
|