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935 lines
24 KiB
935 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Marvell Armada-3700 SPI controller driver |
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* |
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* Copyright (C) 2016 Marvell Ltd. |
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* |
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* Author: Wilson Ding <[email protected]> |
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* Author: Romain Perier <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_device.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/spi/spi.h> |
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#define DRIVER_NAME "armada_3700_spi" |
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#define A3700_SPI_MAX_SPEED_HZ 100000000 |
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#define A3700_SPI_MAX_PRESCALE 30 |
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#define A3700_SPI_TIMEOUT 10 |
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/* SPI Register Offest */ |
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#define A3700_SPI_IF_CTRL_REG 0x00 |
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#define A3700_SPI_IF_CFG_REG 0x04 |
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#define A3700_SPI_DATA_OUT_REG 0x08 |
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#define A3700_SPI_DATA_IN_REG 0x0C |
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#define A3700_SPI_IF_INST_REG 0x10 |
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#define A3700_SPI_IF_ADDR_REG 0x14 |
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#define A3700_SPI_IF_RMODE_REG 0x18 |
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#define A3700_SPI_IF_HDR_CNT_REG 0x1C |
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#define A3700_SPI_IF_DIN_CNT_REG 0x20 |
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#define A3700_SPI_IF_TIME_REG 0x24 |
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#define A3700_SPI_INT_STAT_REG 0x28 |
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#define A3700_SPI_INT_MASK_REG 0x2C |
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/* A3700_SPI_IF_CTRL_REG */ |
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#define A3700_SPI_EN BIT(16) |
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#define A3700_SPI_ADDR_NOT_CONFIG BIT(12) |
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#define A3700_SPI_WFIFO_OVERFLOW BIT(11) |
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#define A3700_SPI_WFIFO_UNDERFLOW BIT(10) |
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#define A3700_SPI_RFIFO_OVERFLOW BIT(9) |
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#define A3700_SPI_RFIFO_UNDERFLOW BIT(8) |
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#define A3700_SPI_WFIFO_FULL BIT(7) |
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#define A3700_SPI_WFIFO_EMPTY BIT(6) |
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#define A3700_SPI_RFIFO_FULL BIT(5) |
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#define A3700_SPI_RFIFO_EMPTY BIT(4) |
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#define A3700_SPI_WFIFO_RDY BIT(3) |
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#define A3700_SPI_RFIFO_RDY BIT(2) |
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#define A3700_SPI_XFER_RDY BIT(1) |
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#define A3700_SPI_XFER_DONE BIT(0) |
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/* A3700_SPI_IF_CFG_REG */ |
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#define A3700_SPI_WFIFO_THRS BIT(28) |
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#define A3700_SPI_RFIFO_THRS BIT(24) |
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#define A3700_SPI_AUTO_CS BIT(20) |
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#define A3700_SPI_DMA_RD_EN BIT(18) |
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#define A3700_SPI_FIFO_MODE BIT(17) |
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#define A3700_SPI_SRST BIT(16) |
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#define A3700_SPI_XFER_START BIT(15) |
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#define A3700_SPI_XFER_STOP BIT(14) |
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#define A3700_SPI_INST_PIN BIT(13) |
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#define A3700_SPI_ADDR_PIN BIT(12) |
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#define A3700_SPI_DATA_PIN1 BIT(11) |
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#define A3700_SPI_DATA_PIN0 BIT(10) |
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#define A3700_SPI_FIFO_FLUSH BIT(9) |
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#define A3700_SPI_RW_EN BIT(8) |
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#define A3700_SPI_CLK_POL BIT(7) |
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#define A3700_SPI_CLK_PHA BIT(6) |
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#define A3700_SPI_BYTE_LEN BIT(5) |
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#define A3700_SPI_CLK_PRESCALE BIT(0) |
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#define A3700_SPI_CLK_PRESCALE_MASK (0x1f) |
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#define A3700_SPI_CLK_EVEN_OFFS (0x10) |
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#define A3700_SPI_WFIFO_THRS_BIT 28 |
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#define A3700_SPI_RFIFO_THRS_BIT 24 |
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#define A3700_SPI_FIFO_THRS_MASK 0x7 |
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#define A3700_SPI_DATA_PIN_MASK 0x3 |
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/* A3700_SPI_IF_HDR_CNT_REG */ |
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#define A3700_SPI_DUMMY_CNT_BIT 12 |
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#define A3700_SPI_DUMMY_CNT_MASK 0x7 |
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#define A3700_SPI_RMODE_CNT_BIT 8 |
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#define A3700_SPI_RMODE_CNT_MASK 0x3 |
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#define A3700_SPI_ADDR_CNT_BIT 4 |
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#define A3700_SPI_ADDR_CNT_MASK 0x7 |
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#define A3700_SPI_INSTR_CNT_BIT 0 |
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#define A3700_SPI_INSTR_CNT_MASK 0x3 |
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/* A3700_SPI_IF_TIME_REG */ |
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#define A3700_SPI_CLK_CAPT_EDGE BIT(7) |
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struct a3700_spi { |
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struct spi_master *master; |
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void __iomem *base; |
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struct clk *clk; |
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unsigned int irq; |
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unsigned int flags; |
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bool xmit_data; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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size_t buf_len; |
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u8 byte_len; |
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u32 wait_mask; |
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struct completion done; |
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}; |
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static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) |
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{ |
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return readl(a3700_spi->base + offset); |
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} |
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static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) |
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{ |
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writel(data, a3700_spi->base + offset); |
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} |
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static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~A3700_SPI_AUTO_CS; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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val |= (A3700_SPI_EN << cs); |
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spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); |
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} |
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static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, |
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unsigned int cs) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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val &= ~(A3700_SPI_EN << cs); |
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spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); |
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} |
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static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, |
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unsigned int pin_mode, bool receiving) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); |
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val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); |
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switch (pin_mode) { |
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case SPI_NBITS_SINGLE: |
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break; |
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case SPI_NBITS_DUAL: |
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val |= A3700_SPI_DATA_PIN0; |
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break; |
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case SPI_NBITS_QUAD: |
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val |= A3700_SPI_DATA_PIN1; |
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/* RX during address reception uses 4-pin */ |
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if (receiving) |
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val |= A3700_SPI_ADDR_PIN; |
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break; |
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default: |
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dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); |
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return -EINVAL; |
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} |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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return 0; |
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} |
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static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (enable) |
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val |= A3700_SPI_FIFO_MODE; |
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else |
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val &= ~A3700_SPI_FIFO_MODE; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, |
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unsigned int mode_bits) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (mode_bits & SPI_CPOL) |
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val |= A3700_SPI_CLK_POL; |
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else |
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val &= ~A3700_SPI_CLK_POL; |
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if (mode_bits & SPI_CPHA) |
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val |= A3700_SPI_CLK_PHA; |
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else |
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val &= ~A3700_SPI_CLK_PHA; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, |
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unsigned int speed_hz) |
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{ |
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u32 val; |
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u32 prescale; |
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prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); |
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/* For prescaler values over 15, we can only set it by steps of 2. |
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* Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to |
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* 30. We only use this range from 16 to 30. |
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*/ |
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if (prescale > 15) |
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prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2); |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val = val & ~A3700_SPI_CLK_PRESCALE_MASK; |
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val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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if (prescale <= 2) { |
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val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); |
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val |= A3700_SPI_CLK_CAPT_EDGE; |
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spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); |
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} |
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} |
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static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (len == 4) |
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val |= A3700_SPI_BYTE_LEN; |
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else |
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val &= ~A3700_SPI_BYTE_LEN; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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a3700_spi->byte_len = len; |
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} |
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static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) |
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{ |
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int timeout = A3700_SPI_TIMEOUT; |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val |= A3700_SPI_FIFO_FLUSH; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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while (--timeout) { |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (!(val & A3700_SPI_FIFO_FLUSH)) |
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return 0; |
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udelay(1); |
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} |
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return -ETIMEDOUT; |
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} |
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static void a3700_spi_init(struct a3700_spi *a3700_spi) |
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{ |
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struct spi_master *master = a3700_spi->master; |
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u32 val; |
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int i; |
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/* Reset SPI unit */ |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val |= A3700_SPI_SRST; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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udelay(A3700_SPI_TIMEOUT); |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~A3700_SPI_SRST; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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/* Disable AUTO_CS and deactivate all chip-selects */ |
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a3700_spi_auto_cs_unset(a3700_spi); |
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for (i = 0; i < master->num_chipselect; i++) |
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a3700_spi_deactivate_cs(a3700_spi, i); |
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/* Enable FIFO mode */ |
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a3700_spi_fifo_mode_set(a3700_spi, true); |
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/* Set SPI mode */ |
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a3700_spi_mode_set(a3700_spi, master->mode_bits); |
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/* Reset counters */ |
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spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); |
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/* Mask the interrupts and clear cause bits */ |
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); |
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} |
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static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) |
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{ |
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struct spi_master *master = dev_id; |
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struct a3700_spi *a3700_spi; |
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u32 cause; |
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a3700_spi = spi_master_get_devdata(master); |
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/* Get interrupt causes */ |
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cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); |
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if (!cause || !(a3700_spi->wait_mask & cause)) |
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return IRQ_NONE; |
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/* mask and acknowledge the SPI interrupts */ |
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); |
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/* Wake up the transfer */ |
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complete(&a3700_spi->done); |
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return IRQ_HANDLED; |
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} |
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static bool a3700_spi_wait_completion(struct spi_device *spi) |
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{ |
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struct a3700_spi *a3700_spi; |
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unsigned int timeout; |
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unsigned int ctrl_reg; |
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unsigned long timeout_jiffies; |
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a3700_spi = spi_master_get_devdata(spi->master); |
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/* SPI interrupt is edge-triggered, which means an interrupt will |
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* be generated only when detecting a specific status bit changed |
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* from '0' to '1'. So when we start waiting for a interrupt, we |
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* need to check status bit in control reg first, if it is already 1, |
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* then we do not need to wait for interrupt |
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*/ |
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ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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if (a3700_spi->wait_mask & ctrl_reg) |
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return true; |
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reinit_completion(&a3700_spi->done); |
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, |
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a3700_spi->wait_mask); |
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timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); |
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timeout = wait_for_completion_timeout(&a3700_spi->done, |
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timeout_jiffies); |
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a3700_spi->wait_mask = 0; |
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if (timeout) |
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return true; |
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/* there might be the case that right after we checked the |
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* status bits in this routine and before start to wait for |
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* interrupt by wait_for_completion_timeout, the interrupt |
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* happens, to avoid missing it we need to double check |
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* status bits in control reg, if it is already 1, then |
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* consider that we have the interrupt successfully and |
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* return true. |
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*/ |
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ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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if (a3700_spi->wait_mask & ctrl_reg) |
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return true; |
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); |
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/* Timeout was reached */ |
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return false; |
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} |
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static bool a3700_spi_transfer_wait(struct spi_device *spi, |
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unsigned int bit_mask) |
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{ |
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struct a3700_spi *a3700_spi; |
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a3700_spi = spi_master_get_devdata(spi->master); |
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a3700_spi->wait_mask = bit_mask; |
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return a3700_spi_wait_completion(spi); |
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} |
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static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, |
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unsigned int bytes) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); |
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val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; |
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val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); |
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val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_transfer_setup(struct spi_device *spi, |
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struct spi_transfer *xfer) |
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{ |
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struct a3700_spi *a3700_spi; |
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a3700_spi = spi_master_get_devdata(spi->master); |
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a3700_spi_clock_set(a3700_spi, xfer->speed_hz); |
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/* Use 4 bytes long transfers. Each transfer method has its way to deal |
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* with the remaining bytes for non 4-bytes aligned transfers. |
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*/ |
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a3700_spi_bytelen_set(a3700_spi, 4); |
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|
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/* Initialize the working buffers */ |
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a3700_spi->tx_buf = xfer->tx_buf; |
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a3700_spi->rx_buf = xfer->rx_buf; |
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a3700_spi->buf_len = xfer->len; |
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} |
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static void a3700_spi_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); |
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|
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if (!enable) |
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a3700_spi_activate_cs(a3700_spi, spi->chip_select); |
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else |
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a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); |
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} |
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static void a3700_spi_header_set(struct a3700_spi *a3700_spi) |
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{ |
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unsigned int addr_cnt; |
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u32 val = 0; |
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|
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/* Clear the header registers */ |
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spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); |
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|
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/* Set header counters */ |
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if (a3700_spi->tx_buf) { |
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/* |
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* when tx data is not 4 bytes aligned, there will be unexpected |
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* bytes out of SPI output register, since it always shifts out |
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* as whole 4 bytes. This might cause incorrect transaction with |
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* some devices. To avoid that, use SPI header count feature to |
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* transfer up to 3 bytes of data first, and then make the rest |
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* of data 4-byte aligned. |
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*/ |
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addr_cnt = a3700_spi->buf_len % 4; |
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if (addr_cnt) { |
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val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) |
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<< A3700_SPI_ADDR_CNT_BIT; |
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spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); |
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|
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/* Update the buffer length to be transferred */ |
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a3700_spi->buf_len -= addr_cnt; |
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|
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/* transfer 1~3 bytes through address count */ |
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val = 0; |
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while (addr_cnt--) { |
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val = (val << 8) | a3700_spi->tx_buf[0]; |
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a3700_spi->tx_buf++; |
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} |
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spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); |
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} |
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} |
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} |
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|
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static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) |
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{ |
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u32 val; |
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|
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val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
|
return (val & A3700_SPI_WFIFO_FULL); |
|
} |
|
|
|
static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) |
|
{ |
|
u32 val; |
|
|
|
while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { |
|
val = *(u32 *)a3700_spi->tx_buf; |
|
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); |
|
a3700_spi->buf_len -= 4; |
|
a3700_spi->tx_buf += 4; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) |
|
{ |
|
u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
|
|
|
return (val & A3700_SPI_RFIFO_EMPTY); |
|
} |
|
|
|
static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) |
|
{ |
|
u32 val; |
|
|
|
while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { |
|
val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); |
|
if (a3700_spi->buf_len >= 4) { |
|
|
|
memcpy(a3700_spi->rx_buf, &val, 4); |
|
|
|
a3700_spi->buf_len -= 4; |
|
a3700_spi->rx_buf += 4; |
|
} else { |
|
/* |
|
* When remain bytes is not larger than 4, we should |
|
* avoid memory overwriting and just write the left rx |
|
* buffer bytes. |
|
*/ |
|
while (a3700_spi->buf_len) { |
|
*a3700_spi->rx_buf = val & 0xff; |
|
val >>= 8; |
|
|
|
a3700_spi->buf_len--; |
|
a3700_spi->rx_buf++; |
|
} |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) |
|
{ |
|
int timeout = A3700_SPI_TIMEOUT; |
|
u32 val; |
|
|
|
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
|
val |= A3700_SPI_XFER_STOP; |
|
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
|
|
|
while (--timeout) { |
|
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
|
if (!(val & A3700_SPI_XFER_START)) |
|
break; |
|
udelay(1); |
|
} |
|
|
|
a3700_spi_fifo_flush(a3700_spi); |
|
|
|
val &= ~A3700_SPI_XFER_STOP; |
|
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
|
} |
|
|
|
static int a3700_spi_prepare_message(struct spi_master *master, |
|
struct spi_message *message) |
|
{ |
|
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
|
struct spi_device *spi = message->spi; |
|
int ret; |
|
|
|
ret = clk_enable(a3700_spi->clk); |
|
if (ret) { |
|
dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); |
|
return ret; |
|
} |
|
|
|
/* Flush the FIFOs */ |
|
ret = a3700_spi_fifo_flush(a3700_spi); |
|
if (ret) |
|
return ret; |
|
|
|
a3700_spi_mode_set(a3700_spi, spi->mode); |
|
|
|
return 0; |
|
} |
|
|
|
static int a3700_spi_transfer_one_fifo(struct spi_master *master, |
|
struct spi_device *spi, |
|
struct spi_transfer *xfer) |
|
{ |
|
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
|
int ret = 0, timeout = A3700_SPI_TIMEOUT; |
|
unsigned int nbits = 0, byte_len; |
|
u32 val; |
|
|
|
/* Make sure we use FIFO mode */ |
|
a3700_spi_fifo_mode_set(a3700_spi, true); |
|
|
|
/* Configure FIFO thresholds */ |
|
byte_len = xfer->bits_per_word >> 3; |
|
a3700_spi_fifo_thres_set(a3700_spi, byte_len); |
|
|
|
if (xfer->tx_buf) |
|
nbits = xfer->tx_nbits; |
|
else if (xfer->rx_buf) |
|
nbits = xfer->rx_nbits; |
|
|
|
a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); |
|
|
|
/* Flush the FIFOs */ |
|
a3700_spi_fifo_flush(a3700_spi); |
|
|
|
/* Transfer first bytes of data when buffer is not 4-byte aligned */ |
|
a3700_spi_header_set(a3700_spi); |
|
|
|
if (xfer->rx_buf) { |
|
/* Clear WFIFO, since it's last 2 bytes are shifted out during |
|
* a read operation |
|
*/ |
|
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0); |
|
|
|
/* Set read data length */ |
|
spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, |
|
a3700_spi->buf_len); |
|
/* Start READ transfer */ |
|
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
|
val &= ~A3700_SPI_RW_EN; |
|
val |= A3700_SPI_XFER_START; |
|
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
|
} else if (xfer->tx_buf) { |
|
/* Start Write transfer */ |
|
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
|
val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); |
|
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
|
|
|
/* |
|
* If there are data to be written to the SPI device, xmit_data |
|
* flag is set true; otherwise the instruction in SPI_INSTR does |
|
* not require data to be written to the SPI device, then |
|
* xmit_data flag is set false. |
|
*/ |
|
a3700_spi->xmit_data = (a3700_spi->buf_len != 0); |
|
} |
|
|
|
while (a3700_spi->buf_len) { |
|
if (a3700_spi->tx_buf) { |
|
/* Wait wfifo ready */ |
|
if (!a3700_spi_transfer_wait(spi, |
|
A3700_SPI_WFIFO_RDY)) { |
|
dev_err(&spi->dev, |
|
"wait wfifo ready timed out\n"); |
|
ret = -ETIMEDOUT; |
|
goto error; |
|
} |
|
/* Fill up the wfifo */ |
|
ret = a3700_spi_fifo_write(a3700_spi); |
|
if (ret) |
|
goto error; |
|
} else if (a3700_spi->rx_buf) { |
|
/* Wait rfifo ready */ |
|
if (!a3700_spi_transfer_wait(spi, |
|
A3700_SPI_RFIFO_RDY)) { |
|
dev_err(&spi->dev, |
|
"wait rfifo ready timed out\n"); |
|
ret = -ETIMEDOUT; |
|
goto error; |
|
} |
|
/* Drain out the rfifo */ |
|
ret = a3700_spi_fifo_read(a3700_spi); |
|
if (ret) |
|
goto error; |
|
} |
|
} |
|
|
|
/* |
|
* Stop a write transfer in fifo mode: |
|
* - wait all the bytes in wfifo to be shifted out |
|
* - set XFER_STOP bit |
|
* - wait XFER_START bit clear |
|
* - clear XFER_STOP bit |
|
* Stop a read transfer in fifo mode: |
|
* - the hardware is to reset the XFER_START bit |
|
* after the number of bytes indicated in DIN_CNT |
|
* register |
|
* - just wait XFER_START bit clear |
|
*/ |
|
if (a3700_spi->tx_buf) { |
|
if (a3700_spi->xmit_data) { |
|
/* |
|
* If there are data written to the SPI device, wait |
|
* until SPI_WFIFO_EMPTY is 1 to wait for all data to |
|
* transfer out of write FIFO. |
|
*/ |
|
if (!a3700_spi_transfer_wait(spi, |
|
A3700_SPI_WFIFO_EMPTY)) { |
|
dev_err(&spi->dev, "wait wfifo empty timed out\n"); |
|
return -ETIMEDOUT; |
|
} |
|
} |
|
|
|
if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { |
|
dev_err(&spi->dev, "wait xfer ready timed out\n"); |
|
return -ETIMEDOUT; |
|
} |
|
|
|
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
|
val |= A3700_SPI_XFER_STOP; |
|
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
|
} |
|
|
|
while (--timeout) { |
|
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
|
if (!(val & A3700_SPI_XFER_START)) |
|
break; |
|
udelay(1); |
|
} |
|
|
|
if (timeout == 0) { |
|
dev_err(&spi->dev, "wait transfer start clear timed out\n"); |
|
ret = -ETIMEDOUT; |
|
goto error; |
|
} |
|
|
|
val &= ~A3700_SPI_XFER_STOP; |
|
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
|
goto out; |
|
|
|
error: |
|
a3700_spi_transfer_abort_fifo(a3700_spi); |
|
out: |
|
spi_finalize_current_transfer(master); |
|
|
|
return ret; |
|
} |
|
|
|
static int a3700_spi_transfer_one_full_duplex(struct spi_master *master, |
|
struct spi_device *spi, |
|
struct spi_transfer *xfer) |
|
{ |
|
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
|
u32 val; |
|
|
|
/* Disable FIFO mode */ |
|
a3700_spi_fifo_mode_set(a3700_spi, false); |
|
|
|
while (a3700_spi->buf_len) { |
|
|
|
/* When we have less than 4 bytes to transfer, switch to 1 byte |
|
* mode. This is reset after each transfer |
|
*/ |
|
if (a3700_spi->buf_len < 4) |
|
a3700_spi_bytelen_set(a3700_spi, 1); |
|
|
|
if (a3700_spi->byte_len == 1) |
|
val = *a3700_spi->tx_buf; |
|
else |
|
val = *(u32 *)a3700_spi->tx_buf; |
|
|
|
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); |
|
|
|
/* Wait for all the data to be shifted in / out */ |
|
while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) & |
|
A3700_SPI_XFER_DONE)) |
|
cpu_relax(); |
|
|
|
val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); |
|
|
|
memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); |
|
|
|
a3700_spi->buf_len -= a3700_spi->byte_len; |
|
a3700_spi->tx_buf += a3700_spi->byte_len; |
|
a3700_spi->rx_buf += a3700_spi->byte_len; |
|
|
|
} |
|
|
|
spi_finalize_current_transfer(master); |
|
|
|
return 0; |
|
} |
|
|
|
static int a3700_spi_transfer_one(struct spi_master *master, |
|
struct spi_device *spi, |
|
struct spi_transfer *xfer) |
|
{ |
|
a3700_spi_transfer_setup(spi, xfer); |
|
|
|
if (xfer->tx_buf && xfer->rx_buf) |
|
return a3700_spi_transfer_one_full_duplex(master, spi, xfer); |
|
|
|
return a3700_spi_transfer_one_fifo(master, spi, xfer); |
|
} |
|
|
|
static int a3700_spi_unprepare_message(struct spi_master *master, |
|
struct spi_message *message) |
|
{ |
|
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
|
|
|
clk_disable(a3700_spi->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id a3700_spi_dt_ids[] = { |
|
{ .compatible = "marvell,armada-3700-spi", .data = NULL }, |
|
{}, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); |
|
|
|
static int a3700_spi_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct device_node *of_node = dev->of_node; |
|
struct spi_master *master; |
|
struct a3700_spi *spi; |
|
u32 num_cs = 0; |
|
int irq, ret = 0; |
|
|
|
master = spi_alloc_master(dev, sizeof(*spi)); |
|
if (!master) { |
|
dev_err(dev, "master allocation failed\n"); |
|
ret = -ENOMEM; |
|
goto out; |
|
} |
|
|
|
if (of_property_read_u32(of_node, "num-cs", &num_cs)) { |
|
dev_err(dev, "could not find num-cs\n"); |
|
ret = -ENXIO; |
|
goto error; |
|
} |
|
|
|
master->bus_num = pdev->id; |
|
master->dev.of_node = of_node; |
|
master->mode_bits = SPI_MODE_3; |
|
master->num_chipselect = num_cs; |
|
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); |
|
master->prepare_message = a3700_spi_prepare_message; |
|
master->transfer_one = a3700_spi_transfer_one; |
|
master->unprepare_message = a3700_spi_unprepare_message; |
|
master->set_cs = a3700_spi_set_cs; |
|
master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | |
|
SPI_RX_QUAD | SPI_TX_QUAD); |
|
|
|
platform_set_drvdata(pdev, master); |
|
|
|
spi = spi_master_get_devdata(master); |
|
|
|
spi->master = master; |
|
|
|
spi->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(spi->base)) { |
|
ret = PTR_ERR(spi->base); |
|
goto error; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
ret = -ENXIO; |
|
goto error; |
|
} |
|
spi->irq = irq; |
|
|
|
init_completion(&spi->done); |
|
|
|
spi->clk = devm_clk_get(dev, NULL); |
|
if (IS_ERR(spi->clk)) { |
|
dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); |
|
goto error; |
|
} |
|
|
|
ret = clk_prepare(spi->clk); |
|
if (ret) { |
|
dev_err(dev, "could not prepare clk: %d\n", ret); |
|
goto error; |
|
} |
|
|
|
master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ, |
|
clk_get_rate(spi->clk)); |
|
master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk), |
|
A3700_SPI_MAX_PRESCALE); |
|
|
|
a3700_spi_init(spi); |
|
|
|
ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, |
|
dev_name(dev), master); |
|
if (ret) { |
|
dev_err(dev, "could not request IRQ: %d\n", ret); |
|
goto error_clk; |
|
} |
|
|
|
ret = devm_spi_register_master(dev, master); |
|
if (ret) { |
|
dev_err(dev, "Failed to register master\n"); |
|
goto error_clk; |
|
} |
|
|
|
return 0; |
|
|
|
error_clk: |
|
clk_disable_unprepare(spi->clk); |
|
error: |
|
spi_master_put(master); |
|
out: |
|
return ret; |
|
} |
|
|
|
static int a3700_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master = platform_get_drvdata(pdev); |
|
struct a3700_spi *spi = spi_master_get_devdata(master); |
|
|
|
clk_unprepare(spi->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver a3700_spi_driver = { |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.of_match_table = of_match_ptr(a3700_spi_dt_ids), |
|
}, |
|
.probe = a3700_spi_probe, |
|
.remove = a3700_spi_remove, |
|
}; |
|
|
|
module_platform_driver(a3700_spi_driver); |
|
|
|
MODULE_DESCRIPTION("Armada-3700 SPI driver"); |
|
MODULE_AUTHOR("Wilson Ding <[email protected]>"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
|