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1153 lines
32 KiB
1153 lines
32 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
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*/ |
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|
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/pinctrl/pinconf-generic.h> |
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#include <linux/pinctrl/pinconf.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> |
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#include "../core.h" |
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#include "../pinctrl-utils.h" |
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#define PMIC_GPIO_ADDRESS_RANGE 0x100 |
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/* type and subtype registers base address offsets */ |
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#define PMIC_GPIO_REG_TYPE 0x4 |
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#define PMIC_GPIO_REG_SUBTYPE 0x5 |
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|
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/* GPIO peripheral type and subtype out_values */ |
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#define PMIC_GPIO_TYPE 0x10 |
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#define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 |
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#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 |
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#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 |
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#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd |
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#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 |
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#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 |
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#define PMIC_MPP_REG_RT_STS 0x10 |
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#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 |
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|
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/* control register base address offsets */ |
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#define PMIC_GPIO_REG_MODE_CTL 0x40 |
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#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 |
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#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 |
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#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 |
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#define PMIC_GPIO_REG_DIG_IN_CTL 0x43 |
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#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 |
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#define PMIC_GPIO_REG_EN_CTL 0x46 |
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#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A |
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/* PMIC_GPIO_REG_MODE_CTL */ |
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#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 |
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#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 |
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#define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 |
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#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 |
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#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 |
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#define PMIC_GPIO_MODE_DIGITAL_INPUT 0 |
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#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 |
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#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 |
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#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 |
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#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 |
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|
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/* PMIC_GPIO_REG_DIG_VIN_CTL */ |
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#define PMIC_GPIO_REG_VIN_SHIFT 0 |
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#define PMIC_GPIO_REG_VIN_MASK 0x7 |
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/* PMIC_GPIO_REG_DIG_PULL_CTL */ |
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#define PMIC_GPIO_REG_PULL_SHIFT 0 |
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#define PMIC_GPIO_REG_PULL_MASK 0x7 |
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#define PMIC_GPIO_PULL_DOWN 4 |
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#define PMIC_GPIO_PULL_DISABLE 5 |
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/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ |
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#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 |
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#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 |
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#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF |
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/* PMIC_GPIO_REG_DIG_IN_CTL */ |
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#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 |
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#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 |
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#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf |
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/* PMIC_GPIO_REG_DIG_OUT_CTL */ |
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#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 |
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#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 |
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#define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 |
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#define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 |
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/* |
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* Output type - indicates pin should be configured as push-pull, |
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* open drain or open source. |
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*/ |
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#define PMIC_GPIO_OUT_BUF_CMOS 0 |
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#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 |
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#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 |
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/* PMIC_GPIO_REG_EN_CTL */ |
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#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 |
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#define PMIC_GPIO_PHYSICAL_OFFSET 1 |
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/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ |
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#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 |
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|
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/* Qualcomm specific pin configurations */ |
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#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) |
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#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) |
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#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) |
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#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) |
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#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) |
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/* The index of each function in pmic_gpio_functions[] array */ |
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enum pmic_gpio_func_index { |
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PMIC_GPIO_FUNC_INDEX_NORMAL, |
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PMIC_GPIO_FUNC_INDEX_PAIRED, |
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PMIC_GPIO_FUNC_INDEX_FUNC1, |
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PMIC_GPIO_FUNC_INDEX_FUNC2, |
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PMIC_GPIO_FUNC_INDEX_FUNC3, |
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PMIC_GPIO_FUNC_INDEX_FUNC4, |
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PMIC_GPIO_FUNC_INDEX_DTEST1, |
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PMIC_GPIO_FUNC_INDEX_DTEST2, |
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PMIC_GPIO_FUNC_INDEX_DTEST3, |
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PMIC_GPIO_FUNC_INDEX_DTEST4, |
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}; |
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/** |
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* struct pmic_gpio_pad - keep current GPIO settings |
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* @base: Address base in SPMI device. |
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* @is_enabled: Set to false when GPIO should be put in high Z state. |
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* @out_value: Cached pin output value |
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* @have_buffer: Set to true if GPIO output could be configured in push-pull, |
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* open-drain or open-source mode. |
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* @output_enabled: Set to true if GPIO output logic is enabled. |
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* @input_enabled: Set to true if GPIO input buffer logic is enabled. |
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* @analog_pass: Set to true if GPIO is in analog-pass-through mode. |
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* @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). |
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* @num_sources: Number of power-sources supported by this GPIO. |
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* @power_source: Current power-source used. |
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* @buffer_type: Push-pull, open-drain or open-source. |
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* @pullup: Constant current which flow trough GPIO output buffer. |
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* @strength: No, Low, Medium, High |
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* @function: See pmic_gpio_functions[] |
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* @atest: the ATEST selection for GPIO analog-pass-through mode |
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* @dtest_buffer: the DTEST buffer selection for digital input mode. |
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*/ |
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struct pmic_gpio_pad { |
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u16 base; |
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bool is_enabled; |
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bool out_value; |
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bool have_buffer; |
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bool output_enabled; |
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bool input_enabled; |
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bool analog_pass; |
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bool lv_mv_type; |
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unsigned int num_sources; |
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unsigned int power_source; |
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unsigned int buffer_type; |
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unsigned int pullup; |
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unsigned int strength; |
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unsigned int function; |
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unsigned int atest; |
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unsigned int dtest_buffer; |
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}; |
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struct pmic_gpio_state { |
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struct device *dev; |
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struct regmap *map; |
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struct pinctrl_dev *ctrl; |
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struct gpio_chip chip; |
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struct irq_chip irq; |
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}; |
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static const struct pinconf_generic_params pmic_gpio_bindings[] = { |
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{"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, |
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{"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, |
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{"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, |
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{"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, |
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{"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, |
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}; |
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#ifdef CONFIG_DEBUG_FS |
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static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { |
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PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), |
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PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), |
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PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), |
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PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), |
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PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), |
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}; |
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#endif |
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static const char *const pmic_gpio_groups[] = { |
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"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", |
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"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", |
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"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", |
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"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", |
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"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", |
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}; |
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static const char *const pmic_gpio_functions[] = { |
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[PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, |
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[PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, |
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[PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, |
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[PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, |
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[PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, |
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[PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, |
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[PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, |
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[PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, |
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[PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, |
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[PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, |
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}; |
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static int pmic_gpio_read(struct pmic_gpio_state *state, |
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struct pmic_gpio_pad *pad, unsigned int addr) |
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{ |
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unsigned int val; |
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int ret; |
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ret = regmap_read(state->map, pad->base + addr, &val); |
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if (ret < 0) |
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dev_err(state->dev, "read 0x%x failed\n", addr); |
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else |
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ret = val; |
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return ret; |
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} |
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static int pmic_gpio_write(struct pmic_gpio_state *state, |
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struct pmic_gpio_pad *pad, unsigned int addr, |
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unsigned int val) |
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{ |
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int ret; |
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ret = regmap_write(state->map, pad->base + addr, val); |
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if (ret < 0) |
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dev_err(state->dev, "write 0x%x failed\n", addr); |
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return ret; |
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} |
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static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) |
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{ |
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/* Every PIN is a group */ |
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return pctldev->desc->npins; |
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} |
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static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, |
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unsigned pin) |
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{ |
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return pctldev->desc->pins[pin].name; |
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} |
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static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, |
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const unsigned **pins, unsigned *num_pins) |
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{ |
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*pins = &pctldev->desc->pins[pin].number; |
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*num_pins = 1; |
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return 0; |
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} |
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static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { |
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.get_groups_count = pmic_gpio_get_groups_count, |
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.get_group_name = pmic_gpio_get_group_name, |
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.get_group_pins = pmic_gpio_get_group_pins, |
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
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.dt_free_map = pinctrl_utils_free_map, |
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}; |
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static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) |
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{ |
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return ARRAY_SIZE(pmic_gpio_functions); |
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} |
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static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, |
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unsigned function) |
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{ |
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return pmic_gpio_functions[function]; |
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} |
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static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, |
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unsigned function, |
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const char *const **groups, |
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unsigned *const num_qgroups) |
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{ |
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*groups = pmic_gpio_groups; |
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*num_qgroups = pctldev->desc->npins; |
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return 0; |
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} |
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static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, |
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unsigned pin) |
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{ |
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struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); |
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struct pmic_gpio_pad *pad; |
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unsigned int val; |
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int ret; |
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if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { |
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pr_err("function: %d is not defined\n", function); |
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return -EINVAL; |
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} |
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pad = pctldev->desc->pins[pin].drv_data; |
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/* |
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* Non-LV/MV subtypes only support 2 special functions, |
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* offsetting the dtestx function values by 2 |
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*/ |
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if (!pad->lv_mv_type) { |
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if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || |
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function == PMIC_GPIO_FUNC_INDEX_FUNC4) { |
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pr_err("LV/MV subtype doesn't have func3/func4\n"); |
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return -EINVAL; |
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} |
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if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) |
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function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - |
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PMIC_GPIO_FUNC_INDEX_FUNC3); |
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} |
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pad->function = function; |
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if (pad->analog_pass) |
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val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; |
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else if (pad->output_enabled && pad->input_enabled) |
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val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; |
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else if (pad->output_enabled) |
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val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; |
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else |
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val = PMIC_GPIO_MODE_DIGITAL_INPUT; |
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if (pad->lv_mv_type) { |
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ret = pmic_gpio_write(state, pad, |
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PMIC_GPIO_REG_MODE_CTL, val); |
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if (ret < 0) |
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return ret; |
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val = pad->atest - 1; |
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ret = pmic_gpio_write(state, pad, |
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PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); |
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if (ret < 0) |
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return ret; |
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val = pad->out_value |
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<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; |
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val |= pad->function |
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& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; |
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ret = pmic_gpio_write(state, pad, |
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PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); |
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if (ret < 0) |
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return ret; |
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} else { |
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val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; |
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val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; |
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val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; |
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ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); |
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if (ret < 0) |
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return ret; |
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} |
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val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; |
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return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); |
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} |
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static const struct pinmux_ops pmic_gpio_pinmux_ops = { |
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.get_functions_count = pmic_gpio_get_functions_count, |
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.get_function_name = pmic_gpio_get_function_name, |
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.get_function_groups = pmic_gpio_get_function_groups, |
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.set_mux = pmic_gpio_set_mux, |
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}; |
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static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, |
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unsigned int pin, unsigned long *config) |
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{ |
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unsigned param = pinconf_to_config_param(*config); |
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struct pmic_gpio_pad *pad; |
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unsigned arg; |
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pad = pctldev->desc->pins[pin].drv_data; |
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switch (param) { |
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case PIN_CONFIG_DRIVE_PUSH_PULL: |
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if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
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if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
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if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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if (pad->pullup != PMIC_GPIO_PULL_DOWN) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_DISABLE: |
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if (pad->pullup != PMIC_GPIO_PULL_DISABLE) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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if (pad->pullup != PMIC_GPIO_PULL_UP_30) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
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if (pad->is_enabled) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_POWER_SOURCE: |
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arg = pad->power_source; |
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break; |
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case PIN_CONFIG_INPUT_ENABLE: |
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if (!pad->input_enabled) |
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return -EINVAL; |
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arg = 1; |
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break; |
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case PIN_CONFIG_OUTPUT: |
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arg = pad->out_value; |
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break; |
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case PMIC_GPIO_CONF_PULL_UP: |
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arg = pad->pullup; |
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break; |
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case PMIC_GPIO_CONF_STRENGTH: |
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arg = pad->strength; |
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break; |
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case PMIC_GPIO_CONF_ATEST: |
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arg = pad->atest; |
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break; |
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case PMIC_GPIO_CONF_ANALOG_PASS: |
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arg = pad->analog_pass; |
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break; |
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case PMIC_GPIO_CONF_DTEST_BUFFER: |
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arg = pad->dtest_buffer; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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*config = pinconf_to_config_packed(param, arg); |
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return 0; |
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} |
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|
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static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, |
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unsigned long *configs, unsigned nconfs) |
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{ |
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struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); |
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struct pmic_gpio_pad *pad; |
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unsigned param, arg; |
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unsigned int val; |
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int i, ret; |
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|
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pad = pctldev->desc->pins[pin].drv_data; |
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|
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pad->is_enabled = true; |
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for (i = 0; i < nconfs; i++) { |
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param = pinconf_to_config_param(configs[i]); |
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arg = pinconf_to_config_argument(configs[i]); |
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|
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switch (param) { |
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case PIN_CONFIG_DRIVE_PUSH_PULL: |
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pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; |
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break; |
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case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
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if (!pad->have_buffer) |
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return -EINVAL; |
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pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; |
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break; |
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case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
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if (!pad->have_buffer) |
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return -EINVAL; |
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pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; |
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break; |
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case PIN_CONFIG_BIAS_DISABLE: |
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pad->pullup = PMIC_GPIO_PULL_DISABLE; |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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pad->pullup = PMIC_GPIO_PULL_UP_30; |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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if (arg) |
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pad->pullup = PMIC_GPIO_PULL_DOWN; |
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else |
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pad->pullup = PMIC_GPIO_PULL_DISABLE; |
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break; |
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
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pad->is_enabled = false; |
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break; |
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case PIN_CONFIG_POWER_SOURCE: |
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if (arg >= pad->num_sources) |
|
return -EINVAL; |
|
pad->power_source = arg; |
|
break; |
|
case PIN_CONFIG_INPUT_ENABLE: |
|
pad->input_enabled = arg ? true : false; |
|
break; |
|
case PIN_CONFIG_OUTPUT: |
|
pad->output_enabled = true; |
|
pad->out_value = arg; |
|
break; |
|
case PMIC_GPIO_CONF_PULL_UP: |
|
if (arg > PMIC_GPIO_PULL_UP_1P5_30) |
|
return -EINVAL; |
|
pad->pullup = arg; |
|
break; |
|
case PMIC_GPIO_CONF_STRENGTH: |
|
if (arg > PMIC_GPIO_STRENGTH_LOW) |
|
return -EINVAL; |
|
pad->strength = arg; |
|
break; |
|
case PMIC_GPIO_CONF_ATEST: |
|
if (!pad->lv_mv_type || arg > 4) |
|
return -EINVAL; |
|
pad->atest = arg; |
|
break; |
|
case PMIC_GPIO_CONF_ANALOG_PASS: |
|
if (!pad->lv_mv_type) |
|
return -EINVAL; |
|
pad->analog_pass = true; |
|
break; |
|
case PMIC_GPIO_CONF_DTEST_BUFFER: |
|
if (arg > 4) |
|
return -EINVAL; |
|
pad->dtest_buffer = arg; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; |
|
|
|
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
|
|
val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; |
|
|
|
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
|
|
val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; |
|
val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; |
|
|
|
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (pad->dtest_buffer == 0) { |
|
val = 0; |
|
} else { |
|
if (pad->lv_mv_type) { |
|
val = pad->dtest_buffer - 1; |
|
val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; |
|
} else { |
|
val = BIT(pad->dtest_buffer - 1); |
|
} |
|
} |
|
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (pad->analog_pass) |
|
val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; |
|
else if (pad->output_enabled && pad->input_enabled) |
|
val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; |
|
else if (pad->output_enabled) |
|
val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; |
|
else |
|
val = PMIC_GPIO_MODE_DIGITAL_INPUT; |
|
|
|
if (pad->lv_mv_type) { |
|
ret = pmic_gpio_write(state, pad, |
|
PMIC_GPIO_REG_MODE_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
|
|
val = pad->atest - 1; |
|
ret = pmic_gpio_write(state, pad, |
|
PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); |
|
if (ret < 0) |
|
return ret; |
|
|
|
val = pad->out_value |
|
<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; |
|
val |= pad->function |
|
& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; |
|
ret = pmic_gpio_write(state, pad, |
|
PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
} else { |
|
val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; |
|
val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; |
|
val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; |
|
|
|
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); |
|
if (ret < 0) |
|
return ret; |
|
} |
|
|
|
val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; |
|
|
|
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); |
|
|
|
return ret; |
|
} |
|
|
|
static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, |
|
struct seq_file *s, unsigned pin) |
|
{ |
|
struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); |
|
struct pmic_gpio_pad *pad; |
|
int ret, val, function; |
|
|
|
static const char *const biases[] = { |
|
"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", |
|
"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" |
|
}; |
|
static const char *const buffer_types[] = { |
|
"push-pull", "open-drain", "open-source" |
|
}; |
|
static const char *const strengths[] = { |
|
"no", "high", "medium", "low" |
|
}; |
|
|
|
pad = pctldev->desc->pins[pin].drv_data; |
|
|
|
seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); |
|
|
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); |
|
|
|
if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { |
|
seq_puts(s, " ---"); |
|
} else { |
|
if (pad->input_enabled) { |
|
ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); |
|
if (ret < 0) |
|
return; |
|
|
|
ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; |
|
pad->out_value = ret; |
|
} |
|
/* |
|
* For the non-LV/MV subtypes only 2 special functions are |
|
* available, offsetting the dtest function values by 2. |
|
*/ |
|
function = pad->function; |
|
if (!pad->lv_mv_type && |
|
pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) |
|
function += PMIC_GPIO_FUNC_INDEX_DTEST1 - |
|
PMIC_GPIO_FUNC_INDEX_FUNC3; |
|
|
|
if (pad->analog_pass) |
|
seq_puts(s, " analog-pass"); |
|
else |
|
seq_printf(s, " %-4s", |
|
pad->output_enabled ? "out" : "in"); |
|
seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); |
|
seq_printf(s, " %-7s", pmic_gpio_functions[function]); |
|
seq_printf(s, " vin-%d", pad->power_source); |
|
seq_printf(s, " %-27s", biases[pad->pullup]); |
|
seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); |
|
seq_printf(s, " %-7s", strengths[pad->strength]); |
|
seq_printf(s, " atest-%d", pad->atest); |
|
seq_printf(s, " dtest-%d", pad->dtest_buffer); |
|
} |
|
} |
|
|
|
static const struct pinconf_ops pmic_gpio_pinconf_ops = { |
|
.is_generic = true, |
|
.pin_config_group_get = pmic_gpio_config_get, |
|
.pin_config_group_set = pmic_gpio_config_set, |
|
.pin_config_group_dbg_show = pmic_gpio_config_dbg_show, |
|
}; |
|
|
|
static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) |
|
{ |
|
struct pmic_gpio_state *state = gpiochip_get_data(chip); |
|
unsigned long config; |
|
|
|
config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); |
|
|
|
return pmic_gpio_config_set(state->ctrl, pin, &config, 1); |
|
} |
|
|
|
static int pmic_gpio_direction_output(struct gpio_chip *chip, |
|
unsigned pin, int val) |
|
{ |
|
struct pmic_gpio_state *state = gpiochip_get_data(chip); |
|
unsigned long config; |
|
|
|
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); |
|
|
|
return pmic_gpio_config_set(state->ctrl, pin, &config, 1); |
|
} |
|
|
|
static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) |
|
{ |
|
struct pmic_gpio_state *state = gpiochip_get_data(chip); |
|
struct pmic_gpio_pad *pad; |
|
int ret; |
|
|
|
pad = state->ctrl->desc->pins[pin].drv_data; |
|
|
|
if (!pad->is_enabled) |
|
return -EINVAL; |
|
|
|
if (pad->input_enabled) { |
|
ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); |
|
if (ret < 0) |
|
return ret; |
|
|
|
pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; |
|
} |
|
|
|
return !!pad->out_value; |
|
} |
|
|
|
static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) |
|
{ |
|
struct pmic_gpio_state *state = gpiochip_get_data(chip); |
|
unsigned long config; |
|
|
|
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); |
|
|
|
pmic_gpio_config_set(state->ctrl, pin, &config, 1); |
|
} |
|
|
|
static int pmic_gpio_of_xlate(struct gpio_chip *chip, |
|
const struct of_phandle_args *gpio_desc, |
|
u32 *flags) |
|
{ |
|
if (chip->of_gpio_n_cells < 2) |
|
return -EINVAL; |
|
|
|
if (flags) |
|
*flags = gpio_desc->args[1]; |
|
|
|
return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; |
|
} |
|
|
|
static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
|
{ |
|
struct pmic_gpio_state *state = gpiochip_get_data(chip); |
|
unsigned i; |
|
|
|
for (i = 0; i < chip->ngpio; i++) { |
|
pmic_gpio_config_dbg_show(state->ctrl, s, i); |
|
seq_puts(s, "\n"); |
|
} |
|
} |
|
|
|
static const struct gpio_chip pmic_gpio_gpio_template = { |
|
.direction_input = pmic_gpio_direction_input, |
|
.direction_output = pmic_gpio_direction_output, |
|
.get = pmic_gpio_get, |
|
.set = pmic_gpio_set, |
|
.request = gpiochip_generic_request, |
|
.free = gpiochip_generic_free, |
|
.of_xlate = pmic_gpio_of_xlate, |
|
.dbg_show = pmic_gpio_dbg_show, |
|
}; |
|
|
|
static int pmic_gpio_populate(struct pmic_gpio_state *state, |
|
struct pmic_gpio_pad *pad) |
|
{ |
|
int type, subtype, val, dir; |
|
|
|
type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); |
|
if (type < 0) |
|
return type; |
|
|
|
if (type != PMIC_GPIO_TYPE) { |
|
dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", |
|
type, pad->base); |
|
return -ENODEV; |
|
} |
|
|
|
subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); |
|
if (subtype < 0) |
|
return subtype; |
|
|
|
switch (subtype) { |
|
case PMIC_GPIO_SUBTYPE_GPIO_4CH: |
|
pad->have_buffer = true; |
|
fallthrough; |
|
case PMIC_GPIO_SUBTYPE_GPIOC_4CH: |
|
pad->num_sources = 4; |
|
break; |
|
case PMIC_GPIO_SUBTYPE_GPIO_8CH: |
|
pad->have_buffer = true; |
|
fallthrough; |
|
case PMIC_GPIO_SUBTYPE_GPIOC_8CH: |
|
pad->num_sources = 8; |
|
break; |
|
case PMIC_GPIO_SUBTYPE_GPIO_LV: |
|
pad->num_sources = 1; |
|
pad->have_buffer = true; |
|
pad->lv_mv_type = true; |
|
break; |
|
case PMIC_GPIO_SUBTYPE_GPIO_MV: |
|
pad->num_sources = 2; |
|
pad->have_buffer = true; |
|
pad->lv_mv_type = true; |
|
break; |
|
default: |
|
dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); |
|
return -ENODEV; |
|
} |
|
|
|
if (pad->lv_mv_type) { |
|
val = pmic_gpio_read(state, pad, |
|
PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); |
|
pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; |
|
|
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; |
|
} else { |
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; |
|
|
|
dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; |
|
dir &= PMIC_GPIO_REG_MODE_DIR_MASK; |
|
pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; |
|
pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; |
|
} |
|
|
|
switch (dir) { |
|
case PMIC_GPIO_MODE_DIGITAL_INPUT: |
|
pad->input_enabled = true; |
|
pad->output_enabled = false; |
|
break; |
|
case PMIC_GPIO_MODE_DIGITAL_OUTPUT: |
|
pad->input_enabled = false; |
|
pad->output_enabled = true; |
|
break; |
|
case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: |
|
pad->input_enabled = true; |
|
pad->output_enabled = true; |
|
break; |
|
case PMIC_GPIO_MODE_ANALOG_PASS_THRU: |
|
if (!pad->lv_mv_type) |
|
return -ENODEV; |
|
pad->analog_pass = true; |
|
break; |
|
default: |
|
dev_err(state->dev, "unknown GPIO direction\n"); |
|
return -ENODEV; |
|
} |
|
|
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; |
|
pad->power_source &= PMIC_GPIO_REG_VIN_MASK; |
|
|
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; |
|
pad->pullup &= PMIC_GPIO_REG_PULL_MASK; |
|
|
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) |
|
pad->dtest_buffer = |
|
(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; |
|
else if (!pad->lv_mv_type) |
|
pad->dtest_buffer = ffs(val); |
|
else |
|
pad->dtest_buffer = 0; |
|
|
|
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); |
|
if (val < 0) |
|
return val; |
|
|
|
pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; |
|
pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; |
|
|
|
pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; |
|
pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; |
|
|
|
if (pad->lv_mv_type) { |
|
val = pmic_gpio_read(state, pad, |
|
PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); |
|
if (val < 0) |
|
return val; |
|
pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; |
|
} |
|
|
|
/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ |
|
pad->is_enabled = true; |
|
return 0; |
|
} |
|
|
|
static int pmic_gpio_domain_translate(struct irq_domain *domain, |
|
struct irq_fwspec *fwspec, |
|
unsigned long *hwirq, |
|
unsigned int *type) |
|
{ |
|
struct pmic_gpio_state *state = container_of(domain->host_data, |
|
struct pmic_gpio_state, |
|
chip); |
|
|
|
if (fwspec->param_count != 2 || |
|
fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) |
|
return -EINVAL; |
|
|
|
*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET; |
|
*type = fwspec->param[1]; |
|
|
|
return 0; |
|
} |
|
|
|
static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip, |
|
unsigned int offset) |
|
{ |
|
return offset + PMIC_GPIO_PHYSICAL_OFFSET; |
|
} |
|
|
|
static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip, |
|
unsigned int child_hwirq, |
|
unsigned int child_type, |
|
unsigned int *parent_hwirq, |
|
unsigned int *parent_type) |
|
{ |
|
*parent_hwirq = child_hwirq + 0xc0; |
|
*parent_type = child_type; |
|
|
|
return 0; |
|
} |
|
|
|
static int pmic_gpio_probe(struct platform_device *pdev) |
|
{ |
|
struct irq_domain *parent_domain; |
|
struct device_node *parent_node; |
|
struct device *dev = &pdev->dev; |
|
struct pinctrl_pin_desc *pindesc; |
|
struct pinctrl_desc *pctrldesc; |
|
struct pmic_gpio_pad *pad, *pads; |
|
struct pmic_gpio_state *state; |
|
struct gpio_irq_chip *girq; |
|
int ret, npins, i; |
|
u32 reg; |
|
|
|
ret = of_property_read_u32(dev->of_node, "reg", ®); |
|
if (ret < 0) { |
|
dev_err(dev, "missing base address"); |
|
return ret; |
|
} |
|
|
|
npins = (uintptr_t) device_get_match_data(&pdev->dev); |
|
|
|
state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); |
|
if (!state) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, state); |
|
|
|
state->dev = &pdev->dev; |
|
state->map = dev_get_regmap(dev->parent, NULL); |
|
|
|
pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); |
|
if (!pindesc) |
|
return -ENOMEM; |
|
|
|
pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); |
|
if (!pads) |
|
return -ENOMEM; |
|
|
|
pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); |
|
if (!pctrldesc) |
|
return -ENOMEM; |
|
|
|
pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; |
|
pctrldesc->pmxops = &pmic_gpio_pinmux_ops; |
|
pctrldesc->confops = &pmic_gpio_pinconf_ops; |
|
pctrldesc->owner = THIS_MODULE; |
|
pctrldesc->name = dev_name(dev); |
|
pctrldesc->pins = pindesc; |
|
pctrldesc->npins = npins; |
|
pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); |
|
pctrldesc->custom_params = pmic_gpio_bindings; |
|
#ifdef CONFIG_DEBUG_FS |
|
pctrldesc->custom_conf_items = pmic_conf_items; |
|
#endif |
|
|
|
for (i = 0; i < npins; i++, pindesc++) { |
|
pad = &pads[i]; |
|
pindesc->drv_data = pad; |
|
pindesc->number = i; |
|
pindesc->name = pmic_gpio_groups[i]; |
|
|
|
pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; |
|
|
|
ret = pmic_gpio_populate(state, pad); |
|
if (ret < 0) |
|
return ret; |
|
} |
|
|
|
state->chip = pmic_gpio_gpio_template; |
|
state->chip.parent = dev; |
|
state->chip.base = -1; |
|
state->chip.ngpio = npins; |
|
state->chip.label = dev_name(dev); |
|
state->chip.of_gpio_n_cells = 2; |
|
state->chip.can_sleep = false; |
|
|
|
state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); |
|
if (IS_ERR(state->ctrl)) |
|
return PTR_ERR(state->ctrl); |
|
|
|
parent_node = of_irq_find_parent(state->dev->of_node); |
|
if (!parent_node) |
|
return -ENXIO; |
|
|
|
parent_domain = irq_find_host(parent_node); |
|
of_node_put(parent_node); |
|
if (!parent_domain) |
|
return -ENXIO; |
|
|
|
state->irq.name = "spmi-gpio", |
|
state->irq.irq_ack = irq_chip_ack_parent, |
|
state->irq.irq_mask = irq_chip_mask_parent, |
|
state->irq.irq_unmask = irq_chip_unmask_parent, |
|
state->irq.irq_set_type = irq_chip_set_type_parent, |
|
state->irq.irq_set_wake = irq_chip_set_wake_parent, |
|
state->irq.flags = IRQCHIP_MASK_ON_SUSPEND, |
|
|
|
girq = &state->chip.irq; |
|
girq->chip = &state->irq; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
girq->handler = handle_level_irq; |
|
girq->fwnode = of_node_to_fwnode(state->dev->of_node); |
|
girq->parent_domain = parent_domain; |
|
girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; |
|
girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; |
|
girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq; |
|
girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate; |
|
|
|
ret = gpiochip_add_data(&state->chip, state); |
|
if (ret) { |
|
dev_err(state->dev, "can't add gpio chip\n"); |
|
return ret; |
|
} |
|
|
|
/* |
|
* For DeviceTree-supported systems, the gpio core checks the |
|
* pinctrl's device node for the "gpio-ranges" property. |
|
* If it is present, it takes care of adding the pin ranges |
|
* for the driver. In this case the driver can skip ahead. |
|
* |
|
* In order to remain compatible with older, existing DeviceTree |
|
* files which don't set the "gpio-ranges" property or systems that |
|
* utilize ACPI the driver has to call gpiochip_add_pin_range(). |
|
*/ |
|
if (!of_property_read_bool(dev->of_node, "gpio-ranges")) { |
|
ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, |
|
npins); |
|
if (ret) { |
|
dev_err(dev, "failed to add pin range\n"); |
|
goto err_range; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
err_range: |
|
gpiochip_remove(&state->chip); |
|
return ret; |
|
} |
|
|
|
static int pmic_gpio_remove(struct platform_device *pdev) |
|
{ |
|
struct pmic_gpio_state *state = platform_get_drvdata(pdev); |
|
|
|
gpiochip_remove(&state->chip); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id pmic_gpio_of_match[] = { |
|
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, |
|
{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, |
|
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, |
|
/* pm8950 has 8 GPIOs with holes on 3 */ |
|
{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 }, |
|
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, |
|
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, |
|
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, |
|
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, |
|
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, |
|
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, |
|
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ |
|
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, |
|
/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ |
|
{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, |
|
/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ |
|
{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, |
|
/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ |
|
{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, |
|
/* pm8150b has 12 GPIOs with holes on 3, r and 7 */ |
|
{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, |
|
/* pm8150l has 12 GPIOs with holes on 7 */ |
|
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, |
|
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, |
|
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, |
|
/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ |
|
{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, |
|
{ }, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); |
|
|
|
static struct platform_driver pmic_gpio_driver = { |
|
.driver = { |
|
.name = "qcom-spmi-gpio", |
|
.of_match_table = pmic_gpio_of_match, |
|
}, |
|
.probe = pmic_gpio_probe, |
|
.remove = pmic_gpio_remove, |
|
}; |
|
|
|
module_platform_driver(pmic_gpio_driver); |
|
|
|
MODULE_AUTHOR("Ivan T. Ivanov <[email protected]>"); |
|
MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); |
|
MODULE_ALIAS("platform:qcom-spmi-gpio"); |
|
MODULE_LICENSE("GPL v2");
|
|
|