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1018 lines
29 KiB
1018 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pinctrl/pinctrl.h> |
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#include "pinctrl-msm.h" |
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#define FUNCTION(fname) \ |
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[msm_mux_##fname] = { \ |
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.name = #fname, \ |
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.groups = fname##_groups, \ |
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.ngroups = ARRAY_SIZE(fname##_groups), \ |
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} |
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#define REG_SIZE 0x1000 |
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#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ |
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{ \ |
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.name = "gpio" #id, \ |
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.pins = gpio##id##_pins, \ |
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.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ |
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.funcs = (int[]){ \ |
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msm_mux_gpio, /* gpio mode */ \ |
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msm_mux_##f1, \ |
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msm_mux_##f2, \ |
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msm_mux_##f3, \ |
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msm_mux_##f4, \ |
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msm_mux_##f5, \ |
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msm_mux_##f6, \ |
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msm_mux_##f7, \ |
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msm_mux_##f8, \ |
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msm_mux_##f9 \ |
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}, \ |
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.nfuncs = 10, \ |
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.ctl_reg = REG_SIZE * id, \ |
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.io_reg = 0x4 + REG_SIZE * id, \ |
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.intr_cfg_reg = 0x8 + REG_SIZE * id, \ |
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.intr_status_reg = 0xc + REG_SIZE * id, \ |
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.intr_target_reg = 0x8 + REG_SIZE * id, \ |
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.mux_bit = 2, \ |
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.pull_bit = 0, \ |
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.drv_bit = 6, \ |
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.oe_bit = 9, \ |
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.in_bit = 0, \ |
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.out_bit = 1, \ |
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.intr_enable_bit = 0, \ |
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.intr_status_bit = 0, \ |
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.intr_target_bit = 5, \ |
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.intr_target_kpss_val = 3, \ |
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.intr_raw_status_bit = 4, \ |
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.intr_polarity_bit = 1, \ |
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.intr_detection_bit = 2, \ |
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.intr_detection_width = 2, \ |
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} |
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#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ |
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{ \ |
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.name = #pg_name, \ |
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.pins = pg_name##_pins, \ |
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.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ |
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.ctl_reg = ctl, \ |
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.io_reg = 0, \ |
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.intr_cfg_reg = 0, \ |
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.intr_status_reg = 0, \ |
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.intr_target_reg = 0, \ |
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.mux_bit = -1, \ |
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.pull_bit = pull, \ |
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.drv_bit = drv, \ |
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.oe_bit = -1, \ |
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.in_bit = -1, \ |
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.out_bit = -1, \ |
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.intr_enable_bit = -1, \ |
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.intr_status_bit = -1, \ |
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.intr_target_bit = -1, \ |
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.intr_raw_status_bit = -1, \ |
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.intr_polarity_bit = -1, \ |
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.intr_detection_bit = -1, \ |
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.intr_detection_width = -1, \ |
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} |
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static const struct pinctrl_pin_desc sdx55_pins[] = { |
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PINCTRL_PIN(0, "GPIO_0"), |
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PINCTRL_PIN(1, "GPIO_1"), |
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PINCTRL_PIN(2, "GPIO_2"), |
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PINCTRL_PIN(3, "GPIO_3"), |
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PINCTRL_PIN(4, "GPIO_4"), |
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PINCTRL_PIN(5, "GPIO_5"), |
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PINCTRL_PIN(6, "GPIO_6"), |
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PINCTRL_PIN(7, "GPIO_7"), |
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PINCTRL_PIN(8, "GPIO_8"), |
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PINCTRL_PIN(9, "GPIO_9"), |
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PINCTRL_PIN(10, "GPIO_10"), |
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PINCTRL_PIN(11, "GPIO_11"), |
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PINCTRL_PIN(12, "GPIO_12"), |
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PINCTRL_PIN(13, "GPIO_13"), |
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PINCTRL_PIN(14, "GPIO_14"), |
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PINCTRL_PIN(15, "GPIO_15"), |
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PINCTRL_PIN(16, "GPIO_16"), |
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PINCTRL_PIN(17, "GPIO_17"), |
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PINCTRL_PIN(18, "GPIO_18"), |
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PINCTRL_PIN(19, "GPIO_19"), |
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PINCTRL_PIN(20, "GPIO_20"), |
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PINCTRL_PIN(21, "GPIO_21"), |
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PINCTRL_PIN(22, "GPIO_22"), |
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PINCTRL_PIN(23, "GPIO_23"), |
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PINCTRL_PIN(24, "GPIO_24"), |
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PINCTRL_PIN(25, "GPIO_25"), |
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PINCTRL_PIN(26, "GPIO_26"), |
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PINCTRL_PIN(27, "GPIO_27"), |
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PINCTRL_PIN(28, "GPIO_28"), |
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PINCTRL_PIN(29, "GPIO_29"), |
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PINCTRL_PIN(30, "GPIO_30"), |
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PINCTRL_PIN(31, "GPIO_31"), |
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PINCTRL_PIN(32, "GPIO_32"), |
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PINCTRL_PIN(33, "GPIO_33"), |
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PINCTRL_PIN(34, "GPIO_34"), |
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PINCTRL_PIN(35, "GPIO_35"), |
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PINCTRL_PIN(36, "GPIO_36"), |
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PINCTRL_PIN(37, "GPIO_37"), |
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PINCTRL_PIN(38, "GPIO_38"), |
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PINCTRL_PIN(39, "GPIO_39"), |
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PINCTRL_PIN(40, "GPIO_40"), |
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PINCTRL_PIN(41, "GPIO_41"), |
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PINCTRL_PIN(42, "GPIO_42"), |
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PINCTRL_PIN(43, "GPIO_43"), |
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PINCTRL_PIN(44, "GPIO_44"), |
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PINCTRL_PIN(45, "GPIO_45"), |
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PINCTRL_PIN(46, "GPIO_46"), |
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PINCTRL_PIN(47, "GPIO_47"), |
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PINCTRL_PIN(48, "GPIO_48"), |
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PINCTRL_PIN(49, "GPIO_49"), |
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PINCTRL_PIN(50, "GPIO_50"), |
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PINCTRL_PIN(51, "GPIO_51"), |
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PINCTRL_PIN(52, "GPIO_52"), |
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PINCTRL_PIN(53, "GPIO_53"), |
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PINCTRL_PIN(54, "GPIO_54"), |
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PINCTRL_PIN(55, "GPIO_55"), |
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PINCTRL_PIN(56, "GPIO_56"), |
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PINCTRL_PIN(57, "GPIO_57"), |
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PINCTRL_PIN(58, "GPIO_58"), |
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PINCTRL_PIN(59, "GPIO_59"), |
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PINCTRL_PIN(60, "GPIO_60"), |
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PINCTRL_PIN(61, "GPIO_61"), |
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PINCTRL_PIN(62, "GPIO_62"), |
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PINCTRL_PIN(63, "GPIO_63"), |
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PINCTRL_PIN(64, "GPIO_64"), |
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PINCTRL_PIN(65, "GPIO_65"), |
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PINCTRL_PIN(66, "GPIO_66"), |
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PINCTRL_PIN(67, "GPIO_67"), |
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PINCTRL_PIN(68, "GPIO_68"), |
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PINCTRL_PIN(69, "GPIO_69"), |
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PINCTRL_PIN(70, "GPIO_70"), |
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PINCTRL_PIN(71, "GPIO_71"), |
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PINCTRL_PIN(72, "GPIO_72"), |
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PINCTRL_PIN(73, "GPIO_73"), |
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PINCTRL_PIN(74, "GPIO_74"), |
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PINCTRL_PIN(75, "GPIO_75"), |
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PINCTRL_PIN(76, "GPIO_76"), |
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PINCTRL_PIN(77, "GPIO_77"), |
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PINCTRL_PIN(78, "GPIO_78"), |
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PINCTRL_PIN(79, "GPIO_79"), |
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PINCTRL_PIN(80, "GPIO_80"), |
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PINCTRL_PIN(81, "GPIO_81"), |
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PINCTRL_PIN(82, "GPIO_82"), |
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PINCTRL_PIN(83, "GPIO_83"), |
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PINCTRL_PIN(84, "GPIO_84"), |
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PINCTRL_PIN(85, "GPIO_85"), |
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PINCTRL_PIN(86, "GPIO_86"), |
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PINCTRL_PIN(87, "GPIO_87"), |
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PINCTRL_PIN(88, "GPIO_88"), |
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PINCTRL_PIN(89, "GPIO_89"), |
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PINCTRL_PIN(90, "GPIO_90"), |
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PINCTRL_PIN(91, "GPIO_91"), |
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PINCTRL_PIN(92, "GPIO_92"), |
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PINCTRL_PIN(93, "GPIO_93"), |
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PINCTRL_PIN(94, "GPIO_94"), |
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PINCTRL_PIN(95, "GPIO_95"), |
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PINCTRL_PIN(96, "GPIO_96"), |
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PINCTRL_PIN(97, "GPIO_97"), |
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PINCTRL_PIN(98, "GPIO_98"), |
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PINCTRL_PIN(99, "GPIO_99"), |
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PINCTRL_PIN(100, "GPIO_100"), |
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PINCTRL_PIN(101, "GPIO_101"), |
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PINCTRL_PIN(102, "GPIO_102"), |
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PINCTRL_PIN(103, "GPIO_103"), |
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PINCTRL_PIN(104, "GPIO_104"), |
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PINCTRL_PIN(105, "GPIO_105"), |
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PINCTRL_PIN(106, "GPIO_106"), |
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PINCTRL_PIN(107, "GPIO_107"), |
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PINCTRL_PIN(108, "SDC1_RCLK"), |
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PINCTRL_PIN(109, "SDC1_CLK"), |
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PINCTRL_PIN(110, "SDC1_CMD"), |
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PINCTRL_PIN(111, "SDC1_DATA"), |
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}; |
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#define DECLARE_MSM_GPIO_PINS(pin) \ |
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static const unsigned int gpio##pin##_pins[] = { pin } |
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DECLARE_MSM_GPIO_PINS(0); |
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DECLARE_MSM_GPIO_PINS(1); |
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DECLARE_MSM_GPIO_PINS(2); |
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DECLARE_MSM_GPIO_PINS(3); |
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DECLARE_MSM_GPIO_PINS(4); |
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DECLARE_MSM_GPIO_PINS(5); |
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DECLARE_MSM_GPIO_PINS(6); |
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DECLARE_MSM_GPIO_PINS(7); |
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DECLARE_MSM_GPIO_PINS(8); |
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DECLARE_MSM_GPIO_PINS(9); |
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DECLARE_MSM_GPIO_PINS(10); |
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DECLARE_MSM_GPIO_PINS(11); |
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DECLARE_MSM_GPIO_PINS(12); |
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DECLARE_MSM_GPIO_PINS(13); |
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DECLARE_MSM_GPIO_PINS(14); |
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DECLARE_MSM_GPIO_PINS(15); |
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DECLARE_MSM_GPIO_PINS(16); |
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DECLARE_MSM_GPIO_PINS(17); |
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DECLARE_MSM_GPIO_PINS(18); |
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DECLARE_MSM_GPIO_PINS(19); |
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DECLARE_MSM_GPIO_PINS(20); |
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DECLARE_MSM_GPIO_PINS(21); |
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DECLARE_MSM_GPIO_PINS(22); |
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DECLARE_MSM_GPIO_PINS(23); |
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DECLARE_MSM_GPIO_PINS(24); |
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DECLARE_MSM_GPIO_PINS(25); |
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DECLARE_MSM_GPIO_PINS(26); |
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DECLARE_MSM_GPIO_PINS(27); |
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DECLARE_MSM_GPIO_PINS(28); |
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DECLARE_MSM_GPIO_PINS(29); |
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DECLARE_MSM_GPIO_PINS(30); |
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DECLARE_MSM_GPIO_PINS(31); |
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DECLARE_MSM_GPIO_PINS(32); |
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DECLARE_MSM_GPIO_PINS(33); |
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DECLARE_MSM_GPIO_PINS(34); |
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DECLARE_MSM_GPIO_PINS(35); |
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DECLARE_MSM_GPIO_PINS(36); |
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DECLARE_MSM_GPIO_PINS(37); |
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DECLARE_MSM_GPIO_PINS(38); |
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DECLARE_MSM_GPIO_PINS(39); |
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DECLARE_MSM_GPIO_PINS(40); |
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DECLARE_MSM_GPIO_PINS(41); |
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DECLARE_MSM_GPIO_PINS(42); |
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DECLARE_MSM_GPIO_PINS(43); |
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DECLARE_MSM_GPIO_PINS(44); |
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DECLARE_MSM_GPIO_PINS(45); |
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DECLARE_MSM_GPIO_PINS(46); |
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DECLARE_MSM_GPIO_PINS(47); |
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DECLARE_MSM_GPIO_PINS(48); |
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DECLARE_MSM_GPIO_PINS(49); |
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DECLARE_MSM_GPIO_PINS(50); |
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DECLARE_MSM_GPIO_PINS(51); |
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DECLARE_MSM_GPIO_PINS(52); |
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DECLARE_MSM_GPIO_PINS(53); |
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DECLARE_MSM_GPIO_PINS(54); |
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DECLARE_MSM_GPIO_PINS(55); |
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DECLARE_MSM_GPIO_PINS(56); |
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DECLARE_MSM_GPIO_PINS(57); |
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DECLARE_MSM_GPIO_PINS(58); |
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DECLARE_MSM_GPIO_PINS(59); |
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DECLARE_MSM_GPIO_PINS(60); |
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DECLARE_MSM_GPIO_PINS(61); |
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DECLARE_MSM_GPIO_PINS(62); |
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DECLARE_MSM_GPIO_PINS(63); |
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DECLARE_MSM_GPIO_PINS(64); |
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DECLARE_MSM_GPIO_PINS(65); |
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DECLARE_MSM_GPIO_PINS(66); |
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DECLARE_MSM_GPIO_PINS(67); |
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DECLARE_MSM_GPIO_PINS(68); |
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DECLARE_MSM_GPIO_PINS(69); |
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DECLARE_MSM_GPIO_PINS(70); |
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DECLARE_MSM_GPIO_PINS(71); |
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DECLARE_MSM_GPIO_PINS(72); |
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DECLARE_MSM_GPIO_PINS(73); |
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DECLARE_MSM_GPIO_PINS(74); |
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DECLARE_MSM_GPIO_PINS(75); |
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DECLARE_MSM_GPIO_PINS(76); |
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DECLARE_MSM_GPIO_PINS(77); |
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DECLARE_MSM_GPIO_PINS(78); |
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DECLARE_MSM_GPIO_PINS(79); |
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DECLARE_MSM_GPIO_PINS(80); |
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DECLARE_MSM_GPIO_PINS(81); |
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DECLARE_MSM_GPIO_PINS(82); |
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DECLARE_MSM_GPIO_PINS(83); |
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DECLARE_MSM_GPIO_PINS(84); |
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DECLARE_MSM_GPIO_PINS(85); |
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DECLARE_MSM_GPIO_PINS(86); |
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DECLARE_MSM_GPIO_PINS(87); |
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DECLARE_MSM_GPIO_PINS(88); |
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DECLARE_MSM_GPIO_PINS(89); |
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DECLARE_MSM_GPIO_PINS(90); |
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DECLARE_MSM_GPIO_PINS(91); |
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DECLARE_MSM_GPIO_PINS(92); |
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DECLARE_MSM_GPIO_PINS(93); |
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DECLARE_MSM_GPIO_PINS(94); |
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DECLARE_MSM_GPIO_PINS(95); |
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DECLARE_MSM_GPIO_PINS(96); |
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DECLARE_MSM_GPIO_PINS(97); |
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DECLARE_MSM_GPIO_PINS(98); |
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DECLARE_MSM_GPIO_PINS(99); |
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DECLARE_MSM_GPIO_PINS(100); |
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DECLARE_MSM_GPIO_PINS(101); |
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DECLARE_MSM_GPIO_PINS(102); |
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DECLARE_MSM_GPIO_PINS(103); |
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DECLARE_MSM_GPIO_PINS(104); |
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DECLARE_MSM_GPIO_PINS(105); |
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DECLARE_MSM_GPIO_PINS(106); |
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DECLARE_MSM_GPIO_PINS(107); |
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static const unsigned int sdc1_rclk_pins[] = { 108 }; |
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static const unsigned int sdc1_clk_pins[] = { 109 }; |
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static const unsigned int sdc1_cmd_pins[] = { 110 }; |
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static const unsigned int sdc1_data_pins[] = { 111 }; |
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enum sdx55_functions { |
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msm_mux_adsp_ext, |
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msm_mux_atest, |
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msm_mux_audio_ref, |
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msm_mux_bimc_dte0, |
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msm_mux_bimc_dte1, |
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msm_mux_blsp_i2c1, |
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msm_mux_blsp_i2c2, |
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msm_mux_blsp_i2c3, |
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msm_mux_blsp_i2c4, |
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msm_mux_blsp_spi1, |
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msm_mux_blsp_spi2, |
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msm_mux_blsp_spi3, |
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msm_mux_blsp_spi4, |
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msm_mux_blsp_uart1, |
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msm_mux_blsp_uart2, |
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msm_mux_blsp_uart3, |
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msm_mux_blsp_uart4, |
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msm_mux_char_exec, |
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msm_mux_coex_uart, |
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msm_mux_coex_uart2, |
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msm_mux_cri_trng, |
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msm_mux_cri_trng0, |
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msm_mux_cri_trng1, |
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msm_mux_dbg_out, |
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msm_mux_ddr_bist, |
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msm_mux_ddr_pxi0, |
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msm_mux_ebi0_wrcdc, |
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msm_mux_ebi2_a, |
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msm_mux_ebi2_lcd, |
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msm_mux_emac_gcc0, |
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msm_mux_emac_gcc1, |
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msm_mux_emac_pps0, |
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msm_mux_emac_pps1, |
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msm_mux_ext_dbg, |
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msm_mux_gcc_gp1, |
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msm_mux_gcc_gp2, |
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msm_mux_gcc_gp3, |
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msm_mux_gcc_plltest, |
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msm_mux_gpio, |
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msm_mux_i2s_mclk, |
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msm_mux_jitter_bist, |
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msm_mux_ldo_en, |
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msm_mux_ldo_update, |
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msm_mux_mgpi_clk, |
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msm_mux_m_voc, |
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msm_mux_native_char, |
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msm_mux_native_char0, |
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msm_mux_native_char1, |
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msm_mux_native_char2, |
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msm_mux_native_char3, |
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msm_mux_native_tsens, |
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msm_mux_native_tsense, |
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msm_mux_nav_gpio, |
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msm_mux_pa_indicator, |
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msm_mux_pcie_clkreq, |
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msm_mux_pci_e, |
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msm_mux_pll_bist, |
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msm_mux_pll_ref, |
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msm_mux_pll_test, |
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msm_mux_pri_mi2s, |
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msm_mux_prng_rosc, |
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msm_mux_qdss_cti, |
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msm_mux_qdss_gpio, |
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msm_mux_qdss_stm, |
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msm_mux_qlink0_en, |
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msm_mux_qlink0_req, |
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msm_mux_qlink0_wmss, |
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msm_mux_qlink1_en, |
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msm_mux_qlink1_req, |
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msm_mux_qlink1_wmss, |
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msm_mux_spmi_coex, |
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msm_mux_sec_mi2s, |
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msm_mux_spmi_vgi, |
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msm_mux_tgu_ch0, |
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msm_mux_uim1_clk, |
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msm_mux_uim1_data, |
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msm_mux_uim1_present, |
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msm_mux_uim1_reset, |
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msm_mux_uim2_clk, |
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msm_mux_uim2_data, |
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msm_mux_uim2_present, |
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msm_mux_uim2_reset, |
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msm_mux_usb2phy_ac, |
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msm_mux_vsense_trigger, |
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msm_mux__, |
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}; |
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static const char * const gpio_groups[] = { |
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", |
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", |
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"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", |
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"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", |
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"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", |
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"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", |
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"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", |
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"gpio50", "gpio51", "gpio52", "gpio52", "gpio53", "gpio53", "gpio54", |
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"gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", |
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"gpio62", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", |
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"gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", |
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"gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", |
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"gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", |
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"gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", |
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"gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", |
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"gpio103", "gpio104", "gpio105", "gpio106", "gpio107", |
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}; |
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static const char * const qdss_stm_groups[] = { |
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", |
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"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", |
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"gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62", |
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"gpio63", "gpio64", "gpio65", "gpio66", |
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}; |
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static const char * const ddr_pxi0_groups[] = { |
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"gpio45", "gpio46", |
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}; |
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static const char * const m_voc_groups[] = { |
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"gpio46", "gpio48", "gpio49", "gpio59", "gpio60", |
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}; |
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static const char * const ddr_bist_groups[] = { |
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"gpio46", "gpio47", "gpio48", "gpio49", |
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}; |
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static const char * const blsp_spi1_groups[] = { |
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"gpio52", "gpio62", "gpio71", "gpio80", "gpio81", "gpio82", "gpio83", |
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}; |
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static const char * const pci_e_groups[] = { |
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"gpio53", |
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}; |
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static const char * const tgu_ch0_groups[] = { |
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"gpio55", |
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}; |
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static const char * const pcie_clkreq_groups[] = { |
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"gpio56", |
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}; |
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static const char * const mgpi_clk_groups[] = { |
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"gpio61", "gpio71", |
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}; |
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static const char * const i2s_mclk_groups[] = { |
|
"gpio62", |
|
}; |
|
|
|
static const char * const audio_ref_groups[] = { |
|
"gpio62", |
|
}; |
|
|
|
static const char * const ldo_update_groups[] = { |
|
"gpio62", |
|
}; |
|
|
|
static const char * const atest_groups[] = { |
|
"gpio63", "gpio64", "gpio65", "gpio66", "gpio67", |
|
}; |
|
|
|
static const char * const uim1_data_groups[] = { |
|
"gpio67", |
|
}; |
|
|
|
static const char * const uim1_present_groups[] = { |
|
"gpio68", |
|
}; |
|
|
|
static const char * const uim1_reset_groups[] = { |
|
"gpio69", |
|
}; |
|
|
|
static const char * const uim1_clk_groups[] = { |
|
"gpio70", |
|
}; |
|
|
|
static const char * const qlink1_en_groups[] = { |
|
"gpio72", |
|
}; |
|
|
|
static const char * const qlink1_req_groups[] = { |
|
"gpio73", |
|
}; |
|
|
|
static const char * const qlink1_wmss_groups[] = { |
|
"gpio74", |
|
}; |
|
|
|
static const char * const coex_uart2_groups[] = { |
|
"gpio75", "gpio76", |
|
}; |
|
|
|
static const char * const spmi_vgi_groups[] = { |
|
"gpio78", "gpio79", |
|
}; |
|
|
|
static const char * const gcc_plltest_groups[] = { |
|
"gpio81", "gpio82", |
|
}; |
|
|
|
static const char * const usb2phy_ac_groups[] = { |
|
"gpio93", |
|
}; |
|
|
|
static const char * const emac_pps1_groups[] = { |
|
"gpio95", |
|
}; |
|
|
|
static const char * const emac_pps0_groups[] = { |
|
"gpio106", |
|
}; |
|
|
|
static const char * const uim2_data_groups[] = { |
|
"gpio0", |
|
}; |
|
|
|
static const char * const ebi0_wrcdc_groups[] = { |
|
"gpio0", "gpio2", |
|
}; |
|
|
|
static const char * const uim2_present_groups[] = { |
|
"gpio1", |
|
}; |
|
|
|
static const char * const blsp_uart1_groups[] = { |
|
"gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio22", |
|
"gpio23", |
|
}; |
|
|
|
static const char * const uim2_reset_groups[] = { |
|
"gpio2", |
|
}; |
|
|
|
static const char * const blsp_i2c1_groups[] = { |
|
"gpio2", "gpio3", "gpio82", "gpio83", |
|
}; |
|
|
|
static const char * const uim2_clk_groups[] = { |
|
"gpio3", |
|
}; |
|
|
|
static const char * const blsp_spi2_groups[] = { |
|
"gpio4", "gpio5", "gpio6", "gpio7", "gpio52", "gpio62", "gpio71", |
|
}; |
|
|
|
static const char * const blsp_uart2_groups[] = { |
|
"gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", |
|
"gpio66", |
|
}; |
|
|
|
static const char * const blsp_i2c2_groups[] = { |
|
"gpio6", "gpio7", "gpio65", "gpio66", |
|
}; |
|
|
|
static const char * const char_exec_groups[] = { |
|
"gpio6", "gpio7", |
|
}; |
|
|
|
static const char * const pri_mi2s_groups[] = { |
|
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", |
|
"gpio15", |
|
}; |
|
|
|
static const char * const blsp_spi3_groups[] = { |
|
"gpio8", "gpio9", "gpio10", "gpio11", "gpio52", "gpio62", "gpio71", |
|
}; |
|
|
|
static const char * const blsp_uart3_groups[] = { |
|
"gpio8", "gpio9", "gpio10", "gpio11", |
|
}; |
|
|
|
static const char * const ext_dbg_groups[] = { |
|
"gpio8", "gpio9", "gpio10", "gpio11", |
|
}; |
|
|
|
static const char * const ldo_en_groups[] = { |
|
"gpio8", |
|
}; |
|
|
|
static const char * const blsp_i2c3_groups[] = { |
|
"gpio10", "gpio11", |
|
}; |
|
|
|
static const char * const gcc_gp3_groups[] = { |
|
"gpio11", |
|
}; |
|
|
|
static const char * const emac_gcc1_groups[] = { |
|
"gpio14", |
|
}; |
|
|
|
static const char * const bimc_dte0_groups[] = { |
|
"gpio14", "gpio59", |
|
}; |
|
|
|
static const char * const native_tsens_groups[] = { |
|
"gpio14", |
|
}; |
|
|
|
static const char * const vsense_trigger_groups[] = { |
|
"gpio14", |
|
}; |
|
|
|
static const char * const emac_gcc0_groups[] = { |
|
"gpio15", |
|
}; |
|
|
|
static const char * const bimc_dte1_groups[] = { |
|
"gpio15", "gpio61", |
|
}; |
|
|
|
static const char * const sec_mi2s_groups[] = { |
|
"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", |
|
"gpio23", |
|
}; |
|
|
|
static const char * const blsp_spi4_groups[] = { |
|
"gpio16", "gpio17", "gpio18", "gpio19", "gpio52", "gpio62", "gpio71", |
|
}; |
|
|
|
static const char * const blsp_uart4_groups[] = { |
|
"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", |
|
"gpio23", |
|
}; |
|
|
|
static const char * const qdss_cti_groups[] = { |
|
"gpio16", "gpio16", "gpio17", "gpio17", "gpio22", "gpio22", "gpio23", |
|
"gpio23", "gpio54", "gpio54", "gpio55", "gpio55", "gpio59", "gpio60", |
|
"gpio94", "gpio94", "gpio95", "gpio95", |
|
}; |
|
|
|
static const char * const blsp_i2c4_groups[] = { |
|
"gpio18", "gpio19", "gpio78", "gpio79", |
|
}; |
|
|
|
static const char * const gcc_gp1_groups[] = { |
|
"gpio18", |
|
}; |
|
|
|
static const char * const jitter_bist_groups[] = { |
|
"gpio19", |
|
}; |
|
|
|
static const char * const gcc_gp2_groups[] = { |
|
"gpio19", |
|
}; |
|
|
|
static const char * const ebi2_a_groups[] = { |
|
"gpio20", |
|
}; |
|
|
|
static const char * const ebi2_lcd_groups[] = { |
|
"gpio21", "gpio22", "gpio23", |
|
}; |
|
|
|
static const char * const pll_bist_groups[] = { |
|
"gpio22", |
|
}; |
|
|
|
static const char * const adsp_ext_groups[] = { |
|
"gpio24", "gpio25", |
|
}; |
|
|
|
static const char * const native_char_groups[] = { |
|
"gpio26", |
|
}; |
|
|
|
static const char * const qlink0_wmss_groups[] = { |
|
"gpio28", |
|
}; |
|
|
|
static const char * const native_char3_groups[] = { |
|
"gpio28", |
|
}; |
|
|
|
static const char * const native_char2_groups[] = { |
|
"gpio29", |
|
}; |
|
|
|
static const char * const native_tsense_groups[] = { |
|
"gpio29", |
|
}; |
|
|
|
static const char * const nav_gpio_groups[] = { |
|
"gpio31", "gpio32", "gpio76", |
|
}; |
|
|
|
static const char * const pll_ref_groups[] = { |
|
"gpio32", |
|
}; |
|
|
|
static const char * const pa_indicator_groups[] = { |
|
"gpio33", |
|
}; |
|
|
|
static const char * const native_char0_groups[] = { |
|
"gpio33", |
|
}; |
|
|
|
static const char * const qlink0_en_groups[] = { |
|
"gpio34", |
|
}; |
|
|
|
static const char * const qlink0_req_groups[] = { |
|
"gpio35", |
|
}; |
|
|
|
static const char * const pll_test_groups[] = { |
|
"gpio35", |
|
}; |
|
|
|
static const char * const cri_trng_groups[] = { |
|
"gpio36", |
|
}; |
|
|
|
static const char * const dbg_out_groups[] = { |
|
"gpio36", |
|
}; |
|
|
|
static const char * const prng_rosc_groups[] = { |
|
"gpio38", |
|
}; |
|
|
|
static const char * const cri_trng0_groups[] = { |
|
"gpio40", |
|
}; |
|
|
|
static const char * const cri_trng1_groups[] = { |
|
"gpio41", |
|
}; |
|
|
|
static const char * const qdss_gpio_groups[] = { |
|
"gpio4", "gpio5", "gpio6", "gpio7", |
|
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", |
|
"gpio42", "gpio61", "gpio63", "gpio64", "gpio65", "gpio66", |
|
}; |
|
|
|
static const char * const native_char1_groups[] = { |
|
"gpio42", |
|
}; |
|
|
|
static const char * const coex_uart_groups[] = { |
|
"gpio44", "gpio45", |
|
}; |
|
|
|
static const char * const spmi_coex_groups[] = { |
|
"gpio44", "gpio45", |
|
}; |
|
|
|
static const struct msm_function sdx55_functions[] = { |
|
FUNCTION(adsp_ext), |
|
FUNCTION(atest), |
|
FUNCTION(audio_ref), |
|
FUNCTION(bimc_dte0), |
|
FUNCTION(bimc_dte1), |
|
FUNCTION(blsp_i2c1), |
|
FUNCTION(blsp_i2c2), |
|
FUNCTION(blsp_i2c3), |
|
FUNCTION(blsp_i2c4), |
|
FUNCTION(blsp_spi1), |
|
FUNCTION(blsp_spi2), |
|
FUNCTION(blsp_spi3), |
|
FUNCTION(blsp_spi4), |
|
FUNCTION(blsp_uart1), |
|
FUNCTION(blsp_uart2), |
|
FUNCTION(blsp_uart3), |
|
FUNCTION(blsp_uart4), |
|
FUNCTION(char_exec), |
|
FUNCTION(coex_uart), |
|
FUNCTION(coex_uart2), |
|
FUNCTION(cri_trng), |
|
FUNCTION(cri_trng0), |
|
FUNCTION(cri_trng1), |
|
FUNCTION(dbg_out), |
|
FUNCTION(ddr_bist), |
|
FUNCTION(ddr_pxi0), |
|
FUNCTION(ebi0_wrcdc), |
|
FUNCTION(ebi2_a), |
|
FUNCTION(ebi2_lcd), |
|
FUNCTION(emac_gcc0), |
|
FUNCTION(emac_gcc1), |
|
FUNCTION(emac_pps0), |
|
FUNCTION(emac_pps1), |
|
FUNCTION(ext_dbg), |
|
FUNCTION(gcc_gp1), |
|
FUNCTION(gcc_gp2), |
|
FUNCTION(gcc_gp3), |
|
FUNCTION(gcc_plltest), |
|
FUNCTION(gpio), |
|
FUNCTION(i2s_mclk), |
|
FUNCTION(jitter_bist), |
|
FUNCTION(ldo_en), |
|
FUNCTION(ldo_update), |
|
FUNCTION(mgpi_clk), |
|
FUNCTION(m_voc), |
|
FUNCTION(native_char), |
|
FUNCTION(native_char0), |
|
FUNCTION(native_char1), |
|
FUNCTION(native_char2), |
|
FUNCTION(native_char3), |
|
FUNCTION(native_tsens), |
|
FUNCTION(native_tsense), |
|
FUNCTION(nav_gpio), |
|
FUNCTION(pa_indicator), |
|
FUNCTION(pcie_clkreq), |
|
FUNCTION(pci_e), |
|
FUNCTION(pll_bist), |
|
FUNCTION(pll_ref), |
|
FUNCTION(pll_test), |
|
FUNCTION(pri_mi2s), |
|
FUNCTION(prng_rosc), |
|
FUNCTION(qdss_cti), |
|
FUNCTION(qdss_gpio), |
|
FUNCTION(qdss_stm), |
|
FUNCTION(qlink0_en), |
|
FUNCTION(qlink0_req), |
|
FUNCTION(qlink0_wmss), |
|
FUNCTION(qlink1_en), |
|
FUNCTION(qlink1_req), |
|
FUNCTION(qlink1_wmss), |
|
FUNCTION(spmi_coex), |
|
FUNCTION(sec_mi2s), |
|
FUNCTION(spmi_vgi), |
|
FUNCTION(tgu_ch0), |
|
FUNCTION(uim1_clk), |
|
FUNCTION(uim1_data), |
|
FUNCTION(uim1_present), |
|
FUNCTION(uim1_reset), |
|
FUNCTION(uim2_clk), |
|
FUNCTION(uim2_data), |
|
FUNCTION(uim2_present), |
|
FUNCTION(uim2_reset), |
|
FUNCTION(usb2phy_ac), |
|
FUNCTION(vsense_trigger), |
|
}; |
|
|
|
/* Every pin is maintained as a single group, and missing or non-existing pin |
|
* would be maintained as dummy group to synchronize pin group index with |
|
* pin descriptor registered with pinctrl core. |
|
* Clients would not be able to request these dummy pin groups. |
|
*/ |
|
static const struct msm_pingroup sdx55_groups[] = { |
|
[0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _), |
|
[1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _), |
|
[2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _), |
|
[3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _), |
|
[4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), |
|
[5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), |
|
[6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), |
|
[7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), |
|
[8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _), |
|
[9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _), |
|
[10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _), |
|
[11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _), |
|
[12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), |
|
[13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), |
|
[14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger), |
|
[15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _), |
|
[16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio), |
|
[17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _), |
|
[18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _), |
|
[19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio), |
|
[20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _), |
|
[21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _), |
|
[22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm), |
|
[23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _), |
|
[24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), |
|
[25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), |
|
[26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), |
|
[27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), |
|
[28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _), |
|
[29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _), |
|
[30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), |
|
[31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), |
|
[32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), |
|
[33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _), |
|
[34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), |
|
[35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _), |
|
[36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _), |
|
[37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), |
|
[38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), |
|
[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), |
|
[40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), |
|
[41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), |
|
[42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _), |
|
[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), |
|
[44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _), |
|
[45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _), |
|
[46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), |
|
[47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _), |
|
[48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _), |
|
[49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _), |
|
[50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), |
|
[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), |
|
[52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _), |
|
[53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _), |
|
[54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), |
|
[55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), |
|
[56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _), |
|
[57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _), |
|
[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), |
|
[59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), |
|
[60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), |
|
[61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _), |
|
[62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _), |
|
[63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _), |
|
[64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _), |
|
[65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _), |
|
[66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _), |
|
[67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _), |
|
[68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), |
|
[69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), |
|
[70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), |
|
[71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), |
|
[72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _), |
|
[73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), |
|
[74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), |
|
[75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _), |
|
[76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _), |
|
[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), |
|
[78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), |
|
[79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), |
|
[80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _), |
|
[81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _), |
|
[82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), |
|
[83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), |
|
[84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), |
|
[85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), |
|
[86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), |
|
[87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), |
|
[88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), |
|
[89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), |
|
[90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), |
|
[91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), |
|
[92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), |
|
[93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), |
|
[94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), |
|
[95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _), |
|
[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), |
|
[97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), |
|
[98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), |
|
[99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), |
|
[100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), |
|
[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), |
|
[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), |
|
[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _), |
|
[104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), |
|
[105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), |
|
[106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _), |
|
[107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), |
|
[109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), |
|
[110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6), |
|
[111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), |
|
[112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0), |
|
}; |
|
|
|
static const struct msm_pinctrl_soc_data sdx55_pinctrl = { |
|
.pins = sdx55_pins, |
|
.npins = ARRAY_SIZE(sdx55_pins), |
|
.functions = sdx55_functions, |
|
.nfunctions = ARRAY_SIZE(sdx55_functions), |
|
.groups = sdx55_groups, |
|
.ngroups = ARRAY_SIZE(sdx55_groups), |
|
.ngpios = 108, |
|
}; |
|
|
|
static int sdx55_pinctrl_probe(struct platform_device *pdev) |
|
{ |
|
return msm_pinctrl_probe(pdev, &sdx55_pinctrl); |
|
} |
|
|
|
static const struct of_device_id sdx55_pinctrl_of_match[] = { |
|
{ .compatible = "qcom,sdx55-pinctrl", }, |
|
{ }, |
|
}; |
|
|
|
static struct platform_driver sdx55_pinctrl_driver = { |
|
.driver = { |
|
.name = "sdx55-pinctrl", |
|
.of_match_table = sdx55_pinctrl_of_match, |
|
}, |
|
.probe = sdx55_pinctrl_probe, |
|
.remove = msm_pinctrl_remove, |
|
}; |
|
|
|
static int __init sdx55_pinctrl_init(void) |
|
{ |
|
return platform_driver_register(&sdx55_pinctrl_driver); |
|
} |
|
arch_initcall(sdx55_pinctrl_init); |
|
|
|
static void __exit sdx55_pinctrl_exit(void) |
|
{ |
|
platform_driver_unregister(&sdx55_pinctrl_driver); |
|
} |
|
module_exit(sdx55_pinctrl_exit); |
|
|
|
MODULE_DESCRIPTION("QTI sdx55 pinctrl driver"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match);
|
|
|