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164 lines
4.8 KiB
164 lines
4.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
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* |
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* GPIO and pin control functions on this SOC are handled by the "TLMM" |
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* device. The driver which controls this device is pinctrl-msm.c. Each |
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* SOC with a TLMM is expected to create a client driver that registers |
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* with pinctrl-msm.c. This means that all TLMM drivers are pin control |
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* drivers. |
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* |
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* This pin control driver is intended to be used only an ACPI-enabled |
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* system. As such, UEFI will handle all pin control configuration, so |
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* this driver does not provide pin control functions. It is effectively |
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* a GPIO-only driver. The alternative is to duplicate the GPIO code of |
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* pinctrl-msm.c into another driver. |
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*/ |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pinctrl/pinctrl.h> |
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#include <linux/acpi.h> |
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#include "pinctrl-msm.h" |
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/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */ |
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#define MAX_GPIOS 256 |
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/* maximum size of each gpio name (enough room for "gpioXXX" + null) */ |
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#define NAME_SIZE 8 |
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static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) |
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{ |
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struct msm_pinctrl_soc_data *pinctrl; |
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struct pinctrl_pin_desc *pins; |
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struct msm_pingroup *groups; |
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char (*names)[NAME_SIZE]; |
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unsigned int i; |
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u32 num_gpios; |
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unsigned int avail_gpios; /* The number of GPIOs we support */ |
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u8 gpios[MAX_GPIOS]; /* An array of supported GPIOs */ |
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int ret; |
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/* Query the number of GPIOs from ACPI */ |
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ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "missing 'num-gpios' property\n"); |
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return ret; |
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} |
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if (!num_gpios || num_gpios > MAX_GPIOS) { |
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dev_err(&pdev->dev, "invalid 'num-gpios' property\n"); |
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return -ENODEV; |
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} |
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/* The number of GPIOs in the approved list */ |
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ret = device_property_count_u8(&pdev->dev, "gpios"); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "missing 'gpios' property\n"); |
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return ret; |
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} |
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/* |
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* The number of available GPIOs should be non-zero, and no |
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* more than the total number of GPIOS. |
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*/ |
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if (!ret || ret > num_gpios) { |
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dev_err(&pdev->dev, "invalid 'gpios' property\n"); |
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return -ENODEV; |
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} |
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avail_gpios = ret; |
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ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios, |
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avail_gpios); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "could not read list of GPIOs\n"); |
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return ret; |
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} |
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pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); |
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pins = devm_kcalloc(&pdev->dev, num_gpios, |
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sizeof(struct pinctrl_pin_desc), GFP_KERNEL); |
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groups = devm_kcalloc(&pdev->dev, num_gpios, |
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sizeof(struct msm_pingroup), GFP_KERNEL); |
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names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL); |
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if (!pinctrl || !pins || !groups || !names) |
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return -ENOMEM; |
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/* |
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* Initialize the array. GPIOs not listed in the 'gpios' array |
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* still need a number, but nothing else. |
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*/ |
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for (i = 0; i < num_gpios; i++) { |
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pins[i].number = i; |
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groups[i].pins = &pins[i].number; |
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} |
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/* Populate the entries that are meant to be exposed as GPIOs. */ |
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for (i = 0; i < avail_gpios; i++) { |
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unsigned int gpio = gpios[i]; |
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groups[gpio].npins = 1; |
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snprintf(names[i], NAME_SIZE, "gpio%u", gpio); |
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pins[gpio].name = names[i]; |
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groups[gpio].name = names[i]; |
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groups[gpio].ctl_reg = 0x10000 * gpio; |
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groups[gpio].io_reg = 0x04 + 0x10000 * gpio; |
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groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; |
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groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; |
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groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; |
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groups[gpio].mux_bit = 2; |
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groups[gpio].pull_bit = 0; |
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groups[gpio].drv_bit = 6; |
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groups[gpio].oe_bit = 9; |
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groups[gpio].in_bit = 0; |
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groups[gpio].out_bit = 1; |
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groups[gpio].intr_enable_bit = 0; |
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groups[gpio].intr_status_bit = 0; |
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groups[gpio].intr_target_bit = 5; |
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groups[gpio].intr_target_kpss_val = 1; |
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groups[gpio].intr_raw_status_bit = 4; |
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groups[gpio].intr_polarity_bit = 1; |
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groups[gpio].intr_detection_bit = 2; |
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groups[gpio].intr_detection_width = 2; |
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} |
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pinctrl->pins = pins; |
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pinctrl->groups = groups; |
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pinctrl->npins = num_gpios; |
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pinctrl->ngroups = num_gpios; |
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pinctrl->ngpios = num_gpios; |
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return msm_pinctrl_probe(pdev, pinctrl); |
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} |
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static const struct acpi_device_id qdf2xxx_acpi_ids[] = { |
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{"QCOM8002"}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); |
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static struct platform_driver qdf2xxx_pinctrl_driver = { |
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.driver = { |
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.name = "qdf2xxx-pinctrl", |
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.acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids), |
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}, |
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.probe = qdf2xxx_pinctrl_probe, |
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.remove = msm_pinctrl_remove, |
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}; |
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static int __init qdf2xxx_pinctrl_init(void) |
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{ |
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return platform_driver_register(&qdf2xxx_pinctrl_driver); |
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} |
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arch_initcall(qdf2xxx_pinctrl_init); |
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static void __exit qdf2xxx_pinctrl_exit(void) |
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{ |
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platform_driver_unregister(&qdf2xxx_pinctrl_driver); |
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} |
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module_exit(qdf2xxx_pinctrl_exit); |
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MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver"); |
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MODULE_LICENSE("GPL v2");
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