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272 lines
7.9 KiB
272 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/time.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/slab.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy/phy.h> |
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/* PHY registers */ |
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#define UNIPHY_PLL_REFCLK_CFG 0x000 |
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#define UNIPHY_PLL_PWRGEN_CFG 0x014 |
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#define UNIPHY_PLL_GLB_CFG 0x020 |
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#define UNIPHY_PLL_SDM_CFG0 0x038 |
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#define UNIPHY_PLL_SDM_CFG1 0x03C |
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#define UNIPHY_PLL_SDM_CFG2 0x040 |
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#define UNIPHY_PLL_SDM_CFG3 0x044 |
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#define UNIPHY_PLL_SDM_CFG4 0x048 |
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#define UNIPHY_PLL_SSC_CFG0 0x04C |
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#define UNIPHY_PLL_SSC_CFG1 0x050 |
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#define UNIPHY_PLL_SSC_CFG2 0x054 |
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#define UNIPHY_PLL_SSC_CFG3 0x058 |
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#define UNIPHY_PLL_LKDET_CFG0 0x05C |
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#define UNIPHY_PLL_LKDET_CFG1 0x060 |
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#define UNIPHY_PLL_LKDET_CFG2 0x064 |
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#define UNIPHY_PLL_CAL_CFG0 0x06C |
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#define UNIPHY_PLL_CAL_CFG8 0x08C |
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#define UNIPHY_PLL_CAL_CFG9 0x090 |
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#define UNIPHY_PLL_CAL_CFG10 0x094 |
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#define UNIPHY_PLL_CAL_CFG11 0x098 |
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#define UNIPHY_PLL_STATUS 0x0C0 |
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#define SATA_PHY_SER_CTRL 0x100 |
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#define SATA_PHY_TX_DRIV_CTRL0 0x104 |
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#define SATA_PHY_TX_DRIV_CTRL1 0x108 |
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#define SATA_PHY_TX_IMCAL0 0x11C |
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#define SATA_PHY_TX_IMCAL2 0x124 |
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#define SATA_PHY_RX_IMCAL0 0x128 |
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#define SATA_PHY_EQUAL 0x13C |
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#define SATA_PHY_OOB_TERM 0x144 |
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#define SATA_PHY_CDR_CTRL0 0x148 |
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#define SATA_PHY_CDR_CTRL1 0x14C |
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#define SATA_PHY_CDR_CTRL2 0x150 |
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#define SATA_PHY_CDR_CTRL3 0x154 |
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#define SATA_PHY_PI_CTRL0 0x168 |
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#define SATA_PHY_POW_DWN_CTRL0 0x180 |
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#define SATA_PHY_POW_DWN_CTRL1 0x184 |
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#define SATA_PHY_TX_DATA_CTRL 0x188 |
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#define SATA_PHY_ALIGNP 0x1A4 |
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#define SATA_PHY_TX_IMCAL_STAT 0x1E4 |
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#define SATA_PHY_RX_IMCAL_STAT 0x1E8 |
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#define UNIPHY_PLL_LOCK BIT(0) |
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#define SATA_PHY_TX_CAL BIT(0) |
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#define SATA_PHY_RX_CAL BIT(0) |
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/* default timeout set to 1 sec */ |
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#define TIMEOUT_MS 10000 |
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#define DELAY_INTERVAL_US 100 |
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struct qcom_apq8064_sata_phy { |
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void __iomem *mmio; |
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struct clk *cfg_clk; |
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struct device *dev; |
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}; |
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/* Helper function to do poll and timeout */ |
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static int poll_timeout(void __iomem *addr, u32 mask) |
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{ |
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u32 val; |
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return readl_relaxed_poll_timeout(addr, val, (val & mask), |
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DELAY_INTERVAL_US, TIMEOUT_MS * 1000); |
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} |
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static int qcom_apq8064_sata_phy_init(struct phy *generic_phy) |
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{ |
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struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy); |
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void __iomem *base = phy->mmio; |
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int ret = 0; |
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/* SATA phy initialization */ |
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writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); |
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writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); |
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/* Make sure the power down happens before power up */ |
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mb(); |
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usleep_range(10, 60); |
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writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); |
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writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); |
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writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); |
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writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); |
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writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); |
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/* Write UNIPHYPLL registers to configure PLL */ |
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writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); |
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writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); |
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writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0); |
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writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8); |
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writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9); |
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writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10); |
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writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11); |
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writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0); |
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writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1); |
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writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2); |
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writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3); |
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writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4); |
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writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0); |
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writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1); |
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writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2); |
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writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3); |
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writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0); |
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writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1); |
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writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG); |
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/* make sure global config LDO power down happens before power up */ |
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mb(); |
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writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG); |
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writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2); |
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/* PLL Lock wait */ |
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ret = poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); |
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if (ret) { |
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dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n"); |
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return ret; |
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} |
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/* TX Calibration */ |
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ret = poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); |
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if (ret) { |
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dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n"); |
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return ret; |
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} |
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/* RX Calibration */ |
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ret = poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); |
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if (ret) { |
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dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n"); |
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return ret; |
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} |
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/* SATA phy calibrated succesfully, power up to functional mode */ |
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writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); |
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writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); |
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writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); |
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writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1); |
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writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0); |
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writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1); |
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writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2); |
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writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0); |
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writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3); |
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writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); |
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writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL); |
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writel_relaxed(0x43, base + SATA_PHY_ALIGNP); |
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writel_relaxed(0x04, base + SATA_PHY_OOB_TERM); |
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writel_relaxed(0x01, base + SATA_PHY_EQUAL); |
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writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0); |
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writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1); |
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return 0; |
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} |
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static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy) |
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{ |
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struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy); |
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void __iomem *base = phy->mmio; |
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/* Power down PHY */ |
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writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0); |
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writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1); |
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/* Power down PLL block */ |
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writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG); |
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return 0; |
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} |
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static const struct phy_ops qcom_apq8064_sata_phy_ops = { |
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.init = qcom_apq8064_sata_phy_init, |
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.exit = qcom_apq8064_sata_phy_exit, |
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.owner = THIS_MODULE, |
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}; |
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static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev) |
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{ |
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struct qcom_apq8064_sata_phy *phy; |
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struct device *dev = &pdev->dev; |
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struct phy_provider *phy_provider; |
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struct phy *generic_phy; |
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int ret; |
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); |
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if (!phy) |
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return -ENOMEM; |
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phy->mmio = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(phy->mmio)) |
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return PTR_ERR(phy->mmio); |
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generic_phy = devm_phy_create(dev, NULL, &qcom_apq8064_sata_phy_ops); |
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if (IS_ERR(generic_phy)) { |
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dev_err(dev, "%s: failed to create phy\n", __func__); |
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return PTR_ERR(generic_phy); |
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} |
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phy->dev = dev; |
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phy_set_drvdata(generic_phy, phy); |
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platform_set_drvdata(pdev, phy); |
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phy->cfg_clk = devm_clk_get(dev, "cfg"); |
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if (IS_ERR(phy->cfg_clk)) { |
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dev_err(dev, "Failed to get sata cfg clock\n"); |
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return PTR_ERR(phy->cfg_clk); |
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} |
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ret = clk_prepare_enable(phy->cfg_clk); |
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if (ret) |
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return ret; |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(phy_provider)) { |
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clk_disable_unprepare(phy->cfg_clk); |
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dev_err(dev, "%s: failed to register phy\n", __func__); |
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return PTR_ERR(phy_provider); |
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} |
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return 0; |
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} |
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static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev) |
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{ |
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struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev); |
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clk_disable_unprepare(phy->cfg_clk); |
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return 0; |
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} |
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static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = { |
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{ .compatible = "qcom,apq8064-sata-phy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match); |
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static struct platform_driver qcom_apq8064_sata_phy_driver = { |
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.probe = qcom_apq8064_sata_phy_probe, |
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.remove = qcom_apq8064_sata_phy_remove, |
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.driver = { |
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.name = "qcom-apq8064-sata-phy", |
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.of_match_table = qcom_apq8064_sata_phy_of_match, |
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} |
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}; |
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module_platform_driver(qcom_apq8064_sata_phy_driver); |
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MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver"); |
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MODULE_LICENSE("GPL v2");
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