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720 lines
28 KiB
720 lines
28 KiB
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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/* |
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* Copyright (C) 2005-2014, 2018-2020 Intel Corporation |
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* Copyright (C) 2015-2017 Intel Deutschland GmbH |
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*/ |
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#ifndef __iwl_fh_h__ |
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#define __iwl_fh_h__ |
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#include <linux/types.h> |
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#include <linux/bitfield.h> |
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#include "iwl-trans.h" |
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/****************************/ |
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/* Flow Handler Definitions */ |
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/****************************/ |
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/** |
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* This I/O area is directly read/writable by driver (e.g. Linux uses writel()) |
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* Addresses are offsets from device's PCI hardware base address. |
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*/ |
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#define FH_MEM_LOWER_BOUND (0x1000) |
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#define FH_MEM_UPPER_BOUND (0x2000) |
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#define FH_MEM_LOWER_BOUND_GEN2 (0xa06000) |
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#define FH_MEM_UPPER_BOUND_GEN2 (0xa08000) |
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/** |
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* Keep-Warm (KW) buffer base address. |
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* |
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* Driver must allocate a 4KByte buffer that is for keeping the |
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* host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency |
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* DRAM access when doing Txing or Rxing. The dummy accesses prevent host |
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* from going into a power-savings mode that would cause higher DRAM latency, |
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* and possible data over/under-runs, before all Tx/Rx is complete. |
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* |
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* Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) |
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* of the buffer, which must be 4K aligned. Once this is set up, the device |
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* automatically invokes keep-warm accesses when normal accesses might not |
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* be sufficient to maintain fast DRAM response. |
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* |
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* Bit fields: |
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* 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned |
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*/ |
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#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) |
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/** |
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* TFD Circular Buffers Base (CBBC) addresses |
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* |
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* Device has 16 base pointer registers, one for each of 16 host-DRAM-resident |
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* circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) |
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* (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 |
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* bytes from one another. Each TFD circular buffer in DRAM must be 256-byte |
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* aligned (address bits 0-7 must be 0). |
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* Later devices have 20 (5000 series) or 30 (higher) queues, but the registers |
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* for them are in different places. |
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* |
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* Bit fields in each pointer register: |
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* 27-0: TFD CB physical base address [35:8], must be 256-byte aligned |
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*/ |
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#define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) |
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#define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) |
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#define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) |
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#define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
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#define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) |
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#define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) |
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/* 22000 TFD table address, 64 bit */ |
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#define TFH_TFDQ_CBB_TABLE (0x1C00) |
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/* Find TFD CB base pointer for given queue */ |
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static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans, |
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unsigned int chnl) |
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{ |
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if (trans->trans_cfg->use_tfh) { |
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WARN_ON_ONCE(chnl >= 64); |
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return TFH_TFDQ_CBB_TABLE + 8 * chnl; |
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} |
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if (chnl < 16) |
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return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; |
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if (chnl < 20) |
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return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); |
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WARN_ON_ONCE(chnl >= 32); |
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return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); |
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} |
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/* 22000 configuration registers */ |
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/* |
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* TFH Configuration register. |
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* |
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* BIT fields: |
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* |
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* Bits 3:0: |
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* Define the maximum number of pending read requests. |
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* Maximum configuration value allowed is 0xC |
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* Bits 9:8: |
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* Define the maximum transfer size. (64 / 128 / 256) |
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* Bit 10: |
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* When bit is set and transfer size is set to 128B, the TFH will enable |
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* reading chunks of more than 64B only if the read address is aligned to 128B. |
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* In case of DRAM read address which is not aligned to 128B, the TFH will |
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* enable transfer size which doesn't cross 64B DRAM address boundary. |
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*/ |
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#define TFH_TRANSFER_MODE (0x1F40) |
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#define TFH_TRANSFER_MAX_PENDING_REQ 0xc |
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#define TFH_CHUNK_SIZE_128 BIT(8) |
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#define TFH_CHUNK_SPLIT_MODE BIT(10) |
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/* |
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* Defines the offset address in dwords referring from the beginning of the |
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* Tx CMD which will be updated in DRAM. |
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* Note that the TFH offset address for Tx CMD update is always referring to |
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* the start of the TFD first TB. |
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* In case of a DRAM Tx CMD update the TFH will update PN and Key ID |
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*/ |
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#define TFH_TXCMD_UPDATE_CFG (0x1F48) |
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/* |
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* Controls TX DMA operation |
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* |
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* BIT fields: |
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* |
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* Bits 31:30: Enable the SRAM DMA channel. |
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* Turning on bit 31 will kick the SRAM2DRAM DMA. |
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* Note that the sram2dram may be enabled only after configuring the DRAM and |
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* SRAM addresses registers and the byte count register. |
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* Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When |
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* set to 1 - interrupt is sent to the driver |
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* Bit 0: Indicates the snoop configuration |
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*/ |
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#define TFH_SRV_DMA_CHNL0_CTRL (0x1F60) |
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#define TFH_SRV_DMA_SNOOP BIT(0) |
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#define TFH_SRV_DMA_TO_DRIVER BIT(24) |
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#define TFH_SRV_DMA_START BIT(31) |
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/* Defines the DMA SRAM write start address to transfer a data block */ |
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#define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) |
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/* Defines the 64bits DRAM start address to read the DMA data block from */ |
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#define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) |
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/* |
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* Defines the number of bytes to transfer from DRAM to SRAM. |
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* Note that this register may be configured with non-dword aligned size. |
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*/ |
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#define TFH_SRV_DMA_CHNL0_BC (0x1F70) |
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/** |
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* Rx SRAM Control and Status Registers (RSCSR) |
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* |
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* These registers provide handshake between driver and device for the Rx queue |
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* (this queue handles *all* command responses, notifications, Rx data, etc. |
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* sent from uCode to host driver). Unlike Tx, there is only one Rx |
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* queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can |
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* concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer |
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* Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 |
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* mapping between RBDs and RBs. |
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* |
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* Driver must allocate host DRAM memory for the following, and set the |
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* physical address of each into device registers: |
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* |
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* 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 |
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* entries (although any power of 2, up to 4096, is selectable by driver). |
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* Each entry (1 dword) points to a receive buffer (RB) of consistent size |
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* (typically 4K, although 8K or 16K are also selectable by driver). |
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* Driver sets up RB size and number of RBDs in the CB via Rx config |
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* register FH_MEM_RCSR_CHNL0_CONFIG_REG. |
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* |
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* Bit fields within one RBD: |
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* 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned |
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* |
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* Driver sets physical address [35:8] of base of RBD circular buffer |
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* into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. |
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* |
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* 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers |
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* (RBs) have been filled, via a "write pointer", actually the index of |
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* the RB's corresponding RBD within the circular buffer. Driver sets |
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* physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. |
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* |
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* Bit fields in lower dword of Rx status buffer (upper dword not used |
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* by driver: |
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* 31-12: Not used by driver |
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* 11- 0: Index of last filled Rx buffer descriptor |
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* (device writes, driver reads this value) |
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* |
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* As the driver prepares Receive Buffers (RBs) for device to fill, driver must |
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* enter pointers to these RBs into contiguous RBD circular buffer entries, |
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* and update the device's "write" index register, |
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* FH_RSCSR_CHNL0_RBDCB_WPTR_REG. |
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* |
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* This "write" index corresponds to the *next* RBD that the driver will make |
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* available, i.e. one RBD past the tail of the ready-to-fill RBDs within |
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* the circular buffer. This value should initially be 0 (before preparing any |
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* RBs), should be 8 after preparing the first 8 RBs (for example), and must |
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* wrap back to 0 at the end of the circular buffer (but don't wrap before |
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* "read" index has advanced past 1! See below). |
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* NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. |
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* |
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* As the device fills RBs (referenced from contiguous RBDs within the circular |
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* buffer), it updates the Rx status buffer in host DRAM, 2) described above, |
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* to tell the driver the index of the latest filled RBD. The driver must |
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* read this "read" index from DRAM after receiving an Rx interrupt from device |
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* |
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* The driver must also internally keep track of a third index, which is the |
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* next RBD to process. When receiving an Rx interrupt, driver should process |
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* all filled but unprocessed RBs up to, but not including, the RB |
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* corresponding to the "read" index. For example, if "read" index becomes "1", |
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* driver may process the RB pointed to by RBD 0. Depending on volume of |
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* traffic, there may be many RBs to process. |
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* |
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* If read index == write index, device thinks there is no room to put new data. |
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* Due to this, the maximum number of filled RBs is 255, instead of 256. To |
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* be safe, make sure that there is a gap of at least 2 RBDs between "write" |
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* and "read" indexes; that is, make sure that there are no more than 254 |
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* buffers waiting to be filled. |
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*/ |
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#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) |
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#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
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#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) |
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/** |
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* Physical base address of 8-byte Rx Status buffer. |
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* Bit fields: |
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* 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. |
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*/ |
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#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) |
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/** |
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* Physical base address of Rx Buffer Descriptor Circular Buffer. |
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* Bit fields: |
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* 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. |
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*/ |
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#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) |
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/** |
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* Rx write pointer (index, really!). |
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* Bit fields: |
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* 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. |
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* NOTE: For 256-entry circular buffer, use only bits [7:0]. |
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*/ |
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#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) |
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#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) |
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#define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) |
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#define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG |
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/** |
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* Rx Config/Status Registers (RCSR) |
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* Rx Config Reg for channel 0 (only channel used) |
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* |
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* Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for |
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* normal operation (see bit fields). |
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* |
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* Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. |
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* Driver should poll FH_MEM_RSSR_RX_STATUS_REG for |
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* FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. |
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* |
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* Bit fields: |
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* 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, |
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* '10' operate normally |
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* 29-24: reserved |
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* 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), |
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* min "5" for 32 RBDs, max "12" for 4096 RBDs. |
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* 19-18: reserved |
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* 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, |
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* '10' 12K, '11' 16K. |
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* 15-14: reserved |
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* 13-12: IRQ destination; '00' none, '01' host driver (normal operation) |
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* 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) |
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* typical value 0x10 (about 1/2 msec) |
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* 3- 0: reserved |
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*/ |
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#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
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#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) |
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#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) |
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#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) |
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#define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) |
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#define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) |
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#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ |
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ |
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#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ |
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#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ |
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#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ |
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#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ |
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#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) |
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#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) |
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#define RX_RB_TIMEOUT (0x11) |
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) |
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) |
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#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) |
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) |
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) |
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) |
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) |
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#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) |
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) |
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) |
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/** |
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* Rx Shared Status Registers (RSSR) |
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* |
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* After stopping Rx DMA channel (writing 0 to |
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* FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll |
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* FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. |
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* |
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* Bit fields: |
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* 24: 1 = Channel 0 is idle |
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* |
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* FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV |
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* contain default values that should not be altered by the driver. |
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*/ |
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#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) |
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#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) |
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#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) |
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#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) |
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#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ |
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(FH_MEM_RSSR_LOWER_BOUND + 0x008) |
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#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) |
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#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 |
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#define FH_MEM_TB_MAX_LENGTH (0x00020000) |
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/* 9000 rx series registers */ |
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#define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ |
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#define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8) |
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/* Write index table */ |
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#define RFH_Q0_FRBDCB_WIDX 0xA08080 |
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#define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4) |
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/* Write index table - shadow registers */ |
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#define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 |
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#define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) |
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/* Read index table */ |
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#define RFH_Q0_FRBDCB_RIDX 0xA080C0 |
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#define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4) |
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/* Used list table */ |
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#define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ |
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#define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8) |
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/* Write index table */ |
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#define RFH_Q0_URBDCB_WIDX 0xA08180 |
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#define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4) |
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#define RFH_Q0_URBDCB_VAID 0xA081C0 |
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#define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4) |
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/* stts */ |
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#define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ |
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#define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) |
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#define RFH_Q0_ORB_WPTR_LSB 0xA08280 |
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#define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8) |
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#define RFH_RBDBUF_RBD0_LSB 0xA08300 |
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#define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8) |
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/** |
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* RFH Status Register |
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* |
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* Bit fields: |
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* |
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* Bit 29: RBD_FETCH_IDLE |
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* This status flag is set by the RFH when there is no active RBD fetch from |
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* DRAM. |
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* Once the RFH RBD controller starts fetching (or when there is a pending |
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* RBD read response from DRAM), this flag is immediately turned off. |
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* |
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* Bit 30: SRAM_DMA_IDLE |
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* This status flag is set by the RFH when there is no active transaction from |
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* SRAM to DRAM. |
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* Once the SRAM to DRAM DMA is active, this flag is immediately turned off. |
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* |
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* Bit 31: RXF_DMA_IDLE |
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* This status flag is set by the RFH when there is no active transaction from |
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* RXF to DRAM. |
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* Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. |
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*/ |
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#define RFH_GEN_STATUS 0xA09808 |
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#define RFH_GEN_STATUS_GEN3 0xA07824 |
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#define RBD_FETCH_IDLE BIT(29) |
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#define SRAM_DMA_IDLE BIT(30) |
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#define RXF_DMA_IDLE BIT(31) |
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/* DMA configuration */ |
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#define RFH_RXF_DMA_CFG 0xA09820 |
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#define RFH_RXF_DMA_CFG_GEN3 0xA07880 |
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/* RB size */ |
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#define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ |
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#define RFH_RXF_DMA_RB_SIZE_POS 16 |
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#define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS) |
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#define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS) |
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/* RB Circular Buffer size:defines the table sizes in RBD units */ |
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#define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ |
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#define RFH_RXF_DMA_RBDCB_SIZE_POS 20 |
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#define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS) |
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#define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ |
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#define RFH_RXF_DMA_MIN_RB_SIZE_POS 24 |
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#define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS) |
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#define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ |
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#define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ |
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#define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ |
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#define RFH_DMA_EN_ENABLE_VAL BIT(31) |
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#define RFH_RXF_RXQ_ACTIVE 0xA0980C |
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|
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#define RFH_GEN_CFG 0xA09800 |
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#define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) |
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#define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) |
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#define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) |
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#define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1 |
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#define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0 |
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/* the driver assumes everywhere that the default RXQ is 0 */ |
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#define RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 |
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#define RFH_GEN_CFG_VAL(_n, _v) FIELD_PREP(RFH_GEN_CFG_ ## _n, _v) |
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|
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/* end of 9000 rx series registers */ |
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|
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/* TFDB Area - TFDs buffer table */ |
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#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) |
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#define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) |
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#define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) |
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#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) |
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#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) |
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/** |
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* Transmit DMA Channel Control/Status Registers (TCSR) |
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* |
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* Device has one configuration register for each of 8 Tx DMA/FIFO channels |
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* supported in hardware (don't confuse these with the 16 Tx queues in DRAM, |
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* which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. |
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* |
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* To use a Tx DMA channel, driver must initialize its |
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* FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: |
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* |
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* FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
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* FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
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* |
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* All other bits should be 0. |
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* |
|
* Bit fields: |
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* 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, |
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* '10' operate normally |
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* 29- 4: Reserved, set to "0" |
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* 3: Enable internal DMA requests (1, normal operation), disable (0) |
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* 2- 0: Reserved, set to "0" |
|
*/ |
|
#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) |
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#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) |
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|
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/* Find Control/Status reg for given Tx DMA/FIFO channel */ |
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#define FH_TCSR_CHNL_NUM (8) |
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|
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/* TCSR: tx_config register values */ |
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#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
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(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) |
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#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ |
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(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) |
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#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ |
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(FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) |
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|
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#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) |
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|
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) |
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|
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) |
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|
|
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) |
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#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) |
|
#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) |
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|
|
#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) |
|
#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) |
|
#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) |
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|
|
#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) |
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#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) |
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|
|
/** |
|
* Tx Shared Status Registers (TSSR) |
|
* |
|
* After stopping Tx DMA channel (writing 0 to |
|
* FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll |
|
* FH_TSSR_TX_STATUS_REG until selected Tx channel is idle |
|
* (channel's buffers empty | no pending requests). |
|
* |
|
* Bit fields: |
|
* 31-24: 1 = Channel buffers empty (channel 7:0) |
|
* 23-16: 1 = No pending requests (channel 7:0) |
|
*/ |
|
#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) |
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#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) |
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|
|
#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) |
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|
|
/** |
|
* Bit fields for TSSR(Tx Shared Status & Control) error status register: |
|
* 31: Indicates an address error when accessed to internal memory |
|
* uCode/driver must write "1" in order to clear this flag |
|
* 30: Indicates that Host did not send the expected number of dwords to FH |
|
* uCode/driver must write "1" in order to clear this flag |
|
* 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA |
|
* command was received from the scheduler while the TRB was already full |
|
* with previous command |
|
* uCode/driver must write "1" in order to clear this flag |
|
* 7-0: Each status bit indicates a channel's TxCredit error. When an error |
|
* bit is set, it indicates that the FH has received a full indication |
|
* from the RTC TxFIFO and the current value of the TxCredit counter was |
|
* not equal to zero. This mean that the credit mechanism was not |
|
* synchronized to the TxFIFO status |
|
* uCode/driver must write "1" in order to clear this flag |
|
*/ |
|
#define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) |
|
#define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) |
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|
|
#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) |
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|
|
/* Tx service channels */ |
|
#define FH_SRVC_CHNL (9) |
|
#define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) |
|
#define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) |
|
#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ |
|
(FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) |
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|
|
#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) |
|
#define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) |
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|
|
/* Instruct FH to increment the retry count of a packet when |
|
* it is brought from the memory to TX-FIFO |
|
*/ |
|
#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) |
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|
|
#define RX_POOL_SIZE(rbds) ((rbds) - 1 + \ |
|
IWL_MAX_RX_HW_QUEUES * \ |
|
(RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC)) |
|
/* cb size is the exponent */ |
|
#define RX_QUEUE_CB_SIZE(x) ilog2(x) |
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|
|
#define RX_QUEUE_SIZE 256 |
|
#define RX_QUEUE_MASK 255 |
|
#define RX_QUEUE_SIZE_LOG 8 |
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|
|
/** |
|
* struct iwl_rb_status - reserve buffer status |
|
* host memory mapped FH registers |
|
* @closed_rb_num [0:11] - Indicates the index of the RB which was closed |
|
* @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed |
|
* @finished_rb_num [0:11] - Indicates the index of the current RB |
|
* in which the last frame was written to |
|
* @finished_fr_num [0:11] - Indicates the index of the RX Frame |
|
* which was transferred |
|
*/ |
|
struct iwl_rb_status { |
|
__le16 closed_rb_num; |
|
__le16 closed_fr_num; |
|
__le16 finished_rb_num; |
|
__le16 finished_fr_nam; |
|
__le32 __unused; |
|
} __packed; |
|
|
|
|
|
#define TFD_QUEUE_SIZE_MAX (256) |
|
#define TFD_QUEUE_SIZE_MAX_GEN3 (65536) |
|
/* cb size is the exponent - 3 */ |
|
#define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3) |
|
#define TFD_QUEUE_SIZE_BC_DUP (64) |
|
#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) |
|
#define TFD_QUEUE_BC_SIZE_GEN3 1024 |
|
#define IWL_TX_DMA_MASK DMA_BIT_MASK(36) |
|
#define IWL_NUM_OF_TBS 20 |
|
#define IWL_TFH_NUM_TBS 25 |
|
|
|
static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) |
|
{ |
|
return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF; |
|
} |
|
|
|
/** |
|
* enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits |
|
* @TB_HI_N_LEN_ADDR_HI_MSK: high 4 bits (to make it 36) of DMA address |
|
* @TB_HI_N_LEN_LEN_MSK: length of the TB |
|
*/ |
|
enum iwl_tfd_tb_hi_n_len { |
|
TB_HI_N_LEN_ADDR_HI_MSK = 0xf, |
|
TB_HI_N_LEN_LEN_MSK = 0xfff0, |
|
}; |
|
|
|
/** |
|
* struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor |
|
* |
|
* This structure contains dma address and length of transmission address |
|
* |
|
* @lo: low [31:0] portion of the dma address of TX buffer |
|
* every even is unaligned on 16 bit boundary |
|
* @hi_n_len: &enum iwl_tfd_tb_hi_n_len |
|
*/ |
|
struct iwl_tfd_tb { |
|
__le32 lo; |
|
__le16 hi_n_len; |
|
} __packed; |
|
|
|
/** |
|
* struct iwl_tfh_tb transmit buffer descriptor within transmit frame descriptor |
|
* |
|
* This structure contains dma address and length of transmission address |
|
* |
|
* @tb_len length of the tx buffer |
|
* @addr 64 bits dma address |
|
*/ |
|
struct iwl_tfh_tb { |
|
__le16 tb_len; |
|
__le64 addr; |
|
} __packed; |
|
|
|
/** |
|
* Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. |
|
* Both driver and device share these circular buffers, each of which must be |
|
* contiguous 256 TFDs. |
|
* For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes |
|
* For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes |
|
* |
|
* Driver must indicate the physical address of the base of each |
|
* circular buffer via the FH_MEM_CBBC_QUEUE registers. |
|
* |
|
* Each TFD contains pointer/size information for up to 20 / 25 data buffers |
|
* in host DRAM. These buffers collectively contain the (one) frame described |
|
* by the TFD. Each buffer must be a single contiguous block of memory within |
|
* itself, but buffers may be scattered in host DRAM. Each buffer has max size |
|
* of (4K - 4). The concatenates all of a TFD's buffers into a single |
|
* Tx frame, up to 8 KBytes in size. |
|
* |
|
* A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. |
|
*/ |
|
|
|
/** |
|
* struct iwl_tfd - Transmit Frame Descriptor (TFD) |
|
* @ __reserved1[3] reserved |
|
* @ num_tbs 0-4 number of active tbs |
|
* 5 reserved |
|
* 6-7 padding (not used) |
|
* @ tbs[20] transmit frame buffer descriptors |
|
* @ __pad padding |
|
*/ |
|
struct iwl_tfd { |
|
u8 __reserved1[3]; |
|
u8 num_tbs; |
|
struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; |
|
__le32 __pad; |
|
} __packed; |
|
|
|
/** |
|
* struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD) |
|
* @ num_tbs 0-4 number of active tbs |
|
* 5 -15 reserved |
|
* @ tbs[25] transmit frame buffer descriptors |
|
* @ __pad padding |
|
*/ |
|
struct iwl_tfh_tfd { |
|
__le16 num_tbs; |
|
struct iwl_tfh_tb tbs[IWL_TFH_NUM_TBS]; |
|
__le32 __pad; |
|
} __packed; |
|
|
|
/* Keep Warm Size */ |
|
#define IWL_KW_SIZE 0x1000 /* 4k */ |
|
|
|
/* Fixed (non-configurable) rx data from phy */ |
|
|
|
/** |
|
* struct iwlagn_schedq_bc_tbl scheduler byte count table |
|
* base physical address provided by SCD_DRAM_BASE_ADDR |
|
* For devices up to 22000: |
|
* @tfd_offset 0-12 - tx command byte count |
|
* 12-16 - station index |
|
* For 22000: |
|
* @tfd_offset 0-12 - tx command byte count |
|
* 12-13 - number of 64 byte chunks |
|
* 14-16 - reserved |
|
*/ |
|
struct iwlagn_scd_bc_tbl { |
|
__le16 tfd_offset[TFD_QUEUE_BC_SIZE]; |
|
} __packed; |
|
|
|
/** |
|
* struct iwl_gen3_bc_tbl scheduler byte count table gen3 |
|
* For AX210 and on: |
|
* @tfd_offset: 0-12 - tx command byte count |
|
* 12-13 - number of 64 byte chunks |
|
* 14-16 - reserved |
|
*/ |
|
struct iwl_gen3_bc_tbl { |
|
__le16 tfd_offset[TFD_QUEUE_BC_SIZE_GEN3]; |
|
} __packed; |
|
|
|
#endif /* !__iwl_fh_h__ */
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|
|